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3-2

Reference Generator, V

ROUT

 and V

RIN

The HI5905 has an internal reference voltage generator,
therefore no external reference voltage is required. The eval
board, however, offers the ability to use the internal or an
external reference. V

ROUT

must be connected to V

RIN

when

using the internal reference. Internal to the converter, two
reference voltages of 1.3V and 3.3V are generated making
for a fully differential analog input signal range of

±

2V.

The HI5905 can be used with an external reference. The
converter requires only one external reference voltage
connected to the V

RIN

 pin with V

ROUT

 left open. The

evaluation board is configured with V

ROUT

 connected to V

RIN

through a 0

resistor, R4. If it is desired to evaluate the

performance of the converter utilizing an externally provided
reference voltage, R4 can be removed and the alternate
reference voltage can be brought in through twisted pair wire or
coaxial cable. The latter would be the recommended method
since it would provide the greatest immunity to externally
coupled noise voltages. In order to minimize overall converter
noise it is recommended that adequate high frequency
decoupling be provided at the reference input pin, V

RIN

.

Analog Input

The fully differential analog input of the HI5905 A/D can be
configured in various ways depending on the signal source
and the required level of performance.

Differential Analog Input Configuration

A fully differential connection (Figure 1) will yield the best
performance from the HI5905 A/D converter. Since the HI5905
is powered off a 5V supply, the analog input must be
biased so it lies within the analog input common mode voltage
range of 1.0V to 4.0V. Figure 2 illustrates the differential analog
input common mode voltage range that the converter will
accommodate. The performance of the ADC does not change
significantly with the value of the common mode voltage.

A 2.3V DC bias voltage source, V

DC

, half way between the top

and bottom internally generated reference voltages, is made
available to the user to help simplify circuit design when using a
differential input. This low output impedance voltage source is
not designed to be a reference but makes an excellent bias
source and stays within the analog input common mode
voltage range over temperature. The DC voltage source has a
temperature coefficient of about +200ppm/

o

C.

The difference between the converter's two internally
generated voltage references is 2V. For the AC coupled
differential input (Figure 1), if V

IN

is a 2V

P-P

sinewave with -V

IN

being 180 degrees out of phase with V

IN

, the converter will be

at positive full scale when the V

IN

+ input is at V

DC

+ 1V and the

V

IN

- input is at V

DC

 - 1V (V

IN

+ - V

IN

- = +2V). Conversely, the

ADC will be at negative full scale when the V

IN

+ input is equal

to V

DC

 - 1V and V

IN

- is at V

DC

 + 1V (V

IN

+ - V

IN

- = -2V).

It should be noted that overdriving the analog input beyond
the

±

2.0V fullscale input voltage range will not damage the

converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.

Evaluation Board Layout and
Power Supplies

The HI5905 evaluation board is a four layer board with a
layout optimized for the best performance of the ADC. This
application note includes an electrical schematic of the
evaluation board, a component parts list, a component
placement layout drawing and reproductions of the various
board layers used in the board stack-up. The user should
feel free to copy the layout in their application. Refer to the
component layout and the evaluation board electrical
schematic for the following discussions.

The HI5905 monolithic A/D converter has been designed
with separate analog and digital supply and ground pins to
keep digital noise out of the analog signal path. The
evaluation board provides separate low impedance analog
and digital ground planes on layer 2. Since the analog and
digital ground planes are connected together at a single
point where the power supplies enter the board, DO NOT tie
them together back at the power supplies.

V

IN

+

V

DC

V

IN

-

HI5905

V

IN

-V

IN

FIGURE 1. AC COUPLED DIFFERENTIAL INPUT

FIGURE 2A.

FIGURE 2B.

FIGURE 2C.

FIGURE 2. DIFFERENTIAL ANALOG INPUT COMMON MODE

VOLTAGE RANGE

V

IN

+

V

IN

-

2.0V

P-P

VDC = 4.0V

+5V

+5V

V

IN

+

V

IN

-

2.0V

P-P

1.0V < VDC < 4.0V

0V

V

IN

+

V

IN

-

2.0V

P-P

VDC = 1.0V

0V

Application Note 9785

Summary of Contents for HI5905EVAL2

Page 1: ...erter is adjustable by way of a potentiometer This allows the effects of sample clock duty cycle on the HI5905 to be observed The analog input signal is also connected through an SMA type RF connector...

Page 2: ...input This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature The DC...

Page 3: ...the best performance from the ADC and to allow the user to investigate the effects of expected duty cycle variations on the performance of the converter The HI5905 clock input trigger level is approx...

Page 4: ...ing the ADC analog input is bandpass filtered to improve the harmonic distortion of the analog input signal The comparator on the evaluation board will convert the sine wave CLK input signal to a squa...

Page 5: ...RTION 2HD vs INPUT FREQUENCY FIGURE 9 SNR vs INPUT FREQUENCY FIGURE 10 THIRD HARMONIC DISTORTION 3HD vs INPUT FREQUENCY 100 INPUT FREQUENCY MHz 10 1 7 12 11 10 9 8 ENOB BITS 100 INPUT FREQUENCY MHz 10...

Page 6: ...3 6 Appendix A Board Layout FIGURE 11 HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT NEAR SIDE FIGURE 12 HI5905EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE LAYER 1 Application Note 9785...

Page 7: ...3 7 FIGURE 13 HI5905EVAL2 EVALUATION BOARD GROUND PLANE LAYER LAYER 2 FIGURE 14 HI5905EVAL2 EVALUATION BOARD POWER PLANE LAYER LAYER 3 Appendix A Board Layout Continued Application Note 9785...

Page 8: ...3 8 FIGURE 15 HI5905EVAL2 EVALUATION BOARD COMPONENT FAR SIDE LAYER 4 FIGURE 16 HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT FAR SIDE Appendix A Board Layout Continued Application Note 9785...

Page 9: ...D4 D3 D2 D1 D0 D11 D12 D0 D13 CLK 5VD 5VD2 4 7 F 0 1 F 0 1 F 0 1 F 0 4 7 F C18 C17 C14 0 1 F 0 1 F P1 FB6 4 99K 4 99K 4 7 F C16 C15 0 1 F 4 7 F C12 C11 0 1 F VIN VDC VIN 17 18 19 20 24 25 26 HI5905 N...

Page 10: ...R15 R13 C1 CLK CLK 1 5 2 3 8 7 4 6 V V NC V V U6 C42 R17 C43 C22 5VA 5VA 5VA 5VA OPA628AU OPA628U MAX9686BCSA 0 1 F 56 2 0 1 F A R 22 1 499 0 1 F 4 7 F 249 0 1 F 4 7 F 100 0 100 0 1 F 4 7 F 0 1 F 0 1...

Page 11: ...A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 P2A C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 P2C D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D...

Page 12: ...FB3 FB7 FB4 FB5 AGND DGND DGND DGND DGND AGND AND DGND TIE TOGETHER AT A SINGLE POINT WHERE ENTER THE PWB THE POWER SUPPLIES 4 7 F 0 1 F 4 7 F 4 7 F 4 7 F 4 7 F 4 7 F 0 1 F 0 1 F 0 1 F 0 1 F 0 1 F E1...

Page 13: ...a 4 bit flash converter Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase Each individual sub converter clock signal is offset by 180 degrees f...

Page 14: ...ch and is presented in offset binary format CH CS CS VIN VOUT VOUT VIN 1 1 2 1 1 CH 1 1 FIGURE 17 ANALOG INPUT SAMPLE AND HOLD NOTES 1 SN N th sampling period 2 HN N th holding period 3 BM N M th stag...

Page 15: ...LASH 4 BIT DAC 4 BIT FLASH STAGE 5 STAGE 4 STAGE 1 AVCC AGND DVCC1 DGND1 DIGITAL DELAY D13 MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 4 BIT FLASH 4 BIT DAC AND DIGITAL ERROR CORRECTION CLOCK REF DVCC2...

Page 16: ...DESCRIPTION 1 NC No Connection 2 NC No Connection 3 DGND1 Digital Ground 4 NC No Connection 5 AVCC Analog Supply 5 0V 6 AGND Analog Ground 7 NC No Connection 8 NC No Connection 9 VIN Positive Analog I...

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