3-1
TM
AN9785
HI5905EVAL2 Evaluation Board User’s Manual
Description
The HI5905EVAL2 evaluation board allows the circuit
designer to evaluate the performance of the Intersil HI5905
monolithic 14-bit, 5MSPS analog-to-digital converter (ADC).
As shown in the Evaluation Board Functional Block Diagram,
the evaluation board includes sample clock generation
circuitry, a single-ended to differential analog input amplifier
configuration and digital data output latches/buffers. The
buffered digital data outputs are conveniently provided for
easy interfacing to a ribbon connector or logic probes. In
addition, the evaluation board includes some prototyping area
for the addition of user designed custom interfaces or circuits.
The sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2. This
input is AC-coupled and terminated in 50
Ω
allowing for
connection to most laboratory signal generators. In addition,
the duty cycle of the clock driving the A/D converter is
adjustable by way of a potentiometer. This allows the effects
of sample clock duty cycle on the HI5905 to be observed.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input amplifier. This input is AC-coupled
and terminated in 50
Ω
allowing for connection to most
laboratory signal generators. Also, provisions for a
differential RC lowpass filter is incorporated on the output of
the differential amplifier to limit the broadband noise going
into the HI5905 converter.
The digital data output latches/buffers consist of a pair of
74ALS574A D-type flip-flops. With this digital output
configuration the digital output data transitions seen at the
I/O connector are essentially time aligned with the rising
edge of the sampling clock.
Evaluation Board Functional Block Diagram
CLK IN
+5V
D
-5V
D
V
REFOUT
V
REFIN
V
IN
-
G = +1
TTL COMPARATOR
14
CLOCK
DIGITAL
DGND
AGND
D
0
-D
13
HI5905
ANALOG
50
Ω
+5V
D
-5V
D
+5V
A
-5V
A
50
Ω
OUT
DATA
V
IN
+
CLK
IN
OUT
14
(CLK)
(D0 - D13)
G = -1
J2
J1
D
>
Q
Application Note
January 1999
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
©
Intersil Corporation 2000
