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Intersil HI5905EVAL2, User Manual

The Intersil HI5905EVAL2 is a high-performance evaluation board for testing and configuring the HI5905 precision voltage reference. For detailed instructions on how to set up and utilize this product, users can access the free User Manual available for download from manualshive.com. Get started with your evaluation today!

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FIGURE 15. HI5905EVAL2 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4)

FIGURE 16. HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT (FAR SIDE)

Appendix A Board Layout

 (Continued)

Application Note 9785

Summary of Contents for HI5905EVAL2

Page 1: ...erter is adjustable by way of a potentiometer This allows the effects of sample clock duty cycle on the HI5905 to be observed The analog input signal is also connected through an SMA type RF connector...

Page 2: ...input This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature The DC...

Page 3: ...the best performance from the ADC and to allow the user to investigate the effects of expected duty cycle variations on the performance of the converter The HI5905 clock input trigger level is approx...

Page 4: ...ing the ADC analog input is bandpass filtered to improve the harmonic distortion of the analog input signal The comparator on the evaluation board will convert the sine wave CLK input signal to a squa...

Page 5: ...RTION 2HD vs INPUT FREQUENCY FIGURE 9 SNR vs INPUT FREQUENCY FIGURE 10 THIRD HARMONIC DISTORTION 3HD vs INPUT FREQUENCY 100 INPUT FREQUENCY MHz 10 1 7 12 11 10 9 8 ENOB BITS 100 INPUT FREQUENCY MHz 10...

Page 6: ...3 6 Appendix A Board Layout FIGURE 11 HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT NEAR SIDE FIGURE 12 HI5905EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE LAYER 1 Application Note 9785...

Page 7: ...3 7 FIGURE 13 HI5905EVAL2 EVALUATION BOARD GROUND PLANE LAYER LAYER 2 FIGURE 14 HI5905EVAL2 EVALUATION BOARD POWER PLANE LAYER LAYER 3 Appendix A Board Layout Continued Application Note 9785...

Page 8: ...3 8 FIGURE 15 HI5905EVAL2 EVALUATION BOARD COMPONENT FAR SIDE LAYER 4 FIGURE 16 HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT FAR SIDE Appendix A Board Layout Continued Application Note 9785...

Page 9: ...D4 D3 D2 D1 D0 D11 D12 D0 D13 CLK 5VD 5VD2 4 7 F 0 1 F 0 1 F 0 1 F 0 4 7 F C18 C17 C14 0 1 F 0 1 F P1 FB6 4 99K 4 99K 4 7 F C16 C15 0 1 F 4 7 F C12 C11 0 1 F VIN VDC VIN 17 18 19 20 24 25 26 HI5905 N...

Page 10: ...R15 R13 C1 CLK CLK 1 5 2 3 8 7 4 6 V V NC V V U6 C42 R17 C43 C22 5VA 5VA 5VA 5VA OPA628AU OPA628U MAX9686BCSA 0 1 F 56 2 0 1 F A R 22 1 499 0 1 F 4 7 F 249 0 1 F 4 7 F 100 0 100 0 1 F 4 7 F 0 1 F 0 1...

Page 11: ...A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 P2A C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 P2C D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D...

Page 12: ...FB3 FB7 FB4 FB5 AGND DGND DGND DGND DGND AGND AND DGND TIE TOGETHER AT A SINGLE POINT WHERE ENTER THE PWB THE POWER SUPPLIES 4 7 F 0 1 F 4 7 F 4 7 F 4 7 F 4 7 F 4 7 F 0 1 F 0 1 F 0 1 F 0 1 F 0 1 F E1...

Page 13: ...a 4 bit flash converter Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase Each individual sub converter clock signal is offset by 180 degrees f...

Page 14: ...ch and is presented in offset binary format CH CS CS VIN VOUT VOUT VIN 1 1 2 1 1 CH 1 1 FIGURE 17 ANALOG INPUT SAMPLE AND HOLD NOTES 1 SN N th sampling period 2 HN N th holding period 3 BM N M th stag...

Page 15: ...LASH 4 BIT DAC 4 BIT FLASH STAGE 5 STAGE 4 STAGE 1 AVCC AGND DVCC1 DGND1 DIGITAL DELAY D13 MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 4 BIT FLASH 4 BIT DAC AND DIGITAL ERROR CORRECTION CLOCK REF DVCC2...

Page 16: ...DESCRIPTION 1 NC No Connection 2 NC No Connection 3 DGND1 Digital Ground 4 NC No Connection 5 AVCC Analog Supply 5 0V 6 AGND Analog Ground 7 NC No Connection 8 NC No Connection 9 VIN Positive Analog I...

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