3-19
Signal Descriptions
Bus 0 to Bus 7 (Data Bus)
8-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor,
and I/O devices.
N0 to N2 (I/O Control Lines)
Activated by an I/O instruction to signal the I/O control logic of
a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device selec-
tion codes to the I/O devices (independently or combined with
the memory byte on the data bus when an I/O instruction is
being executed). The N bits are low at all times except when
an I/O instruction is being executed. During this time their
state is the same as the corresponding bits in the N register.
The direction of data flow is defined in the I/O instruction by bit
N3 (internally) and is indicated by the level of the MRD signal.
MRD = V
CC
: Data from I/O to CPU and Memory
MRD = V
SS
: Data from Memory to I/O
EF1 to EF4 (4 Flags)
These inputs enable the I/O controllers to transfer status
information to the processor. The levels can be tested by the
conditional branch instructions. They can be used in con-
junction with the INTERRUPT request line to establish inter-
rupt priorities. These flags can also be used by I/O devices
to “call the attention” of the processor, in which case the pro-
gram must routinely test the status of these flag(s). The
flag(s) are sampled at the beginning of every S1 cycle.
FIGURE 21. CDP1802BC MINIMUM OUTPUT LOW (SINK)
CURRENT CHARACTERISTICS
FIGURE 22. TYPICAL CHANGE IN PROPAGATION DELAY AS A
FUNCTION OF A CHANGE IN LOAD CAPACITANCE
FOR ALL TYPES
NOTE: IDLE = “00” AT M(0000), BRANCH = “3707” AT M(8107), CL = 50pF
FIGURE 23. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE
INSTRUCTION FOR ALL TYPES
Performance Curves
(Continued)
V
GS
, GATE-TO-SOURCE = 5V
T
A
= -40
o
C TO +85
o
C
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
I
OL
, OUT
P
UT
L
O
W (
S
INK)
CURRENT
(
m
A)
0
1
2
3
4
5
5
10
20
150
125
100
75
50
25
0
25
50
100
150
200
∆
t
PL
H
,
∆
t
PH
L
,
∆
PROP
AGA
T
IO
N DEL
A
Y
TI
M
E
(n
s)
∆
C
L
,
∆
LOAD CAPACITANCE (pF)
T
A
= 25
o
C
V
CC
= V
DD
= 10V
V
CC
= V
DD
= 5V
V
CC
= V
DD
= 5V
V
CC
= V
DD
= 10V
∆
t
PLH
∆
t
PHL
NOTE: ANY OUTPUT EXCEPT XTAL
T
A
= 25
o
C
P
D
, T
Y
P
ICAL
PO
WE
R
DISSIP
A
T
ION
F
O
R CDP1
8
0
2
D (
m
W)
f
CL
, CLOCK INPUT FREQUENCY (MHz)
0.01
0.1
1
10
0.1
1
10
100
1000
V
CC
= V
DD
= 10V
BRANCH
IDLE
V
CC
= V
DD
= 5V
CDP1802A, CDP1802AC, CDP1802BC
