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Intersil CDP1802ACD, Manual

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Intersil CDP1802ACD Manual Download Page 12

3-14

FIGURE 8. MEMORY READ CYCLE TIMING WAVEFORMS

FIGURE 9. LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS

Machine Cycle Timing Waveforms

(Propagation Delays Not Shown)  (Continued)

MEMORY READ CYCLE

MEMORY READ CYCLE

MEMORY READ CYCLE

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

FETCH (S0)

EXECUTE

MEMORY

OUTPUT

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

VALID
OUTPUT

MRD

MWR (HIGH)

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

VALID
OUTPUT

MEMORY

OUTPUT

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

VALID
OUTPUT

MEMORY READ CYCLE

MEMORY READ CYCLE

MEMORY READ CYCLE

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

EXECUTE (S1)

FETCH (S0)

MRD

MWR (HIGH)

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

VALID OUTPUT

CDP1802A, CDP1802AC, CDP1802BC

Summary of Contents for CDP1802ACD

Page 1: ...m flexibility and minimum cost can be realized The 1800 series CPU also provides a synchro nous interface to memories and external controllers for I O devices and minimizes the cost of interface contr...

Page 2: ...TPA TPB MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 EF1 EF2 EF3 EF4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 SC0 MRD BUS 7 BUS 6 B...

Page 3: ...F 1 R F 0 R E 0 REGISTER ARRAY 8 BIT BIDIRECTIONAL DATA BUS LATCH AND DECODE R X T P I N N1 N0 N2 I O COMMANDS BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 TO INSTRUCTION DECODE CONTROL AND TIMING...

Page 4: ...ion is not implied Recommended Operating Conditions TA 40oC to 85oC For maximum reliability operating conditions should be selected so that operation is always within the following ranges PARAMETER TE...

Page 5: ...0 5 5 0 0 1 0 0 1 V Low Level VOL 0 10 10 0 0 1 V Output Voltage 0 5 5 4 9 5 4 9 5 V High Level VOH 0 10 10 9 9 10 V Input Low Voltage VIL 0 5 4 5 5 1 5 1 5 V 0 5 4 5 5 10 1 V 1 9 10 3 V Input High Vo...

Page 6: ...850 475 525 ns 5 10 400 600 ns 10 10 300 400 ns Clock to Memory Low Address Byte Valid tPLH tPHL 5 5 250 350 175 250 ns 5 10 150 250 ns 10 10 100 150 ns Clock to MRD tPHL 5 5 200 300 175 275 ns 5 10 1...

Page 7: ...s 5 10 100 125 ns 10 10 75 100 ns DMA Set Up tSU 5 5 0 30 0 30 ns 5 10 0 20 ns 10 10 0 10 ns DMA Hold tH Note 2 5 5 150 250 100 150 ns 5 10 100 200 ns 10 10 75 125 ns Interrupt Set Up tSU 5 5 75 0 75...

Page 8: ...NS CDP1802A CDP1802AC CDP1802BC UNITS VCC V VDD V MIN NOTE 1 TYP MIN NOTE 1 TYP High Order Memory Address Byte Set Up to TPA Time tSU 5 5 2T 550 2T 400 2T 325 2T 275 ns 5 10 2T 350 2T250 ns 10 10 2T 2...

Page 9: ...s as a function of T T 1 fCLOCK at TA 40 to 85oC Except as Noted PARAMETERS SYMBOL TEST CONDITIONS CDP1802A CDP1802AC CDP1802BC UNITS VCC V VDD V MIN NOTE 1 TYP MIN NOTE 1 TYP Timing Waveforms FIGURE...

Page 10: ...A INTERRUPT EF 1 4 WAIT CLEAR REQUEST REQUEST BUS TO CPU N0 N1 N2 STATE DATA FROM CPU TO BUS MEMORY WRITE CYCLE MEMORY ADDRESS READ CYCLE CODES CYCLE tW 00 10 20 30 40 50 60 70 00 01 11 21 31 41 51 61...

Page 11: ...RESS HIGH ADD MEMORY READ CYCLE NON MEMORY CYCLE MEMORY READ CYCLE INSTRUCTION MRD MWR HIGH MEMORY OUTPUT FETCH S0 EXECUTE S1 FETCH S0 EXECUTE ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID OUTPUT DON T C...

Page 12: ...S0 EXECUTE S1 FETCH S0 EXECUTE MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID OUTPUT MRD MWR HIGH DON T CARE OR INTERNAL DELAYS HIGH IMPEDANCE STATE VALID OUTPUT MEMORY OUTPUT ALLOWABLE MEMO...

Page 13: ...FROM INPUT DEVICE N 9 F EXECUTE S1 CYCLE n 1 CYCLE n FETCH S0 NOTE 1 DON T CARE OR INTERNAL DELAYS HIGH IMPEDANCE STATE NOTE 1 USER GENERATED SIGNAL 0 CLOCK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 TPA TPB MA...

Page 14: ...RNAL DELAYS HIGH IMPEDANCE STATE NOTE 1 USER GENERATED SIGNAL VALID DATA FROM INPUT DEVICE CYCLE n FETCH S0 CYCLE n 1 EXECUTE S1 CYCLE n 2 DMA S2 VALID OUTPUT 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4...

Page 15: ...TERRUPT S3 EXECUTE S1 FETCH S0 MRD MWR INTERRUPT MEMORY OUTPUT VALID OUTPUT NOTE 1 MEMORY READ CYCLE MEMORY READ WRITE NON MEMORY CYCLE OR NON MEMORY CYCLE DON T CARE OR INTERNAL DELAYS HIGH IMPEDANCE...

Page 16: ...200 t THL t TLH TRANSITION TIME ns CL LOAD CAPACITANCE pF TA 25o C VCC VDD 10V VCC VDD 5V VCC VDD 5V VCC VDD 10V tTLH tTHL VGS GATE TO VOLTAGE 5V TA AMBIENT TEMPERATURE 40o C TO 85o C 10V VDS DRAIN T...

Page 17: ...he conditional branch instructions They can be used in con junction with the INTERRUPT request line to establish inter rupt priorities These flags can also be used by I O devices to call the attention...

Page 18: ...common data input and output bus If a memory does not have a three state high impedance output MRD is useful for driving memory bus separator gates It is also used to indicate the direction of data t...

Page 19: ...he program counter for the user s interrupt servicing routine After reset and during a DMA operation R 0 is used as the program counter At all other times the register designated as pro gram counter i...

Page 20: ...a Schmitt trig gered input see Figure 24 Pause Stops the internal CPU timing generator on the first negative high to low transition of the input clock The oscillator contin ues to operate but subsequ...

Page 21: ...A X AND DECREMENT STXD 73 D M R X R X 1 R X REGISTER OPERATIONS INCREMENT REG N INC 1N R N 1 R N DECREMENT REG N DEC 2N R N 1 R N INCREMENT REG X IRX 60 R X 1 R X GET LOW REG N GLO 8N R N 0 D PUT LOW...

Page 22: ...T DF DF D SUBTRACT D WITH BORROW IMMEDIATE SDBl 7D M R P D Not DF DF D R P 1 R P SUBTRACT MEMORY SM F7 D M R X DF D SUBTRACT MEMORY IMMEDIATE SMl FF D M R P DF D R P 1 R P SUBTRACT MEMORY WITH BORROW...

Page 23: ...NCH IF DF 1 LBDF C3 lF DF 1 M R P R P 1 M R P 1 R P 0 ELSE R P 2 R P LONG BRANCH IF DF 0 LBNF CB IF DF 0 M R P R P 1 M R P 1 R P 0 ELSE R P 2 R P LONG BRANCH IF Q 1 LBQ C1 IF Q 1 M R P R P 1 M R P 1 R...

Page 24: ...R X 1 R X N LINES 4 OUTPUT 5 OUT 5 65 M R X BUS R X 1 R X N LINES 5 OUTPUT 6 OUT 6 66 M R X BUS R X 1 R X N LINES 6 OUTPUT 7 OUT 7 67 M R X BUS R X 1 R X N LINES 7 INPUT 1 INP 1 69 BUS M R X BUS D N...

Page 25: ...first byte specifies the condition to be tested and the second specifies the branching address The short branch instruction can a Branch unconditionally b Test for D 0 or D 0 c Test for DF 0 or DF 1 d...

Page 26: ...5 0 F STR D MRN D RN 1 0 0 Fig 7 6 0 IRX RX 1 RX MRX RX 0 1 0 Fig 7 6 1 OUT 1 MRX BUS RX 1 RX MRX RX 0 1 1 Fig 11 2 OUT 2 2 Fig 11 3 OUT 3 3 Fig 11 4 OUT 4 4 Fig 11 5 OUT 5 5 Fig 11 6 OUT 6 6 Fig 11...

Page 27: ...0 1 0 Fig 9 2 Not Taken RP 1 RP M RP 1 RP 1 0 1 0 Fig 9 S1 1 5 6 7 C D E F Long Skip Taken RP 1 RP MRP RP 0 1 0 Fig 9 2 Taken RP 1 RP M RP 1 RP 1 0 1 0 Fig 9 S1 1 Not Taken No Operation MRP RP 0 1 0 F...

Page 28: ...rip ple or ground noise any of these conditions must not cause VDD VSS to exceed the absolute maximum rating Input Signals To prevent damage to the input protection circuit input signals should never...

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