3-15
FIGURE 10. INPUT CYCLE TIMING WAVEFORMS
FIGURE 11. OUTPUT CYCLE TIMING WAVEFORMS
Machine Cycle Timing Waveforms
(Propagation Delays Not Shown) (Continued)
CLOCK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
MEMORY
OUTPUT
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
TPA
TPB
MACHINE
INSTRUCTION
MRD
N0 - N2
DATA
MWR
CYCLE
BUS
MEMORY READ CYCLE
MEMORY WRITE CYCLE
VALID DATA FROM INPUT DEVICE
N = 9 - F
EXECUTE (S1)
CYCLE (n + 1)
CYCLE n
FETCH (S0)
NOTE 1
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
(NOTE 1)
USER GENERATED SIGNAL
0
CLOCK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
TPA
TPB
MACHINE
INSTRUCTION
CYCLE
EXECUTE (S1)
CYCLE (n + 1)
CYCLE n
FETCH (S0)
DATA BUS
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
VALID DATA FROM MEMORY
ALLOWABLE MEMORY ACCESS
MEMORY READ CYCLE
MEMORY READ CYCLE
MRD
N0 - N2
DATA STROBE
(MRD
•
TPB
•
N)
NOTE 1
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
(NOTE 1)
USER GENERATED SIGNAL
0
N = 1 - 9
CDP1802A, CDP1802AC, CDP1802BC
