3-16
FIGURE 12. DMA IN CYCLE TIMING WAVEFORMS
FIGURE 13. DMA OUT CYCLE TIMING WAVEFORMS
Machine Cycle Timing Waveforms
(Propagation Delays Not Shown) (Continued)
CLOCK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
TPA
TPB
MACHINE
INSTRUCTION
DMA-IN
MRD
MWR
MEMORY
DATA BUS
CYCLE
OUTPUT
4
5
6
7
NOTE 1
MEMORY READ CYCLE
MEMORY READ, WRITE
MEMORY WRITE CYCLE
OR NON-MEMORY CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
(NOTE 1)
USER GENERATED SIGNAL
VALID DATA FROM INPUT DEVICE
CYCLE n
FETCH (S0)
CYCLE (n+1)
EXECUTE (S1)
CYCLE (n+2)
DMA (S2)
VALID OUTPUT
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
CLOCK
TPA
TPB
MACHINE
CYCLE
INSTRUCTION
DMA OUT
MRD
MWR
MEMORY
OUTPUT
DATA
STROBE
(S2
•
TPB)
CYCLE n
CYCLE (n + 1)
CYCLE (n + 2)
DMA (S2)
EXECUTE (S1)
FETCH (S0)
VALID OUTPUT
VALID DATA FROM MEMORY
NOTE 1
MEMORY READ CYCLE
MEMORY READ, WRITE
MEMORY READ CYCLE
OR NON-MEMORY CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
USER GENERATED SIGNAL
(NOTE 1)
(NOTE 1)
CDP1802A, CDP1802AC, CDP1802BC
