Intel® Server Chassis SR1475 / Intel® Server System SR1475NH1-E
Revision 1.0
- 63 -
6.26 Common Mode Noise
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency
band of 10 Hz to 20 MHz.
1. The measurement shall be made across a 100
Ω
resistor between each of the
DC outputs, including ground at the DC power connector and chassis ground
(power subsystem enclosure).
2. The test set-up shall use a FET probe such as Tektronix* model P6046 or
equivalent.
6.27 Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the table below.
This is measured over a bandwidth of 10 Hz to 20 MHz at the power supply output connectors.
A 10
μ
F tantalum capacitor in parallel with a 0.1
μ
F ceramic capacitor is placed at the point of
measurement.
Table 38. Ripple and Noise
+3.3V
+5V
+12V
-12V
+5VSB
50mVp-p 50mVp-p 120mVp-p 120mVp-p 50mVp-p
6.28 Soft Starting
The power supply shall contain a control circuit which provides a monotonic soft start for its
outputs without overstress of the AC line or any power supply components at any specified AC
line or load conditions.
6.29 Zero Load Stability Requirements
When the power sub-system operates in a no load condition, it does not need to meet the
output regulation specification, but it must operate without any tripping of over-voltage or other
fault circuitry. When the power sub-system is subsequently loaded, it must begin to regulate
and source current without fault.
6.30 Timing Requirements
These are the timing requirements for the power supply operation. The output voltages must
rise from 10% to within regulation limits (Tvout_rise) within 5 to 70 ms, except for 5VSB; it is
allowed to rise from 1.0 to 25 ms. The +3.3V, +5V and +12V output voltages should start to rise
approximately at the same time. All outputs must rise monotonically. The 5V output needs to
be greater than the 3.3 V output during any point of the voltage rise condition. The +5V output
must never be greater than the +3.3V output by more than 2.25V. Each output voltage shall
reach regulation within 50 ms (Tvout_on) of each other during turn on of the power supply.
Each output voltage shall fall out of regulation within 400 ms (Tvout_off) of each other during
Summary of Contents for SR1475
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