Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification Download Page 46

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64-bit Intel

Xeon

Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Documentation Changes

Note:

Documentation changes for

IA-32 Intel

Architecture Software Developer’s Manual,

Volumes 1,

2A, 2B, and 3 will be posted in the separate document

IA-32 Intel

Architecture Software

Developer’s Manual Documentation Changes

. Follow the link below to become familiar with this

file.

http://developer.intel.com/design/pentium4/specupdt/252046.htm

There are no new Documentation Changes

for this revision of the

64-bit Intel

Xeon

Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update.

The Documentation Changes listed in this section apply to the following documents:

64-bit Intel

Xeon

Processor with 2 MB L2 Cache Datasheet

(Document Number 306249)

Link: http://developer/design/xeon/datashts/306249.htm

Intel

Xeon

Processor with 800 MHz System Bus Datasheet

(Document Number 302355)

Link: http://developer/design/xeon/datashts/302355.htm

All Documentation Changes will be incorporated into a future version of the appropriate Intel
Xeon processor documentation.

Summary of Contents for SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor

Page 1: ...ocument Number 302402 022 Notice The 64 bit Intel Xeon processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions may contain design defects or errors known as errata which may cause the produc...

Page 2: ...systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of an...

Page 3: ...Bus 3 1 MB and 2 MB L2 Cache Versions Specification Update Contents Revision History 5 Preface 6 Identification Information 7 Summary Table of Changes 12 Errata 19 Specification Changes 44 Specificat...

Page 4: ...4 64 bit Intel Xeon Processor with 800 MHz System Bus 1 MB and 2 MB L2 Cache Versions Specification Update...

Page 5: ...S78 S79 added additional text to Mixed Steppings In DP Systems chapter January 2005 009 Added 2 MB L2 cache version of the 64 bit Intel Xeon processor with 800 MHz system bus added errata S80 S81 add...

Page 6: ...cribed in the processor identification information table Care should be taken to read all notes associated with each S Spec number Errata are design defects or errors Errata may cause the processor s...

Page 7: ...ngs 604 pin FC mPGA4 Package The 64 bit Intel Xeon Processor with 800 MHz System Bus 1 MB and 2 MB L2 cache versions can be identified by the following values Figure 1 Top Side Processor Marking Examp...

Page 8: ...and 2 MB L2 Cache Versions Identification Information Sheet 1 of 2 S Spec Core Stepping CPUID Core Freq GHz Data Bus Freq MHz L2 Cache Size Processor Package Revision Package and Revision Notes SL7DV...

Page 9: ...A4 package 2 3 4 6 SL7ZD N 0 0F43h 3 40 800 2 MB 01 604 pin micro PGA with 42 5 x 42 5 mm FC PGA4 package 2 3 4 6 SL7ZE N 0 0F43h 3 20 800 2 MB 01 604 pin micro PGA with 42 5 x 42 5 mm FC PGA4 package...

Page 10: ...to perform validation of system configurations with mixed frequencies cache sizes or voltages and that those efforts are an acceptable option to our customers customers would be fully responsible for...

Page 11: ...ociated with mixing these steppings 3 TBD No issues are expected however further investigation is required to fully validate this DP solution Table 3 DP Platform Population Matrix for the 64 bit Intel...

Page 12: ...either new or modified from the previous version of this document Each Specification Update item will be prefixed with a capital letter to distinguish the product The key below details the letters tha...

Page 13: ...ent counting of x87 loads may not work as expected S9 X X X X X No Fix System bus interrupt messages without data and which receive a hard failure response may hang the processor S10 X X X X X No Fix...

Page 14: ...X X X X No Fix Incorrect duty cycle is chosen when on demand clock modulation is enabled in a processor supporting Hyper Threading Technology S30 X X X X X No Fix Memory aliasing of pages as uncacheab...

Page 15: ...4 Technology Intel EM64T S52 X Fixed LDT descriptor which crosses 16 bit boundary access does not cause a GP fault on a processor supporting Intel Extended Memory 64 Technology Intel EM64T S53 X Fixed...

Page 16: ...oneous value for one instruction following mode transition in Hyper Threading Technology Enabled processor supporting Intel Extended Memory 64 Technology Intel EM64T S73 X X X X Fixed The base of an L...

Page 17: ...may be reported as a result of on going transactions during warm reset S87 X X X X X No Fix Writing the local vector table LVT when an interrupt is pending may cause an unexpected interrupt S88 X X X...

Page 18: ...e of Changes Specification Changes No SPECIFICATION CHANGES None for this revision of the Specification Update Specification Clarifications No SPECIFICATION CLARIFICATIONS None for this revision of th...

Page 19: ...anch path Due to an internal boundary condition in some instances the load is not canceled before the page walk is issued The page miss handler PMH starts a speculative page walk for the Load and issu...

Page 20: ...accessed an MCE will occur However upon this MCE or any other subsequent MCE the information for that error will not be logged because MC0_STATUS UNCOR has already been set and the MCA status registe...

Page 21: ...have any way to determine the cause of the MCE The Overflow Error bit bit 62 in the IA32_MC0_STATUS register indicates when set that a machine check error occurred while the results of a previous err...

Page 22: ...ll not be captured When any instruction has multiple debug register matches and any one of those debug registers is enabled in DR7 all of the matches should be reported in DR6 when the processor goes...

Page 23: ...processor may hang Workaround None at this time Status For the steppings affected see the Summary Table of Changes S10 The processor signals page fault exception PF instead of alignment check excepti...

Page 24: ...and DR7 may become invalid Workaround Software may perform a read modify write when writing to DR6 and DR7 to ensure that the values in the reserved bits are maintained Status For the steppings affect...

Page 25: ...register TPR that lowers the APIC priority the interrupt masking operation may take effect before the actual priority has been lowered This may cause interrupts whose priority is lower than the initia...

Page 26: ...ly stop making forward progress Intel has not observed this erratum with any commercially available software Workaround None at this time Status For the steppings affected see the Summary Table of Cha...

Page 27: ...ter set to 0 default where xTPR messages are being transmitted on the system bus to the processor may experience a system hang during voltage transitions caused by power management events Implication...

Page 28: ...ved in any commercially available operating system or application The aliasing of memory regions a condition necessary for this erratum to occur is documented as being unsupported in the IA 32 Intel A...

Page 29: ...n a floating point load which splits a 64 byte cache line gets a floating point stack fault and a data breakpoint register maps to the high line of the floating point load internal boundary conditions...

Page 30: ...e memory access The problem can happen with or without paging enabled Implication This erratum may limit the debug capability of a debugger software Workaround None at this time Status For the steppin...

Page 31: ...elector specified for the VERR or VERW instructions is in non canonical space it may incorrectly cause a GP fault on a processor supporting Intel Extended Memory 64 Technology Intel EM64T Implication...

Page 32: ...processor control transfers through a call gate via the Local Descriptor Table LDT that uses a 16 byte descriptor the upper 8 byte access may wrap and access an incorrect descriptor in the LDT This o...

Page 33: ...systems may encounter unexpected behavior Workaround None at this time Status For the steppings affected see the Summary Table of Changes S55 CPUID instruction incorrectly reports CMPXCH16B as suppor...

Page 34: ...is not set prior to an INIT event on an HT Technology enabled system the processor will not enter C1E until the next SIPI wakeup event for the second logical processor Implication Due to this erratum...

Page 35: ...system hang or operating system failure Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Table of Changes S65 SYSENTER...

Page 36: ...s erratum occurs a single step trap will be taken unexpectedly Workaround None at this time Status For the steppings affected see the Summary Table of Changes S69 PDE PTE loads and continuous locked u...

Page 37: ...ssor is being stalled A similar problem may occur for the observation of the EFER LMA bit by the decode logic Implication The first instruction following a mode transition may be decoded as if it was...

Page 38: ...g central agents can a Not use processor originated BWIL or BLW transactions to update their snoop filter information or b Update the associated cache line state information to shared state on the ori...

Page 39: ...erved this erratum with any commercially available software Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Table of C...

Page 40: ...atum may cause unpredictable system behavior or system hang Workaround It is possible for BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Table of Chang...

Page 41: ...entry must have an ISR associated with it even if that vector was programmed as masked This ISR routine must do an EOI to clear any unexpected interrupts that may occur The ISR associated with the spu...

Page 42: ...gisters BTMs Branch Trace Messages or BTSs Branch Trace Stores may be incorrect Implication The upper 32 bits of the From address debug information reported through LBR or LER MSRs BTMs or BTSs may be...

Page 43: ...may report detection of a spurious breakpoint condition under certain boundary conditions when either A MOV SS or POP SS instruction is immediately followed by a hardware debugger breakpoint instructi...

Page 44: ...ons Specification Update The Specification Changes listed in this section apply to the following documents 1 64 bit Intel Xeon Processor with 2 MB L2 Cache Datasheet Document Number 306249 Link http d...

Page 45: ...ersions Specification Update The Specification Clarifications listed in this section apply to the following documents 1 64 bit Intel Xeon Processor with 2 MB L2 Cache Datasheet Document Number 306249...

Page 46: ...ium4 specupdt 252046 htm There are no new Documentation Changes for this revision of the 64 bit Intel Xeon Processor with 800 MHz System Bus 1 MB and 2 MB L2 Cache Versions Specification Update The Do...

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