10
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Identification Information
Mixed Steppings in DP Systems
Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with 800 MHz
system bus as well as mixed steppings of the 64-bit Intel Xeon processor with 2 MB L2 cache. The
following list and processor matrix describes the requirements to support mixed steppings:
•
Mixed steppings are only supported with processors that have identical family numbers as
indicated by the CPUID instruction.
•
While Intel has done nothing to specifically prevent processors operating at differing
frequencies from functioning within a multiprocessor system, there may be uncharacterized
errata that exist in such configurations. Intel does not support such configurations. In mixed
stepping systems, all processors must operate at identical frequencies (i.e., the highest
frequency rating commonly supported by all processors).
•
While there are no known issues associated with the mixing of processors with differing cache
sizes in a multiprocessor system, and Intel has done nothing to specifically prevent such
system configurations from operating, Intel does not support such configurations since there
may be uncharacterized errata that exist. In mixed stepping systems, all processors must be of
the same cache size.
•
While Intel believes that certain customers may wish to perform validation of system
configurations with mixed frequencies, cache sizes or voltages and that those efforts are an
acceptable option to our customers, customers would be fully responsible for the validation of
such configurations.
•
Intel requires that the proper microcode update be loaded on each processor operating in a
multiprocessor system. Any processor that does not have the proper microcode update loaded
is considered by Intel to be operating out of specification.
•
The workarounds identified in this and following specification updates must be properly
applied to each processor in the system. Certain errata are specific to the multiprocessor
environment. Errata for all processor steppings will affect system performance if not properly
worked around. Also see Also see
Table 2
and
Table 3
for additional details on which
processors are affected by specific errata.
•
In mixed stepping systems, the processor with the lowest feature-set, as determined by the
CPUID Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in
feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest
stepping as determined by the CPUID instruction.
•
While there are no known issues associated with the mixing of processors of different
power-optimization segments (i.e. LV or MV) in a multiprocessor system, and Intel has done
nothing to specifically prevent such system configurations from operating, Intel does not
support such configurations since there may be uncharacterized errata that exist. In mixed
stepping systems, all processors must be of the same power-optimization segment.
