Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz
January 2007
DS
Order Number: 315876-002
19
Electrical Specifications—Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz
3.8
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use
GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+
Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
Table 5
identifies which signals are common clock, source synchronous,
and asynchronous.
Table 5.
FSB Pin Groups
Signal Group
Type
Signals
1
AGTL+ Common Clock Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, PREQ#, RESET#, RS[2:0]#, RSP#,
TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
ADS#, AP[1:0]#,BINIT#, BNR#, BPM[3:0]#
3
, BR[0]#,
DBSY#, DP[3:0], DRDY#, HIT#, HITM#, LOCK#,
MCERR#, PRDY#
3
AGTL+ Source Synchronous I/O
Synchronous
to assoc.
strobe
AGTL+ Strobes
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output
Asynchronous
FERR#, IERR#, THERMTRIP#, PROCHOT#
CMOS Output
Asynchronous
VID[5:0], BSEL[2:0]
CMOS Input
Synchronous
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output
Synchronous
to TCK
TDO
FSB Clock
Clock
BCLK[1:0]
Power/Other
COMP[3:0], DBR#
2
, GTLREF, RSVD, TEST2, TEST1,
THERMDA, THERMDC, ODTEN, V
CC
, V
CCA
, V
CCP,
V
CC_SENSE
,
V
SS,
V
SS_SENSE
Notes:
1.
Refer to
Chapter 4.0
for signal descriptions and termination requirements.
2.
BPM[2:1]# and PRDY# are AGTL+ output only signals.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[35:17]#
ADSTB[1]#
D[15:0]#, DINV0#
DSTBP0#, DSTBN0#
D[31:16]#, DINV1#
DSTBP1#, DSTBN1#
D[47:32]#, DINV2#
DSTBP2#, DSTBN2#
D[63:48]#, DINV3#
DSTBP3#, DSTBN3#
