Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz
January 2007
DS
Order Number: 315876-002
31
Package Mechanical Specifications and Pin Information—Intel
®
Celeron
®
Processor 1.66 GHz/
1.83 GHz
BINIT#
Input/
Output
BINIT# (Bus Initialization) may be observed and driven by all processor front
side bus agents and if used, must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration and BINIT# is
sampled asserted, symmetric agents reset their bus LOCK# activity and bus
request arbitration state machines. The bus agents
do not
reset their IOQ and
transaction tracking state machines upon observation of BINIT# assertion. Once
the BINIT# assertion has been observed, the bus agents re-arbitrate for the
front side bus and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR#
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BPM[2:1]#
BPM[3,0]#
Output
Input/
Output
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[3:0]# should connect the appropriate pins of all Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz FSB agents.This includes debug or
performance monitoring tools.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It
must connect the appropriate pins of all FSB agents. Observing BPRI# active (as
asserted by the priority agent) causes the other agent to stop issuing new
requests, unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BR0#
Input/
Output
The BR0# (Bus Request 0) pin drives the BREQ[0]# signals in the system. The
BREQ[0]# signal is directly connected to the processor (symmetric agent) and
the Memory Controller Hub - MCH (priority agent).
BSEL[2:0]
Output
BSEL[2:0] (Bus Select) are used to select the processor input clock frequency.
Table 3 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the
processor, chipset and clock synthesizer. All agents must operate at the same
frequency. The Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz operates at 667
MHz system bus frequency (166 MHz BCLK[2:0] frequency respectively).
COMP[3:0]
Analog
COMP[3:0] must be terminated on the system board using precision (1%
tolerance) resistors.
Table 11.
Signal Description (Sheet 2 of 7)
Name
Type
Description