LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
22
Design Guide
3.9.1.2
Signal Termination Requirements
Table 13 lists signal termination requirements for the debug port signals.
Figure 9. RESET# Signal Termination
Debug Port
Rt
RESET# Source
Load
Load
Rt
V
TT
V
TT
Rs
Table 13. Debug Port Termination Requirement
Signal
Signal Termination Value (Rt)
Termination
Value (Rs)
Termination
Voltage (Rt)
System Signal
POWERON
1.5 K
Ω
N/A
V
TT
BCLK, BCLK#
BSEN#
240
Ω
N/A
V
CC
DBRESET#
240
Ω
N/A
V
CC
DBINST#
10 K
Ω
N/A
V
CC
JTAG Signals
TCK
39
Ω
N/A
GND
TDI
200 - 300
Ω
N/A
V
CC
CMOS
TDO
150
Ω
N/A
V
CC
CMOS
TMS
39
Ω
N/A
V
CC
CMOS
TRST#
500 - 680
Ω
N/A
GND
Execution signals
RESET#
Match to AGTL characteristic
impedance
240
Ω
V
TT
PREQx#
200 - 300
Ω
N/A
V
CC
CMOS
PRDYx#
Match to AGTL characteristic
impedance
240
Ω
V
TT
