Intel Pentium III Processor 512K, Design Manual

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LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
20 Design Guide
JTAG Signal Layout Guidelines
Reflections on TCK that cause mid-threshold ringing will render the primary system debug tool
inoperative. Simulate the behavioral model, and verify signal integrity using your system bus
signal analysis tools. The following table provides the JTAG signal layout guidelines. It is highly
recommended that TCK be simulated to ensure proper signal quality is maintained.
Table 10. System Signal Layout Guidelines
Signal Routing Notes Sample Layout
POWERON
Route with normal trace 2 to 6 inches to the debug port
connector
Figure 6a
BCLK, BCLK# N/A
DBRESET#, BSEN#,
DBINST#
Figure 6a
Figure 6. Simple Terminations
Table 11. JTAG Signal Layout Guidelines
Signal Routing Notes Sample Layout
TCK
Critical JTAG signal which requires timing and signal integrity
considerations; driver is 74VCX16245 with external edge rate control on
TCK
Figure 7
TMS, TDI,
TDO Critical JTAG signal which requires timing and signal integrity
considerations. ITP driver is 74VCX16245. TMS must be routed with TCK.
Figure 6a
TRST# Pull-down resistors should be used to force TRST# assertion (low). Figure 6b