LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Design Guide
41
7.3
CMOS (Non-AGTL) Signals
It is recommended to route CMOS signal traces on one signal layer, and not next to AGTL traces.
Try to avoid long traces to eliminate speed path issues, especially for APIC clock and APIC data
signals.
LOCK# (V3)
Connect to chipset and second CPU.
REQ[4:0]#
Connect to chipset and second CPU.
RESET# (B15)
Terminate to V
TT
to match AGTL trace impedance which is typically 68
Ω
,
connect to chipset. For ITP, connect to pin 2 (RESET#) of ITP through a 240
Ω
series resistor; terminate to V
TT
to match AGTL trace impedance which is
typically 68
Ω
. Refer to Figure 9 for details.
RP# (T4)
Connect to chipset and second CPU.
RS[2:0]#
Connect to chipset and second CPU.
RSP# (M5)
Connect to chipset and second CPU.
TRDY# (W1)
Connect to chipset and second CPU.
Table 20. AGTL Signals (Sheet 2 of 2)
CPU Pin
Pin Connection
Table 21. CMOS Signals (Sheet 1 of 2)
CPU Pin
Pin Connection
A20M# (AC3)
Connect to second CPU and pull up through ~330
Ω
to VccCMOS. May also
need to be connected to chipset or compatibility logic. For boards supporting
preproduction processors, this pin must be connected to frequency selection
circuitry.
FERR# (AF6)
Connect to second CPU and pull up through ~150
Ω
to VccCMOS. May need to
connect to chipset or server management logic.
FLUSH# (AF5)
Connect to second CPU and pull up through ~150
Ω
to VccCMOS
IERR# (AF4)
Pull up through ~150
Ω
to VccCMOS if connected to external logic. Leave
unconnected otherwise.
IGNNE# (AD9)
Connect to second CPU and pull up through ~330
Ω
to VccCMOS. May also
need to be connected to chipset or compatibility logic. For boards supporting
preproduction processors, this pin must be connected to frequency selection
circuitry.
INIT# (AE6)
Connect to second CPU and pull up through ~330
Ω
to VccCMOS. May also
need to be connected to chipset or compatibility logic.
LINT0/INTR (AD15)
Connect to interrupt control logic and second CPU and pull up through ~330
Ω
to
VccCMOS. For boards supporting preproduction processors, this pin must be
connected to frequency selection circuitry.
LINT1/NMI (AE14)
Connect to interrupt control logic and second CPU and pull up through ~330
Ω
to
VccCMOS. For boards supporting preproduction processors, this pin must be
connected to frequency selection circuitry.
PICD[1:0]
Connect to second CPU and pull up through ~150
Ω
to VccCMOS. May also
need to be connect to interrupt control logic.
PWRGOOD (AB4)
Connect to second CPUs and pull up through 150-330
Ω
to 1.8 V output from the
PWRGOOD logic.
SLP# (AF8)
Connect to second CPU and pull up through ~330
Ω
to VccCMOS. May also
need to be connected to chipset or compatibility logic.
