Intel MAX 10 JTAG, User Manual

Page: 9 / 14

3.4. JTAG Instructions
Instruction
Name
Instruction
Binary
Description
SAMPLE/
PRELOAD
00 0000 0101 • Permits an initial data pattern to be an output at the device pins.
• Allows you to capture and examine a snapshot of signals at the device pins if the
device is operating in normal mode.
EXTEST
( 1 ) 00 0000 1111 • Forces test pattern at the output pins and capture the test results at the input pins.
• Allows you to test the external circuitry and board-level interconnects.
BYPASS
11 1111 1111 • Places the 1-bit bypass register between the
TDI
and
TDO
pins.
• Allows the BST data to pass synchronously through target devices to adjacent
devices during normal device operation.
USERCODE
00 0000 0111 • Places the 1-bit bypass register between the
TDI
and
TDO
pins.
• Allows you to shift the
USERCODE
register out of the
TDO
pin serially.
IDCODE
00 0000 0110 • Selects the
IDCODE
register and places it between the
TDI
and
TDO
pins.
• Allows you to shift the
IDCODE
register out of the
TDO
pin serially.
HIGHZ
( 1 ) 00 0000 1011 • Places the 1-bit bypass register between the
TDI
and
TDO
pins. The 1-bit bypass
register tri-states all the I/O pins.
• Allow the BST data to pass synchronously through target devices to adjacent
devices if device is operating in normal mode.
CLAMP
( 1 ) 00 0000 1010 • Places the 1-bit bypass register between the
TDI
and
TDO
pins. The 1-bit bypass
register holds I/O pins to a state defined by the data in the boundary-scan register.
• Allow the BST data to pass synchronously through target devices to adjacent
devices if device is operating in normal mode.
USER0
00 0000 1100 • Allows you to define the scan chain between the
TDI
and
TDO
pins in the Intel MAX
10 logic array.
• Use this instruction for custom logic and JTAG interfaces.
USER1
00 0000 1110 • Allows you to define the scan chain between the
TDI
and
TDO
pins in the Intel MAX
10 logic array.
• Use this instruction for custom logic and JTAG interfaces.
(1)
HIGHZ
,
CLAMP
, and
EXTEST
instructions do not disable weak pull-up resistors or bus hold
features.
3. BST Operation Control
UG-M10JTAG | 2019.05.10
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10 JTAG Boundary-Scan Testing User Guide
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