6. Guidelines for JTAG BST
Consider the following guidelines when you perform BST with the device:
•
If the “10...” pattern does not shift out of the instruction register through the
TDO
pin during the first clock cycle of the
SHIFT_IR
state, the TAP controller did not
reach the proper state. To solve this problem, try one of the following procedures:
— Verify that the TAP controller has reached the
SHIFT_IR
state correctly. To
advance the TAP controller to the
SHIFT_IR
state, return TAP controller to the
RESET
state and send the
01100
code to the
TMS
pin.
— Check the connections to the
VCC
,
GND
,
JTAG
, and dedicated configuration
pins on the device.
•
Perform a
SAMPLE/PRELOAD
test cycle before the first
EXTEST
test cycle to
ensure that known data is present at the device pins when you enter
EXTEST
mode. If the
OEJ
update register contains 0, the data in the
OUTJ
update register
is driven out. The state must be known and correct to avoid contention with other
devices in the system.
•
To perform testing before configuration, hold the
nCONGFIG
pin low.
UG-M10JTAG | 2019.05.10
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
