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MAX
10 JTAG Boundary-Scan
Testing User Guide
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UG-M10JTAG | 2019.05.10
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Page 1: ...Intel MAX 10 JTAG Boundary Scan Testing User Guide Subscribe Send Feedback UG M10JTAG 2019 05 10 Latest document on the web PDF HTML...
Page 2: ...l 7 3 1 JTAG IDCODE 7 3 2 JTAG Secure Mode 8 3 3 JTAG Private Instruction 8 3 4 JTAG Instructions 9 4 I O Voltage Support in the JTAG Chain 10 5 Enabling and Disabling JTAG BST Circuitry 11 6 Guidelin...
Page 3: ...rol on page 7 I O Voltage Support in the JTAG Chain on page 10 Enabling and Disabling JTAG BST Circuitry on page 11 Guidelines for JTAG BST on page 12 Boundary Scan Description Language Support on pag...
Page 4: ...ion to perform and which data register to access Bypass register 1 bit long data register provides a minimum length serial path between the TDI and TDO pins Boundary scan register shift register compo...
Page 5: ...ary Scan Register You can use the boundary scan register to test external pin connections or to capture internal data The boundary scan register is a large serial shift register that uses the TDI pin...
Page 6: ...PUT OE Fromor toDevice I OCell Circuitryor LogicArray 0 1 0 1 0 1 0 1 0 1 0 1 PIN_OUT INJ OEJ OUTJ VCC SDO Pin SHIFT SDI CLOCK HIGHZ MODE PIN_OE PIN_IN Output Buffer Capture Registers Update Registers...
Page 7: ...each Intel MAX 10 device Use this code to identify the devices in a JTAG chain UG M10JTAG 2019 05 10 Send Feedback Intel Corporation All rights reserved Agilex Altera Arria Cyclone Enpirion Intel the...
Page 8: ...10M04 0000 0011 0001 0000 1010 000 0110 1110 1 10M08 0000 0011 0001 0000 0010 000 0110 1110 1 10M16 0000 0011 0001 0000 0011 000 0110 1110 1 10M25 0000 0011 0001 0000 0100 000 0110 1110 1 10M40 0000 0...
Page 9: ...of the TDO pin serially HIGHZ 1 00 0000 1011 Places the 1 bit bypass register between the TDI and TDO pins The 1 bit bypass register tri states all the I O pins Allow the BST data to pass synchronous...
Page 10: ...and Level Shifters 2 5 V VCCIO 1 8 V VCCIO 1 8 V VCCIO TDI TDO Tester ShiftTDO to Level Accepted byTester if Necessary Must be 5 0 V Tolerant Must be 3 3 V Tolerant Must be 2 5 V Tolerant 1 5 V VCCIO...
Page 11: ...rved Agilex Altera Arria Cyclone Enpirion Intel the Intel logo MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries In...
Page 12: ...be known and correct to avoid contention with other devices in the system To perform testing before configuration hold the nCONGFIG pin low UG M10JTAG 2019 05 10 Send Feedback Intel Corporation All ri...
Page 13: ...and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries Intel warrants performance of its FPGA and semiconductor products to current specifications in acco...
Page 14: ...2019 05 10 Send Feedback Intel Corporation All rights reserved Agilex Altera Arria Cyclone Enpirion Intel the Intel logo MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporatio...
