Hardware Design Guide
73
IXP28XX Network Processor
QDR SRAM
Table 26
lists the QDR K-Clock stack-up signal cross-section details.
4.5.5.1
Relationship between Address, Control, Data-OUT and K-Clock
The trace lengths of all members the K-Clocks net group should be matched to each other to within
±10 mils. The K-Clock is used to sample Address, CONTROL, and Data-OUT simultaneously.
The K-Clock has only two SRAM loads with no stubs (point-to-point topology). The Data-OUT
has two SRAM loads. However, it has either one long stub between the two SRAMs in case of
daisy chain configuration, or two shorter stubs in case of a T-Topology configuration. The Address
signal has 4 SRAM loads in a T-Topology configuration. The CONTROL signals are similar in
topology to the Data-OUT signal.
Because these signals have different topology and/or different number of loads, the flight time of
each would be different. However, the K-Clock must be used to sample the Data-OUT,
CONTROL, and Address at the same time. Therefore it becomes necessary to match their flight
times with respect to each other. Matching their flight times means adjusting their trace lengths
with respect to each accordingly. If the trace length of on of these three signals is fixed the
individual trace length of each one of the other signals must be controlled according to the
following K-Clk to Data-Out relationship formula:
K-Clk-Pkg-trace- K-Clk-trunk-length =
D-Pkg-trace- D-trunk- 500 mil
Similarly, the following formula applies for the
K-Clk/Address
relationship:
K-Clk-Pkg-trace- K-Clk-trunk-length =
Address-Pkg-trace- Address-trunk- 900 mil
Figure 35.
QDR K and K# Signal Trace Width/Spacing Routing
!
!
POWER or GND Plane
POWER or GND Plane
Table 26.
QDR K-Clock Stack-up Signal Cross-section Details
Parameter
QDR
Signal
Trace
Width (W)
[mils]
Trace
Thickness
(Tsignal)
[mils]
Trace
Spacing
(S) [mils]
D1
Thickness
(TD1)
[mils]
D2
Thickness
(Td2)
[mils]
Er(D1) Er(D2)
Spacing
between
signal
groups
[mils]
Value
K-
Clock
5
0.5
20 - 25
5.0
5.7
3.5
3.8
20 - 25
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