Hardware Design Guide
71
IXP28XX Network Processor
QDR SRAM
Figure 33
illustrates routing for QDR Q signal trace width/spacing.
Table 24
lists the QDR Q stack-up signal cross-section details.
4.5.5
QDR SRAM K, K# Clock Topologies
The K input clock registers address and control inputs on the rising edge. Data is registered on the
rising edge of K and the rising edge of K#, which is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock’s rising edges.
The K-Clock signals have 2 SRAM loads and the signals are mirrored in the SRAM part. Thus, the
topology of choice for the K-Clocks is a point-to-point topology with two SRAMs clam-shelled.
Figure 34
illustrates the routing topology for QDR K and K#.
1.
P refers to the package length.
Figure 33.
QDR Q Signal Trace Width/Spacing Routing
B3992-01
20 mil or larger
Prepreg
S
W
W
Other
Signals
POWER or GND Plane
POWER or GND Plane
T
d2
T
d1
T
signal
DATA
Signal
DATA
Signal
D2
D1
Table 24.
QDR Q Stack-up Signal Cross-section Details
Parameter
QDR
Signal
Trace
Width (W)
[mils]
Trace
Thickness
(Tsignal)
[mils]
Trace
Spacing
(S) [mils]
D1
Thickness
(TD1)
[mils]
D2
Thickness
(Td2)
[mils]
Er(D1) Er(D2)
Spacing
between
signal
groups
[mils]
Value
Q
5
0.5
20 - 25
5.0
5.7
3.5
3.8
20 - 25
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