NVM Information Guide—ICH8/ICH9
14
Bit
Name
Default
Description
8
Reserved
0b
This bit is reserved and should be set to 0b.
7:6
PHYT
00b
This field indicates the PHY device type.
00b =
82566
/
82567
PHY - GLCI mode
01b = Reserved
10b =
82562V
PHY - PCIe mode, LCI mode
11b = Reserved
This field is reflected in the PHYTYPE field in the Status register.
5
D/UD Polarity
0b
This bit defines the polarity of the dock/undock indication as
defined.
0b = GBEDOCKB pin value of 0 = dock; 1 = undock.
1b = GBEDOCKB pin value of 0 = undock; 1 = dock.
This bit is loaded in the automatic read process to bit 14 of the
Device Control register.
4
FRCSPD
0b
Force Speed
Default setting for the
Force Speed
bit in the Device Control
register (CTRL[11]). The hardware default value is 1b.
Note:
This is a reserved bit for the
82566
and
82562V
.
4:3
FD
0b
Duplex Setting
Default setting for duplex setting. Mapped to CTRL[0]. The
hardware default value is 1b.
Note:
This is a reserved bit for the
82566
and
82562V
.
2
CLK_CNT_1_16
1b
This bit is loaded to the CTRL_EXT.EnaKumCK16 bit and enables
the reduction of the internal JCLK to one-sixteenth of the external
NJCLK at the GLCI interface in Gigabit Ethernet mode.
0b = Reduction is disabled.
1b = Reduction is enabled.
1
CLK_CNT_1_4
1b
0b for
ICH9
This bit enables the automatic reduction of DMA frequency. It is
mapped to STATUS[31].
0b = Automatic reduction disabled.
1b = Automatic reduction enabled.
0
Dynamic Clock
Gating
1
b
When set, this bit enables the dynamic clock gating of the DMA and
MAC units. This bit is loaded to the
DynCK
bit in the CTRL_EXT
register.
Note:
This is a reserved bit for the
82566
and
82562V
and
should be set to 1b.
Table 10.
Shared Initialization Control (Word 13h)
