Intel GD82559ER, Datasheet

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GD82559ER — Networking Silicon
16 Datasheet
controls the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to
issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting
the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
4.2.1.1.2 Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow. For this reason the 82559ER issues a target-
disconnect at the first data access. The 82559ER asserts the STOP# signal to indicate a target-
disconnect. The figures below illustrate memory CPU read and write accesses to the 128 Kbyte
Flash buffer. The longest burst cycle to the Flash buffer contains one data access only.
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559ER controls
the TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from
the Flash buffer. When TRDY# is asserted, the 82559ER drives valid data on the AD[31:0] lines.
The CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read
accesses can be byte or word length.
Figure 4. Flash Buffer Read Cycle
SY
STE
M
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CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
ADDR DATA
MEM RD BE#
STOP#