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Datasheet

Networking Silicon — GD82559ER

12.

Package and Pinout Information

12.1

Package Information

The GD82559ER is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in

Figure 24

. More information on Intel device packaging is available in the Intel Packaging

Handbook, which is available from the Intel Literature Center or your local Intel sales office.

Figure 24. Dimension Diagram for the GD82559ER 196-Pin BGA

Summary of Contents for GD82559ER

Page 1: ...rt High Performance Networking Functions Chained memory structure similar to the 82559 82558 82557 and 82596 Improved dynamic transmit chaining with multiple priorities transmit queues Full Duplex sup...

Page 2: ...pecifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves...

Page 3: ...TIONAL DESCRIPTION 13 4 1 82559ER Initialization 13 4 1 1 Initialization Effects on 82559ER Units 13 4 2 PCI Interface 14 4 2 1 82559ER Bus Operations 14 4 2 2 Clockrun Signal 22 4 2 3 Power Managemen...

Page 4: ...s Register 49 7 1 4 PCI Revision ID Register 50 7 1 5 PCI Class Code Register 50 7 1 6 PCI Cache Line Size Register 50 7 1 7 PCI Latency Timer 51 7 1 8 PCI Header Type 51 7 1 9 PCI Base Address Regist...

Page 5: ...3 3 Register 18 PHY Address Register 70 9 3 4 Register 19 100BASE TX Receive False Carrier Counter Bit Definitions 70 9 3 5 Register 20 100BASE TX Receive Disconnect Counter Bit Definitions 70 9 3 6...

Page 6: ...GD82559ER Networking Silicon vi Datasheet...

Page 7: ...a proprietary collision reduction mechanism The 82559ER includes a simple PHY interface to the wire transformer at rates of 10BASE T and 100BASE TX and Auto Negotiation capability for speed duplex and...

Page 8: ...GD82559ER Networking Silicon 2 Datasheet...

Page 9: ...or processing of transmit and receive frames the 82559ER operates as a master on the PCI bus initiating zero wait state transfers for accessing these data parameters The 82559ER Control Status Registe...

Page 10: ...em consists of a 3 Kbyte transmit FIFO and 3 Kbyte receive FIFO Each FIFO is unidirectional and independent of the other The FIFO subsystem serves as the interface between the 82559ER parallel side an...

Page 11: ...unit can also be placed in a full duplex mode which allows simultaneous transmission and reception of frames 2 4 10 100 Mbps Physical Layer Unit The Physical Layer PHY unit of the 82559ER allows conne...

Page 12: ...GD82559ER Networking Silicon 6 Datasheet...

Page 13: ...ultiplexed on the same PCI pins A bus transaction consists of an address phase followed by one or more data phases During the address phase the address and data lines contain the 32 bit physical addre...

Page 14: ...CI configuration read and write transactions This signal is provided by the host in PCI systems DEVSEL S T S Device Select The device select signal is asserted by the target once it has detected its a...

Page 15: ...he ISOLATE pin should be pulled high to the bus Vcc through a 4 7K 62K resistor ALTRST IN Alternate Reset The Alternate Reset signal is used to reset the 82559ER on power up In systems that support an...

Page 16: ...the power supply indicator If the 82559ER is fed PCI power this pin should be connected to a pull down resistor if the 82559ER is fed by auxiliary power this pin should be connected to a pull up resis...

Page 17: ...the isolation transformer The bit stream can be two level 10BASE T or three level 100BASE TX signals depending on the mode of operation ACTLED OUT Activity LED The Activity LED pin indicates either t...

Page 18: ...GD82559ER Networking Silicon 12 Datasheet...

Page 19: ...59ER The initialization sources are listed in order of precedence For example any resource that is initialized by the Software Reset is also initialized by the D3 to D0 transition and ALTRST and PCI R...

Page 20: ...target device in one of the following cases CPU accesses to the 82559ER System Control Block SCB Control Status Registers CSR CPU accesses to the EEPROM through its CSR CPU accesses to the 82559ER POR...

Page 21: ...to issue only one read cycle when it accesses the Control Status Registers generating a disconnect by asserting the STOP signal The CPU can insert wait states by de asserting IRDY when it is not ready...

Page 22: ...elow illustrate memory CPU read and write accesses to the 128 Kbyte Flash buffer The longest burst cycle to the Flash buffer contains one data access only Read Accesses The CPU as the initiator drives...

Page 23: ...ffer write accesses can be byte length only 4 2 1 1 3 Retry Premature Accesses The 82559ER responds with a Retry to any configuration cycle accessing the 82559ER before the completion of the automatic...

Page 24: ...the SERR Enable bit in the PCI Configuration Command register or the Parity Error Response bit are not set the 82559ER only sets the Detected Parity Error bit PCI Configuration Status register bit 15...

Page 25: ...the 82559ER uses the Memory Write MW command For write accesses to data structure the 82559ER may use either the Memory Write or Memory Write and Invalidate MWI commands Read Accesses The 82559ER per...

Page 26: ...82559ER completes terminates its initiated memory burst cycles in the following cases Normal Completion All transaction data has been transferred to or from the target device for example host main me...

Page 27: ...minates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82559ER Configure command byte 3 bit 3 If this bit is set the 82559ER terminates the MW cycle and attempts to...

Page 28: ...g at a normal operating frequency or about to be started The 82559ER asserts the CLKRUN signal to indicate that it needs the PCI clock to prevent the host from stopping the PCI clock or to request tha...

Page 29: ...ominal PCI clock signal in other words a clock frequency greater than 16 MHz for proper operation During idle time the 82559ER supports a PCI clock signal suspension using the Clockrun signal mechanis...

Page 30: ...from the auxiliary source in all power states 4 2 4 5 Understanding Power Requirements When running the 82559ER off a 3 3V_standby power source the actual power consumption will scale with network tr...

Page 31: ...is signal In systems that do not have an auxiliary power source the ALTRST signal should be tied to a pull up resistor 4 2 4 7 1 Isolate Signal When the 82559ER is connected to VAUX it may be powered...

Page 32: ...oes not affect any PME related circuits in other words PCI power management registers and the wake up packet would not be affected While the RST signal is active the 82559ER ignores other PCI signals...

Page 33: ...5 1 Interesting Packet Events In the power down state the 82559ER is capable of recognizing interesting packets The 82559ER supports pre defined and programmable packets that can be defined as any of...

Page 34: ...Flash are based on a direct decode of CPU accesses to a memory window defined in either the 82559ER Flash Base Address Register PCI Configuration space at offset 18H or the Expansion ROM Base Address...

Page 35: ...instruction waveform is shown in the figure below The 82559ER performs an automatic read of seven words 0H 1H 2H AH Bh Ch and DH of the EEPROM after the de assertion of Reset The 82559ER EEPROM forma...

Page 36: ...Boot Disable The Boot Disable bit disables the Expansion ROM Base Address Register PCI Configuration space offset 30H when it is set Default value is 0b 10 8 Revision ID These three bits are used as...

Page 37: ...s only in both full duplex and half duplex switched environments The 82559ER flow control feature is not intended to be used in shared media environments Flow control is optional in full duplex mode a...

Page 38: ...specific hardware pins to select the desired mode This structure allows the 82559ER to query the PHY unit for status of the link This register is the MDI Control Register and resides at offset 10h in...

Page 39: ...em level design use The modes are selected through the use of Test Port input pin in static combinations The Test Port pins are TEST TI TEXEC and TCK During normal operation the Test pin must be pulle...

Page 40: ...nput buffers in the device periphery into a NAND tree scheme All the output drivers of the output buffers except the TOUT pin are put into HIGH Z mode These pins can then be driven to affect the outpu...

Page 41: ...A0 26 AD14 FLA1 27 AD13 FLA2 28 AD12 FLA3 29 AD11 FLA4 30 AD10 FLA5 31 AD9 FLA6 32 AD8 FLA7 33 C BE0 FLA8 34 AD7 FLA9 35 AD6 FLA10 36 AD5 FLA11 37 AD4 FLA12 37 AD3 FLA13 EEDI 39 AD2 FLA14 EEDO 40 AD1...

Page 42: ...GD82559ER Networking Silicon 36 Datasheet...

Page 43: ...4B 5B encoder accepts nibble wide data 4 bits from the CSMA unit and compiles it into 5 bit wide parallel symbols These symbols are scrambled and serialized into a 125 Mbps bit stream converted by the...

Page 44: ...NRZI coding but three levels are output instead of two There are three output levels positive negative and zero When an NRZ 0 arrives at the input of the encoder the last output level is maintained ei...

Page 45: ...rent driver that meets the TP PMD specifications Current is sinked from the isolation transformer by the TDP and TDN pins The conceptual transmit differential waveform for 100 Mbps is illustrated in t...

Page 46: ...the 4B symbols are obtained the PHY unit outputs the receive data to the CSMA unit 6 1 3 4 100BASE TX Receive Framing The PHY unit does not differentiate between the fields of the MAC frame containing...

Page 47: ...PHY unit fully supports IEEE 802 3u clause 28 The technology 10BASE T or 100BASE TX is determined by the Auto Negotiation result Speed and duplex auto select are functions of Auto Negotiation However...

Page 48: ...de pulses a major source of jitter 6 2 3 10BASE T Receive Blocks 6 2 3 1 10BASE T Manchester Decoder The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode The Manchester e...

Page 49: ...nction that inhibits transmission after a specified time window when enabled In 10 Mbps mode the jabber timer is set to a value between 26 2 ms and 39 ms If the PHY unit detects continuous transmissio...

Page 50: ...te command a prioritization scheme must be used to ensure that the highest common denominator ability is chosen Each bit in this table is set according to what the PHY is capable of supporting In the...

Page 51: ...nk is detected and off if a 10BASE T link is detected If the link fails while in Auto Negotiation this LED will keep the last valid link state If 100BASE TX link is forced this LED will be on regardle...

Page 52: ...GD82559ER Networking Silicon 46 Datasheet Figure 16 Two and Three LED Schematic Diagram LILED ACTLED VCC SpeedLED LILED ACTLED SpeedLED 82559ER...

Page 53: ...device specific configuration space The configuration space header is depicted below in Figure 17 7 1 1 PCI Vendor ID and Device ID Registers The Vendor ID and Device ID of the 82559ER are both read o...

Page 54: ...ice to ignore any parity errors that it detects and continue normal operation A value of 1b causes the device to take normal action when a parity error is detected This bit must be set to 0b after RST...

Page 55: ...b This bit is set until cleared by writing a 1b 30 Signaled System Error This bit indicates when the device has asserted SERR In the 82559ER the initial value of the Signaled System Error bit is 0b Th...

Page 56: ...s all zeroes when the CLS register is read The figure below illustrates the format of this register 24 Parity Error Detected This bit indicates whether a parity error has been detected This bit is set...

Page 57: ...ility to relocate PCI devices in address spaces The 82559ER contains three types of Base Address Registers BARs Two are used for memory mapped resources and one is used for I O mapping Each register i...

Page 58: ...ory space for the 82559ER CSR Memory Mapped BAR is 4 Kbyte It is marked as prefetchable space and is mapped anywhere in the 32 bit memory address space 7 1 9 2 CSR I O Mapped Base Address Register The...

Page 59: ...value of 01b in bits 15 and 14 then bit number 13 determines whether the values read from the EEPROM words Bh and CH will be loaded into the Subsystem ID word BH and Subsystem Vendor ID word CH field...

Page 60: ...er It signifies whether the current item in the linked list is the register defined for PCI Power Management PCI Power Management has been assigned the value of 01H 7 1 17 Next Item Pointer The Next I...

Page 61: ...2 Table 8 Power Management Capability Register Bits Default Read Write Description Table 9 Power Management Control and Status Register Bits Default Read Write Description 15 0b Read Clear PME Status...

Page 62: ...dynamic range of 0 to 2 55 W with 0 01 W resolution according to the Data Scale The value in this register is hard coded in the silicon The structure of the data register is presented below Table 10 E...

Page 63: ...nding on the current SCB Command word PORT Interface The PORT interface allows the CPU to reset the 82559ER force the 82559ER to dump information to main memory or perform an internal self test Flash...

Page 64: ...ol Block Status Word The System Control Block SCB Status Word contains status information relating to the 82559ER s Command and Receive units Bits Name Description 15 CX Command Unit CU Executed The C...

Page 65: ...2 bit field that enables a read from and a write to the external EEPROM 8 1 7 Management Data Interface Control Register The Management Data Interface MDI Control register is a 32 bit field and is use...

Page 66: ...cated in the PMDR 29 Interrupt Enable When this bit is set to 1b by software the 82559ER asserts an interrupt to indicate the end of an MDI cycle 28 Ready This bit is set to 1b by the 82559ER at the e...

Page 67: ...Management Driver Register Bits Default Read Write Description Table 12 General Control Register Bits Default Read Write Description 7 2 000000b Read Only Reserved These bits are reserved and should...

Page 68: ...he 82559ER is configured to retransmit on underrun this counter may be updated multiple times for a single frame 16 Transmit Lost Carrier Sense CRS This counter contains the number of frames that were...

Page 69: ...he status of the received frame indicates that it is a bad frame the Receive Resource Errors counter is not updated 52 Receive Overrun Errors This counter contains the number of frames known to be los...

Page 70: ...GD82559ER Networking Silicon 64 Datasheet...

Page 71: ...the receive data path The PHY unit s receive circuitry is isolated from the network Note that this may cause the descrambler to lose synchronization and produce 560 nanoseconds of dead time Note also...

Page 72: ...eserved This bit is reserved and should be set to 0b 0 RO E 14 100BASE TX Full Duplex 1 PHY able to perform full duplex 100BASE TX 1 RO 13 100 Mbps Half Duplex 1 PHY able to perform half duplex 100BAS...

Page 73: ...eld Technology Ability Field is an 8 bit field containing information indicating supported technologies specific to the selector field value 00101111 RW 4 0 Selector Field The Selector Field is a 5 bi...

Page 74: ...eceived 1 New Page received 0 New Page not received This bit will self clear on read 0 RO SC LH 0 Link Partner Auto Negotiation Able 1 Link Partner is Auto Negotiation able 0 Link Partner is not Auto...

Page 75: ...11 Good Link 1 100BASE TX link good 0 Normal operation 0 RW 10 Reserved This bit is reserved and should be set to 0b 0 RW 9 Transmit Carrier Sense Disable 1 Transmit Carrier Sense disabled 0 Transmit...

Page 76: ...eceive False Carrier These bits are used for the false carrier counter RO SC Bit s Name Description Default R W 15 0 Disconnect Event This field contains a 16 bit counter that increments for each disc...

Page 77: ...ezes when full and self clears on read RO SC Bit s Name Description Default R W 15 0 End of Frame Counter This is a 16 bit counter that increments for each end of frame error event The counter freezes...

Page 78: ...GD82559ER Networking Silicon 72 Datasheet...

Page 79: ...connected to 5V 5 in a 5 volt PCI system and 3 3 volts in a 3 3 volt PCI system Be sure to install a 10K pull up resistor This resistor acts as a current limit resistor in system where the VIO bias v...

Page 80: ...V V 3 PCI CINP Input Pin Capacitance 10 pF 4 CCLKP CLK Pin Capacitance 5 12 pF 4 CIDSEL IDSEL Pin Capacitance 8 pF 4 LPINP Pin Inductance 12 nH 4 Table 16 PCI Interface DC Specifications Table 17 Fla...

Page 81: ...fferential Peak Voltage 0 95 1 00 1 05 V ICCT100 Line Driver Supply Peak Current RBIAS100 619 20 mA 1 Table 19 100BASE TX Voltage Current Characteristics Figure 24 RBIAS100 Resistance Versus Transmitt...

Page 82: ...19mA 20 mA 21mA Table 21 AC Specifications for PCI Signaling Symbol Parameter Condition Min Max Units Notes IOH AC Switching Current High 0 Vout 1 4 44 mA 1 1 4 Vout 0 9VCC 17 1 VCC Vout mA 1 0 7VCC...

Page 83: ...is met across the minimum peak to peak portion of the clock waveform as shown in Figure 26 10 4 1 2 X1 Specifications X1 serves as a signal input from an external crystal or oscillator Table 23 defin...

Page 84: ...ith maximum clock slew rate fastest edge and voltage swing In addition the design must guarantee proper input operation for input voltage swings and slew rates that exceed the specified test condition...

Page 85: ...al in the Flash implementation should be connected permanently to 12 V Thus writing to the Flash is controlled only by the FLWE pin Table 26 provides the timing parameters for the Flash interface sign...

Page 86: ...T38 tfloe FLOE Active to Read FLD Setup Time 120 ns 1 Flash tGLQV 55 ns T39 tfldf FLOE Inactive to FLD Driven Delay Time 50 ns 1 Flash tGHQZ 35 ns T40 tflas FLA Setup Time before FLWE 5 ns 2 Flash tA...

Page 87: ...Cycle FLADDR FLCS FLOE FLDATA R Address Stable Data In T35 T37 T38 T39 T36 Table 27 EEPROM Timing Parameters Symbol Parameter Min Max Units Notes T50 tEFSK Serial Clock Frequency 1 Mhz EEPROM fsk 1 MH...

Page 88: ...Period 10 Mbps 8 24 ms Figure 31 10BASE T NLP Timings Normal Link Pulse T57 T56 Table 29 Auto Negotiation FLP Timing Parameters Symbol Parameter Min Typ Max Units T58 Tflp_wid FLP Width clock data 100...

Page 89: ...tiation FLP Timings Fast Link Pulse T60 T58 T59 Clock Pulse Data Pulse Clock Pulse FLP Bursts T62 T63 Table 30 100Base TX Transmitter AC Specification Symbol Parameter Condition Min Typ Max Units T64...

Page 90: ...GD82559ER Networking Silicon 84 Datasheet...

Page 91: ...is a 196 pin Ball Grid Array BGA package Package dimensions are shown in Figure 24 More information on Intel device packaging is available in the Intel Packaging Handbook which is available from the...

Page 92: ...TO B13 RBIAS100 B14 RBIAS10 C1 AD21 C2 RST C3 REQ C4 C BE3 C5 NC C6 AD28 C7 AD29 C8 CLKRUN C9 NC C10 VSSPT C11 ACTLED C12 VREF C13 TDP C14 TDN D1 AD18 D2 AD19 D3 AD20 D4 VSS D5 VSS D6 VSS D7 VSS D8 V...

Page 93: ...PL K13 VCC K14 FLA2 L1 AD14 L2 AD15 L3 C BE 1 L4 VCC L5 VCC L6 VSS L7 NC L8 NC L9 VCC L10 VCC L11 VSS L12 FLA5 L13 FLA4 L14 FLA3 M1 AD11 M2 AD12 M3 AD13 M4 C BE0 M5 AD5 M6 VSSPP M7 AD1 M8 FLOE M9 FLWE...

Page 94: ...VCC NC GNT PERR P A R FLD4 FLD5 FLD6 V S S V S S V S S VCC VCC VCC VCC NC D E V S E L INTA STOP V S S P L VCCPL FLD3 V S S V S S V S S V S S V S S VCC VCC NC TRDY VIO CLK FLD0 FLD1 FLD2 V S S V S S V...

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