Errata
Intel
®
Core
™
2 Duo Processor
Specification Update
47
environment is subsequently saved, the value contained in the FP Data
Operand Pointer may be incorrect.
Implication:
Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping
an 80-bit FP load around a 4-Gbyte boundary in this way is not a normal
programming practice. Intel has not observed this erratum with any
commercially available software.
Workaround:
If the FP Data Operand Pointer is used in a 64-bit operating system which
may run code accessing 32-bit addresses, care must be taken to ensure that
no 80-bit FP accesses are wrapped around a 4-Gbyte boundary.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW80.
VM Entry May Overwrite the Value for the IA32_DEBUGCTL MSR
Specified in the VM-Entry MSR-Load Area
Problem:
Following a successful VM entry with the “load debug controls” VM-entry
control set to 1, the IA32_DEBUGCTL MSR (1D9H) will always contain the
value held in the guest IA32_DEBUGCTL field in the virtual-machine control
structure (VMCS). If there is a value for the MSR in the VM-entry MSR-load
area, the processor will incorrectly overwrite that value with the value in the
VMCS.
Implication:
Due to this erratum, VM entry may result in the wrong value being loaded
into the IA32_DEBUGCTL MSR. Intel has not observed this erratum with any
commercially available software.
Workaround:
Software seeking to load the IA32_DEBUGCTL MSR as part of VM entry should
place the desired value in the guest IA32_DEBUGCTL field in the VMCS and
set the “load debug controls” VM-entry control to 1.
Status:
For the steppings affected, see the Summary Tables of Changes.
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