Summary Tables of Changes
Intel
®
Core
™
2 Duo Processor
Specification Update
11
NO
C0
M0
E0
R0
Plan
ERRATA
AW40
X
X
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
AW41
X
Fixed
VM Exit with Exit Reason “TPR Below Threshold” Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
AW42
X
X
X
X
No Fix
Using Memory Type Aliasing with cacheable and WC
Memory Types May Lead to Memory Ordering Violations
AW43
X
X
No Fix
VM Exit Caused by a SIPI Results in Zero to be Saved to
the Guest RIP Field in the VMCS
AW44
X
X
Fixed
NMIs May Not Be Blocked by a VM-Entry
Failure
AW45
X
X
Fixed
Partial Streaming Load Instruction Sequence May Cause
the Processor to Hang
AW46
X
X
Fixed
Self/Cross Modifying Code May Not be Detected or May
Cause a Machine Check Exception
AW47
X
X
Fixed
Data TLB Eviction Condition in the Middle of a Cacheline
Split Load Operation May Cause the Processor to Hang
AW48
X
X
Fixed
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
AW49
X
X
Fixed
RSM Instruction Execution under Certain Conditions May
Cause Processor Hang or Unexpected Instruction Execution
Results
AW50
X
X
X
X
No Fix
Benign Exception after a Double Fault May Not Cause a
Triple Fault Shutdown
AW51
X
X
X
X
Plan Fix
Short Nested Loops That Span Multiple 16-Byte Boundaries
May Cause a Machine Check Exception or a System Hang
AW52
X
X
X
X
No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
AW53
X
X
X
X
No Fix
LER MSRs May be Incorrectly Updated
AW54
X
X
X
X
No Fix
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine
Check Error Reporting Enable Correctly
AW55
X
X
No Fix
A VM Exit Due to a Fault While Delivering a Software
Interrupt May Save Incorrect Data into the VMCS
AW56
X
X
No Fix
A VM Exit Occuring in IA-32e Mode May Not Produce a VMX
Abort When Expected
AW57
X
X
X
X
No Fix
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
AW58
X
X
X
X
Plan Fix PSI# Signal Asserted During Reset
AW59
X
X
X
X
No Fix
Thermal Interrupts are Dropped During and While Exiting
Intel
®
Deep Power-Down State
AW60
X
X
X
X
No Fix
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
