DKHiQV-AGP (Fab. Rev. A) User’s Guide
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DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice
Revision 1.0 7/13/98
3.2
Accelerated Graphics Port
3.2.1
AGP Bus Interface
The DK board interfaces directly with the AGP and supports PCI burst mode operation. The Accelerated
Graphics Port (AGP) is a high performance bus and is based on enhancements to the PCI bus. The AGP
uses the 66MHz PCI 2.1 specification as an operational baseline. The DKHiQV-AGP card does not support
the sideband signals.
3.2.2
AGP Initialization/Configuration
Initialization of an AGP device is done via the configuration mechanism defined by the PCI 2.1 specification.
This requires the device to respond to a PCI configuration transaction when a configuration command is
decoded. The PCI definition provides for complete software driven initialization and configuration using a
separate configuration address space. PCI devices may use 256 bytes of configuration address space for
this purpose. For the PCI Bus configuration, the HiQVideo
controllers use ten registers to identify the chip,
examine the various internal states, configure the video memory and BIOS ROM base addresses and con-
trol the settings for the various operating modes. These registers are located in the PCI configuration space.
The HiQVideo
controllers support both I/O mapped memory and memory mapped I/O.
3.2.3
AGP BIOS Interface
The DKHiQV-AGP incorporates a PCI Video BIOS in a 27C512 EPROM (U2 on the ABHiQV daughtercard).
The code size is 32KB (or 40KB) resident at address 0C0000. The HiQVideo
controller generates the
ROMCS# signal for the BIOS ROM. The PCI BIOS is developed for use with the PCI local bus configuration
as defined in the PCI Local Bus Specification Rev. 2.1. Each BIOS uses word pointers to the PCI Data
Structure at offset C000:18/E000:18. Table 1 defines the PCI data structure.
Table 1: PCI Data Structure
Note
:
The PCI BIOS is usually included in and merged with the system BIOS. For more detailed informa-
tion, please refer to the 69000 VGA BIOS OEM Reference Guides.
Register Mnemonic
Register Name
Offset
VENDID
Vendor ID
00h
DEVID
Device ID
02h
DEVCTL
Device Control
04h
DEVSTAT
Device Status
06h
REV
Revision ID
08h
PRG
Programming Interface
09h
SUB
Sub Class Code
0Ah
BASE
Base Class Code
0Bh
MBASE
Memory Base Address
10h
RBASE
ROM Base Address
30h
