DKHiQV-AGP (Fab. Rev. A) User’s Guide
12
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice
Revision 1.0 7/13/98
3.7
VEESAFE for Panel Operation
3.7.1
Low Voltage for Panel Operation
A new jumper (W39) has been added to allow VEESAFE to be driven by a scaled version of VDDSAFE for
newer panels that have a low voltage requirement for VEESAFE.
W39
= 1-2
VEESAFE is controlled by R28 (potentiometer)
W39
= 2-3
VEESAFE is controlled by W21
It is important for R28 to be fed from VDDSAFE rather than some other voltage source, so that the resulting
VEESAFE will meet the same power sequencing requirements as the panel. The sequencing of VEESAFE
will be the same as for VDDSAFE when the R28 option is selected. The current requirement for low-voltage
VEESAFE is intended to be 1mA max.
3.7.2
High Voltage Operation for VEESAFE
If W39 = 2-3 is selected, the on-board DC-to-DC converter will provide a controllable DC voltage (LCD bias
voltage) for most panels. The voltage range is -12 to -45VDC (Negative) or +12 to +45VDC (Positive). To
receive a (-VEE) voltage in the range of -12 to -45 volts, adjust resistor pot R59. Measure the voltage at
W21 Terminal 1. Place a jumper on W21(1-2). To get a positive (+VEE) voltage in the range of +12 to +45
volts, adjust the resistor pot R59 and measure the voltage at W21 Terminal 3. Place a jumper on W21 (2-
3). Remove power from the system. Hook up the panel to the panel connectors. Turn on the power. This
may lower the voltage at W21 because of the voltage drop caused by the panel load. Adjust pot R59 again
for proper panel voltage. The voltage VEESAFE at W21 (+VEE or -VEE) may be generated by the formula:
R64 = (R66 + R59) * {VEESAFE
÷
1.31)-1}
WARNING
:
Improper use of the DC-to-DC converter may cause damage to the panel.
3.8
3DQHO/LQN
and LVDS Interfaces
The DK board allows a
3DQHO/LQN
or LVDS transmitter adapter card to be installed in the panel connector
(J5). Various jumper options allow flexible selection of 3.3V or 5V power for the adapter card as well as a
PCLK option for STN-DD panel support via
PanelLink
or LVDS interface.
3.8.1
PCLK for
3DQHO/LQN
STN-DD Support
If the
3DQHO/LQN
interface is operated at 3.3V as described below there may be a problem with the PCLK
voltage level. Ideally, PCLK should be reduced to 3.3V but this may not be feasible because of the video
capture VCC requirements (with the ABHiQV daughtercard, XVCC55X on the main DK board provides the
VCC power for the video capture as well as PCLK). A possible solution for PCLK may be to add a 1K
Ω
resistor in series with PCLK as close to the
3DQHO/LQN
clock input as possible to limit the current that might
otherwise flow when a 5V PCLK signal drives a 3.3V
3DQHO/LQN
clock input. This solution has not yet been
characterized or tested. The PCLK voltage level is not an issue when using a TFT panel since SHFCLK is
used for the
3DQHO/LQN
in that case.
