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DKHiQV-AGP

(Fab. Rev. A)

HiQVideo



69000 AGP Demo

Kit Documentation

User’s Guide
Revision 1.0

July 1998

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Summary of Contents for CHIPS DKHiQV-AGP

Page 1: ...DKHiQV AGP Fab Rev A HiQVideo 69000 AGP Demo Kit Documentation User s Guide Revision 1 0 July 1998...

Page 2: ...sidiary of Intel Corporation HiQVideo is a trademark of Chips and Technologies Inc a subsidiary of Intel Corporation All other trademarks are the property of their respective holders 3DQHO LQN technol...

Page 3: ...Revision History Revision Date By Comment 1 0 7 1 98 JW lnc bjb Initial release for Fab Rev A Boards...

Page 4: ...3 4 3 MPEG and ZV Port Connector 10 3 5 Mixed Voltage Generation and Power Measurement 11 3 6 Power Sequencing and Backlight Control 11 3 7 VEESAFE for Panel Operation 12 3 7 1 Low Voltage for Panel...

Page 5: ...5 DKHiQV AGP Board Component Layout 14 List of Tables Table 1 PCI Data Structure 4 Table 2 Flat Panel Connection Summary 7 Table 3 Video Sub System Voltages 11 Table 4 DKHiQV AGP Board Connector Func...

Page 6: ...AGP at speeds up to 66MHz The multiple jumper configurations and connectors allow the DK board to test perfor mance benchmarks demonstrate various multimedia features supported by the HiQVideo family...

Page 7: ...ort located on the daughtercard Flexible power supplies individually configurable to 3 3V and 5V for different blocks of the video subsystem Onboard power sequencing VGA to NTSC PAL conversion to prov...

Page 8: ...fferent blocks of the video subsystem Refer to the 69000 Data Book for the available resolution modes The user may check the power down operation of the HiQVideo controller using a jumper W1 on the DK...

Page 9: ...p examine the various internal states configure the video memory and BIOS ROM base addresses and con trol the settings for the various operating modes These registers are located in the PCI configurat...

Page 10: ...all panel interface connections 3 3 3 STN DD Buffer STN DD panels require video data alternating between two separate locations in memory In addition a dual drive panel requires data from both locati...

Page 11: ...V AGP schematics 3 3 5 Activity Indicator The HiQVideo controller provides an output pin called ACTI 69000 pin V1 to facilitate an orderly power down sequence The ACTI output is an active high signal...

Page 12: ...G1 B6 B12 B2 R4 LB0 LB0 U9 P7 25 P7 LD0 UD0 G2 B7 B13 G2 B4 LR1 LR1 V9 P8 27 LD7 G3 G0 G00 B2 SHFCLKU UG1 Y9 P9 28 LD6 G4 G1 G01 R3 UB1 V10 P10 30 LD5 G5 G2 G02 G3 UR2 Y9 P11 31 LD4 R0 G3 G03 B3 UG2 V...

Page 13: ...ite sync signal which some encod ers require DK boards incorporate an NTSC PAL encoder from Analog Device AD722 or AD723 to con vert the VGA signals to the composite NTSC video and S VHS video signals...

Page 14: ...ble 8 for multimedia jumper settings Figure 3 shows the multimedia connector pins Figure 3 Media Connector Pinout J8 J10 Name Pin Pin Name Name Pin Pin Name GND 1 2 Y0 GND 1 2 UV0 GND 3 4 Y1 GND 3 4 U...

Page 15: ...J7 connector re ceives YUV data from an MPEG or PCMCIA ZV interface card Figure 4 shows the MPEG ZV port pinout Figure 4 MPEG Video In Connector Name Pin Pin Name GND 1 2 Y0 GND 3 4 Y1 GND 5 6 Y2 GND...

Page 16: ...e to conditions where full biasing voltage VEESAFE is applied to the liquid crystal material without enabling the control and data signals to the panel The DKHiQV AGP board provides three controlled v...

Page 17: ...2 3 Remove power from the system Hook up the panel to the panel connectors Turn on the power This may lower the voltage at W21 because of the voltage drop caused by the panel load Adjust pot R59 again...

Page 18: ...to become familiar with board operations 5 Check that all jumpers are in their default positions as shown in Tables 8 through 11 Refer to Fig ures 1 and 2 for jumper locations Note For TV out and mult...

Page 19: ...nt Layout STANDBY J4 Video J3 CMPS Video J1 S Video W 1 J2 Access Bus JP1 JP2 JP3 W 40 W 8 W 7 W 9 W 6 W 5 W 3 W 4 JP10 JP5 JP11 JP9 JP7 JP8 JP6 JP12 JP13 W 37 W 36 JP4 W 21 W 39 W 38 J5 Panel Connect...

Page 20: ...of the twelve different connectors on the DKHiQV AGP board Refer to Figure 5 Table 4 DKHiQV AGP Board Connector Functions Connectors Function J1 SVIDEO Video connector J2 Access Bus J3 RCA jack compo...

Page 21: ...ed up to DVCC55X DDCDAT DDCC0LK are pulled up to GVCC W8 OPEN CLOSED External video encoder uses TSYNC held high External video encoder uses TSYNC derived from VSYNC W9 1 2 2 3 EPROM power is from 3V...

Page 22: ...oard for TV out RED output has 75 ohm termination on board for CRT drive JP2 1 2 OPEN GREEN output has 37 5 ohm termination on board for TV out GREEN output has 75 ohm termination on board for CRT dri...

Page 23: ...control is driven by ENABKL GPIO1 CSYNC ENABKL panel control is driven by ENABKL GPIO1 CSYNC ENABKL panel control is driven by ENAVEE ENABKL ENAVEE panel voltage control is driven ENAVEE ENABKL JP12...

Page 24: ...2 3 W7 sh 5 DDC pull up 2 3 W39 sh 5 VEESAFE by R82 off W8 sh 2 TV out off W40 sh 2 INT on W9 sh 2 GVCC 2 3 JP1 sh 5 CRT drive off W10 sh 3 AGP on JP2 sh 5 CRT drive off W11 not used JP3 sh 5 CRT driv...

Page 25: ...ration Settings for Multimedia Enabled Notes Schematic reference and functional category on jumper plug installed off jumper plug is not installed Jumper NTSC Function State Jumper PAL Function State...

Page 26: ...eshooting Procedures 1 Check that all jumpers and DIP switch positions are set to their default positions 2 Verify that socket U2 contains a PCI BIOS ROM 3 Verify that other parts in the system functi...

Page 27: ...Change Without Notice Revision 1 0 7 13 98 Chips and Technologies Inc a subsidiary of Intel Corporation Title DKHiQV AGP UG 2950 Zanker Road Publication No UG176 San Jose California 95134 Stock No 050...

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