Processor Configuration Registers
Intel
®
Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
April 2010
98
Document Number: 323178-002
6.2.18
PMLIMIT6 - Prefetchable Memory Limit Address
B/D/F/Type:
0/6/0/PCI
Address Offset:
26-27h
Default Value:
0001h
Access:
RO; RW
Size:
16 bits
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range is at the top of a 1-MB aligned memory block.
Note:
Prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the CPU perspective.
Table 41. PMLIMIT6 - Prefetchable Memory Limit Address Register
Bit
Access
Default
Value
RST/
PWR
Description
15:4
RW
000h
Core
Prefetchable Memory Address Limit (PMLIMIT)
Corresponds to A[31:20] of the upper limit of the address range
passed to PCI Express-G.
3:0
RO
1h
Core
64-bit Address Support (RSVD)
Indicates that the upper 32 bits of the prefetchable memory
region limit address are contained in the Prefetchable Memory
Base Limit Address register at 2Ch
