Intel
®
Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel
®
Celeron
®
Processor P4500, P4505 Series
April 2010
Datasheet Addendum
Document Number: 323178-002
21
Signal Description
3
Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type:
The signal description also includes the type of buffer used for the particular signal:
NOTES:
1.
Qualifier for a buffer type.
3.1
System Memory Interface
Notations
Signal Type
I
Input Pin
O
Output Pin
I/O
Bi-directional Input/Output Pin
Table 6.
Signal Description Buffer Types
Signal
Description
PCI Express*
PCI Express interface signals. These signals are compatible with PCI Express 2.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-
V tolerant. Refer to the PCIe specification.
FDI
Intel Flexible Display interface signals. These signals are compatible with PCI Express
2.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3-V tolerant.
DMI
Direct Media Interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3-
V tolerant.
CMOS
CMOS buffers. 1.1-V tolerant
DDR3
DDR3 buffers: 1.5-V tolerant
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
GTL
Gunning Transceiver Logic signaling technology.
Ref
Voltage reference signal.
Asynchronous
1
Signal has no timing relationship with any reference clock.
Table 7.
Memory Channel A (Sheet 1 of 2)
Signal Name
Description
Direction/Buffer
Type
SA_BS[2:0]
Bank Select:
These signals define which banks
are selected within each SDRAM rank.
O
DDR3
SA_WE#
Write Enable Control Signal:
Used with
SA_RAS# and SA_CAS# (along with SA_CS#) to
define the SDRAM Commands.
O
DDR3
