Intel Celeron P4500 Datasheet Download Page 113 | Manualshive

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Intel

®

Core

TM

i7-620LE/UE, i7-610E, i5-520E and Intel

®

Celeron

®

Processor P4500, P4505 Series

April 2010

Datasheet Addendum

Document Number: 323178-002

113

Processor Configuration Registers

6.2.36

DCTL - Device Control

B/D/F/Type:

0/6/0/PCI

Address Offset:

A8-A9h

Default Value:

0000h

Access:

RO; RW

Size:

16 bits

Provides control for PCI Express device specific capabilities.

The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.

Table 59. DCTL - Device Control Register (Sheet 1 of 2)

Bit

Access

Default

Value

RST/

PWR

Description

15

RO

0h

Core

Reserved

14:12

RO

000b

Core

Reserved for Max Read Request Size (MRRS)

11

RO

0b

Core

Reserved for Enable No Snoop (RSVD)

10

RO

0b

Core

Reserved

Reserved for Auxiliary (AUX) PM Enable ()

9

RO

0b

Core

Reserved

Reserved for Phantom Functions Enable ()

8

RO

0b

Core

Reserved

Reserved for Extended Tag Field Enable ()

7:5

RW

000b

Core

Max Payload Size (MPS)

000:128B max supported payload for Transaction Layer Packets
(TLP). As a receiver, the Device must handle TLPs as large as the
set value; as transmitter, the Device must not generate TLPs
exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to
support compliance testing.

4

RO

0b

Core

Reserved for Enable Relaxed Ordering (RSVD)

3

RW

0b

Core

Unsupported Request Reporting Enable (URRE)

When set, allows signaling ERR_NONFATAL, ERR_FATAL, or
ERR_CORR to the Root Control register when detecting an
unmasked Unsupported Request (UR). An ERR_CORR is signaled
when an unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL or ERR_NONFATAL is sent to the Root Control register
when an uncorrectable non-Advisory UR is received with the
severity bit set in the Uncorrectable Error Severity register.

2

RW

0b

Core

Fatal Error Reporting Enable (FERE)

When set, enables signaling of ERR_FATAL to the Root Control
register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.

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Summary of Contents for Celeron P4500

Page 1: ...Document Number 323178 002 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Datasheet Addendum April 2010...

Page 2: ...a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details The...

Page 3: ...rt Bifurcation 20 3 Signal Description 21 3 1 System Memory Interface 21 3 2 Reset and Miscellaneous Signals 24 4 Electrical Specifications 25 4 1 Signal Groups 25 4 2 DC Specifications 25 4 2 1 Volta...

Page 4: ...apabilities 107 6 2 28 SS Subsystem ID and Subsystem Vendor ID 107 6 2 29 MSI_CAPID Message Signaled Interrupts Capability ID 108 6 2 30 MC Message Control 108 6 2 31 MA Message Address 110 6 2 32 MD...

Page 5: ...ht Quadrant 31 Tables 1 Processor Documents 13 2 PCH Documents 14 3 Public Specifications 14 4 Supported DIMM Module Configurations 15 5 DDR3 System Memory Timing Support 16 6 Signal Description Buffe...

Page 6: ...lities Register 107 51 SS Subsystem ID and Subsystem Vendor ID Register 107 52 MSI_CAPID Message Signaled Interrupts Capability ID Register 108 53 MC Message Control Register 108 54 MA Message Address...

Page 7: ...dum Document Number 323178 002 7 Revision History Date Revision Description January 2010 001 Initial release of this document April 2010 002 Added information for the Intel Celeron Processor P4500 and...

Page 8: ...ter process technology Throughout this document Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series may be referred to as simply the processor The processor is desi...

Page 9: ...rocessor MC PProcessor Discrete G raphics PEG AnalogC RT Gigabit NetworkC onnection USB2 0 Intel HDAudio FWH TPM1 2 Super I O PCI Serial ATA Mobile Intel 5 SeriesC hipset PC H DDR3 DIMMs PC I Express...

Page 10: ...DR3 DRAM technologies for x8 and x16 devices Using 2 Gb device technologies the largest memory capacity possible is 8 GB assuming dual channel mode with two x8 dual rank un buffered DIMM memory config...

Page 11: ...roduction and Features Summary 1 3 Package The Intel Core i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series are available on a 34 x 28 mm BGA package BGA1288 Note Although the...

Page 12: ...sing Unit ICH The legacy I O Controller Hub component that contains the main PCI interface LPC interface USB2 Serial ATA and other I O functions It communicates with the legacy G MCH over a proprietar...

Page 13: ...rm in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or rece...

Page 14: ...tion and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification 2 0 http www pcisig com DDR3 SDRAM Speci...

Page 15: ...buffered ECC Raw Card E dual rank x8 unbuffered ECC Raw Card F dual rank x16 unbuffered non ECC DDR3 DRAM Device Technology Standard 1 Gb and 2 Gb technologies and addressing are supported for x16 and...

Page 16: ...er of different configurations can exist 2 1 3 1 Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM...

Page 17: ...nes are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated...

Page 18: ...lated 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology e...

Page 19: ...he IMC to further reduce latency and increase bandwidth efficiency 2 1 6 DRAM Clock Generation Two differential clock pairs for every supported DIMM There are total of four clock pairs driven directly...

Page 20: ...for the secondary port Port 1 and the associated virtual PCI to PCI bridge can be found in PCI Device 6 When the primary port is not bifurcated Device 6 is hidden from the discovery mechanism used in...

Page 21: ...ffers are not 3 3 V tolerant Refer to the PCIe specification FDI Intel Flexible Display interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but...

Page 22: ...bits SA_DQ 71 64 Note Not required for non ECC mode I O DDR3 SA_DQS 7 0 Data Strobe Complements These are the complementary strobe signals I O DDR3 SA_DQ 71 64 ECC Check Data Bits SA_DQ 71 64 are the...

Page 23: ...robe pair The data is captured at the crossing point of SB_DQS 7 0 and its SB_DQS 7 0 during read and write transactions I O DDR3 SB_DQS 8 ECC Data Strobe Complement SB_DQS 8 is the complement strobe...

Page 24: ...lands A test point may be placed on the board for this land CFG 3 PCI Express Static Lane Numbering Reversal A test point may be placed on the board for this land Lane reversal will be applied across...

Page 25: ...The DC specifications for the DDR3 signals are listed in Table 11 4 2 1 Voltage and Current Specifications Table 10 Mobile Signal Groups1 Signal Group Alpha Group Type Signals DDR3 Data Signals2 Singl...

Page 26: ...Symbol Parameter Alpha Group Min Typ Max Units Notes1 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 VIL is defined as the maximum voltage level...

Page 27: ...alphabetically by ball name for the Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series package respectively Table 13 provides a listing of all processor pins order...

Page 28: ...SA_CK 1 BG SB_DQ 5 8 SB_DQS 7 SA_DM 5 VSS SA_DM 4 SA_DQ 7 0 VSS BF SB_DQ 5 7 SB_DM 7 SA_DQ 6 1 SA_DQ 5 7 VSS VTT0 VTT0 SA_DQ 5 2 SA_DQ 4 8 SA_DQ 3 5 SA_DQ 3 4 SA_ODT 0 SA_MA 1 3 SA_WE BE RSVD VSS RSVD...

Page 29: ...Q 7 BH SA_MA 3 SA_MA 4 SA_DQ 3 1 SA_DQ 3 0 SA_DQ 1 9 SA_DQ 2 5 SB_DQ 8 SB_DQ 9 BG VSS SA_MA 9 SA_BS 2 SA_CKE 0 VDDQ VDDQ VSS SA_DQ 9 SA_DQ 1 2 VSS SA_DQ 1 3 SB_DQ 6 BF SA_DQ 8 VSS SA_DQ 7 SA_DQ 6 SB_D...

Page 30: ...M TRST VCC N RESET_ OBS PROCH OT TMS VSS CATERR VSS VCC VSS VCC VSS VCC VSS VCC VCC PEG_TX 0 PEG_TX 1 M PROC_D ETECT BPM 7 VCC VSS VCC VCC VSS VSS L VSS VSS VCC VSS VSS PEG_TX 0 PEG_TX 1 K BCLK_IT P B...

Page 31: ...SS VTT_SE NSE FDI_TX 4 FDI_TX 4 FDI_TX 1 FDI_TX 1 FDI_TX 2 N VSS PEG_RX 3 PEG_TX 2 PEG_TX 12 PEG_TX 13 PM_SYN C DMI_TX 1 FDI_TX 2 VSS M PEG_TX 8 PEG_TX 11 PEG_CL K PEG_TX 15 VSS FDI_TX 0 L VSS VSS VSS...

Page 32: ...F6 CMOS I CFG 17 AB7 CMOS I COMP0 AE66 Analog I COMP1 AD69 Analog I COMP2 AC70 Analog I COMP3 AD71 Analog I DBR W71 O DC_TEST_A5 A5 DC_TEST_A68 A68 DC_TEST_A69 A69 DC_TEST_A71 A71 DC_TEST_BR1 BR1 DC_T...

Page 33: ...oreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir PEG_ICOMPO A13 Analog I PEG_RBIAS B11 Analog I PEG_RCOMPO D12 Analo...

Page 34: ...O PM_EXT_TS 0 AV66 CMOS I PM_EXT_TS 1 AV64 CMOS I PM_SYNC M17 CMOS I PRDY U71 Async GTL O PREQ U69 Async GTL I PROC_DETECT M71 PROC_DPRSLPVR F66 CMOS O Table 12 Intel CoreTM i7 620LE UE i7 610E i5 52...

Page 35: ...me Pin Buffer Type Dir SA_DQ 1 AT6 DDR3 I O SA_DQ 2 BB5 DDR3 I O SA_DQ 3 BB9 DDR3 I O SA_DQ 4 AV7 DDR3 I O SA_DQ 5 AV6 DDR3 I O SA_DQ 6 BE6 DDR3 I O SA_DQ 7 BE8 DDR3 I O SA_DQ 8 BE11 DDR3 I O SA_DQ 9...

Page 36: ...3 I O Table 12 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir SA_DQS 3 BN21 DDR3 I O SA_DQS 4 BK44 DDR3 I O...

Page 37: ...ntel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir SB_DQ 19 BV15 DDR3 I O SB_DQ 20 BV12 DDR3 I O SB_DQ 21 BP12 DDR3 I O SB_DQ 22 BV17 DDR3 I O SB_DQ 23 BU16...

Page 38: ...1 BP30 DDR3 O SB_MA 2 BV29 DDR3 O Table 12 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir SB_MA 3 BU30 DDR...

Page 39: ...20LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VCAP0 AL57 PWR VCAP0 AN50 PWR VCAP0 AN53 PWR VCAP0 AN57 PWR VCAP0 AR48 PWR VC...

Page 40: ...41 REF Table 12 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VCC AA44 REF VCC AA48 REF VCC AA51 REF VCC A...

Page 41: ...essor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VCC U44 REF VCC U48 REF VCC U51 REF VCC U55 REF VCC W41 REF VCC W44 REF VCC W48 REF VCC W51 REF VCC W55 REF VCC_SENSE F64 A...

Page 42: ...ntel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS AA4 GND VSS AA42 GND VSS AA46 GND VSS AA50 GND VSS AA53 G...

Page 43: ...oreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS AH53 GND VSS AH55 GND VSS AH57 GND VSS AH62 GND VSS AJ70 GND VS...

Page 44: ...620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS AU21 GND VSS AU23 GND VSS AU24 GND VSS AU26 GND VSS AU28 GND VSS AU30 GN...

Page 45: ...eTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS BD14 GND VSS BD39 GND VSS BD42 GND VSS BD46 GND VSS BD50 GND VSS...

Page 46: ...2 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS D13 GND VSS D17 GND VSS D20 GND VSS D24 GND VSS D27 GN...

Page 47: ...20E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS P4 GND VSS R14 GND VSS R42 GND VSS R46 GND VSS R5 GND VSS R50 GND VSS R53 GND VSS R57 GND VSS...

Page 48: ...reTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VTT0 AW33 REF VTT0 AW35 REF VTT0 AW60 REF VTT0 AY10 REF VTT0 AY60 RE...

Page 49: ...ntel Celeron Processor P4500 P4505 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir Table 13 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List...

Page 50: ...UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AA71 RSVD AB2 FDI_LSYNC 1 CMOS I AB5 FDI_INT CMOS I AB7 CFG 17 CMOS I AB9 VSS G...

Page 51: ...E i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AD57 VSS GND AD59 VCAP2 PWR AD60 VCAP2 PWR AD62 VSS GND AD69 COMP1 Analog I AD71...

Page 52: ...LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AH46 VSS GND AH48 VSS GND AH50 VSS GND AH51 VSS GND AH53 VSS GND AH55 VSS GND...

Page 53: ...ntel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AL42 VCAP1 PWR AL44 VSS GND AL46 VCAP1 PWR AL48 VSS GND AL50 VCAP0 PWR AL51 VSS GND AL53 VCAP0 PWR AL55...

Page 54: ...620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AR28 VSS GND AR30 VSS GND AR32 VSS GND AR33 VSS GND AR35 VSS GND AR37 VCAP...

Page 55: ...and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AW14 VTT0 REF AW15 VTT0_DDR REF AW17 VTT0_DDR REF AW19 VTT0_DDR REF AW2 SB_DQ 1 DDR3 I O AW21 VTT0_...

Page 56: ...500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir B14 PEG_RX 15 PCIe I B16 PEG_RX 14 PCIe I B18 PEG_RX 13 PCIe I B19 PEG_RX 12 PCIe I B21 PEG_RX 11 PCIe I B23 PEG_RX 10 PCIe I B25...

Page 57: ...n Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BD1 SB_DQ 2 DDR3 I O BD4 SB_DQS 0 DDR3 I O BD14 VSS GND BD15 VDDQ REF BD17 SB_DQS 8 DDR3 I O BD19 SB_DQS 8 DDR3 I O...

Page 58: ...i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BG24 SA_DQ 30 DDR3 I O BG25 SA_DQ 31 DDR3 I O BG32 SA_MA 4 DDR3 O BG34 SA_MA 3 DDR3 O BG36...

Page 59: ...SA_DQS 4 DDR3 I O BK51 SA_DQS 5 DDR3 I O Table 13 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BK53 VS...

Page 60: ...tel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BP49 SB_DQ 35 DDR3 I O BP53 SB_DQ 40 DDR3 I O BP56 SB_DQ 45...

Page 61: ...620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BU46 SB_CAS DDR3 O BU48 VSS GND BU49 SB_ODT 1 DDR3 O BU51 VSS GND BU53 SB...

Page 62: ...PEG_RX 7 PCIe I D31 VSS GND D33 PEG_TX 10 PCIe O Table 13 Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir...

Page 63: ...CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir G55 VCC REF G57 VSS GND G60 VCC REF G70 VSS GND H1 VSS GND H15...

Page 64: ...5 520E and Intel Celeron Processor P4500 P4505 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir L55 VCC REF L57 VSS GND L70 VSS GND M1 VSS GND M4 FDI_TX 2 FDI O M15 DMI_TX 1 DMI O M17 PM_S...

Page 65: ...HOT Async GTL I O N70 RESET_OBS Async CMOS O P1 FDI_TX 3 FDI O P4 VSS GND P34 PEG_RX 3 PCIe I P60 VCC REF P69 TRST CMOS I P71 TDI_M CMOS I R2 FDI_TX 3 FDI O R5 VSS GND R7 FDI_TX 5 FDI O R8 FDI_TX 5 FD...

Page 66: ...S GND R51 VCC REF R53 VSS GND R55 VCC REF R57 VSS GND R59 VCAP2 PWR R60 VCAP2 PWR R62 VSS GND R64 RSVD R66 RSVD R70 VSS GND T1 VSS GND T2 RSVD T4 RSVD U6 FDI_TX 6 FDI O U7 FDI_TX 6 FDI O U9 VSS GND T6...

Page 67: ...REF U39 VSS GND U41 VCC REF U42 VSS GND U44 VCC REF U46 VSS GND U48 VCC REF U50 VSS GND U51 VCC REF U53 VSS GND U55 VCC REF U57 VSS GND U59 VCAP2 PWR U60 VCAP2 PWR U62 VSS GND U64 VSS GND U69 PREQ Asy...

Page 68: ...2 VTT0 REF W33 VTT0 REF W35 VTT0 REF W37 VCCPLL REF W39 VCCPLL REF W41 VCC REF W42 VSS GND W44 VCC REF W46 VSS GND W48 VCC REF W50 VSS GND W51 VCC REF W53 VSS GND W55 VCC REF W57 VSS GND W59 VCAP2 PWR...

Page 69: ...wer Good Reset as defined in the PCI Express Base Specification AF Atomic Flag bit s The first time the bit is read with an enabled byte it returns the value 0 but a side effect of the read is that th...

Page 70: ...field from being writable bit field becomes Read Only RW V L S Read Write Volatile Lockable Sticky bit s These bits can be read and written by software Hardware may set or clear the bit based upon int...

Page 71: ...15 DEVEN Device Enable Register Bit Access Default Value RST PWR Description 31 15 RO 0h Reserved 14 RW L 0b Core Reserved 13 RW L 0b Core PEG1 Enable D6EN 0 Bus 0 Device 6 Function 0 is disabled and...

Page 72: ...Generated Event for SMI GSGESMI This indicates the source of the SMI was a Device 2 Software Event 11 RW1C S 0b Core Processor Thermal Sensor Event for SMI SCI SERR GTSE Indicates that a Processor Th...

Page 73: ...egister in the channel where the error occurred Once this bit is set the CxECCERRLOG fields are locked until the CPU clears this bit by writing a 1 Software uses bits 1 0 to detect whether the logged...

Page 74: ...cle is detected that does not hit DRAM 0 Reporting of this condition via SERR messaging is disabled 8 RW 0b Core Reserved 7 RW 0b Core SERR on DRAM Throttle Condition ERR 0 Reporting of this condition...

Page 75: ...re Reserved 11 RW 0b Core SMI on Processor Thermal Sensor Trip TSTSMI 1 A SMI DMI special cycle is generated by Processor when the thermal sensor trip requires an SMI A thermal sensor trip point canno...

Page 76: ...Bit Access Default Value RST PWR Description 23 16 RW 00h Core ECC bit invert vector C0sd_cr_eccbitinv This vector operates individually for every ECC bit in the selected 64b ECC block during write to...

Page 77: ...1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on QW2 CERR on QW3 Table 20 Channel 0 ECC Error Registers Sheet 1 of 2 Bit Access Default Value RST PWR Description 63 48 RO P 0000h Core Error C...

Page 78: ...ata transfer When this bit is set the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors until this bit is cleared But a multiple bit...

Page 79: ...n cleared by software A multiple bit error will overwrite a single bit error Once the error flag bits are set as a result of an error this bit field is locked and doesn t change as a result of a new e...

Page 80: ...has occurred 28 27 RO V S 00b Core Error Rank Address ERRRANK Rank address of the address block of main memory of which an error single bit or multi bit error has occurred 26 24 RO 000b Core Reserved...

Page 81: ...t Disable the link then program the registers and then re enable the link which will cause a full retrain with the new settings Table 23 PCI Device 6 Register Sheet 1 of 3 Register Name Register Symbo...

Page 82: ...er Management Control Status PM_CS6 84 87 00000008h RO RW S RW Subsystem ID and Vendor ID Capabilities SS_CAPID 88 8B 0000800Dh RO Subsystem ID and Subsystem Vendor ID SS 8C 8F 00008086h RW O Message...

Page 83: ...h RW O RO Slot Control SLOTCTL B8 B9 0000h RO RW Slot Status SLOTSTS BA BB 0000h RO RWC Root Control RCTL BC BD 0000h RO RW Root Status RSTS C0 C3 00000000h RO RWC Link Control 2 LCTL2 D0 D1 0001h RO...

Page 84: ...n register uniquely identifies any PCI device Table 24 VID6 Vendor Identification Register Bit Access Default Value RST PWR Description 15 0 RO 8086h Core Vendor Identification VID6 PCI standard ident...

Page 85: ...Core SERR Message Enable SERRE1 Controls Device 6 SERR messaging The processor communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal a...

Page 86: ...s are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream memory wr...

Page 87: ...concept of a master abort does not exist on primary side of this device 12 RO 0b Core Received Target Abort Status RTAS Not Applicable or Implemented Hard wired to 0 The concept of a target abort doe...

Page 88: ...ilities list is present Hard wired to 1 3 RO 0b Core INTA Status INTAS Indicates that an interrupt message is pending internally to the device Only PME and Hot Plug sources feed into this status bit n...

Page 89: ...rogramming interface Table 28 RID6 Revision Identification Register Bit Access Default Value RST PWR Description 7 0 RO 10h Core Revision Identification Number RID6 This is an 8 bit value that indicat...

Page 90: ...ister identifies the header layout of the configuration space No physical register exists at this location Regost Table 30 CL6 Cache Line Size Register Bit Access Default Value RST PWR Description 7 0...

Page 91: ...d bus side of the virtual bridge i e to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G Table 32 PBUSN6 Primary Bus...

Page 92: ...ess Offset 1Ch Default Value F0h Access RO RW Size 8 bits This register controls the CPU to PCI Express G I O access routing based on the following formula IO_BASE address IO_LIMIT Only upper 4 bits a...

Page 93: ...I O address range is at the top of a 4 KB aligned address block Table 35 IOBASE6 I O Base Address Register Bit Access Default Value RST PWR Description 7 4 RW Fh Core I O Address Base IOBASE Correspon...

Page 94: ...Abort RMA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request...

Page 95: ...r 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This reg...

Page 96: ...registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT a...

Page 97: ...20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the config...

Page 98: ...ss bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the...

Page 99: ...PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper...

Page 100: ...dress bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initiali...

Page 101: ...mation The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information Table 44 CAPPTR6 Capabilities Pointer Register B...

Page 102: ...ing Table 46 INTRPIN6 Interrupt Pin Register Bit Access Default Value RST PWR Description 7 0 RO 01h Core Interrupt Pin INTPIN As a single function device the PCI Express device specifies INTA as its...

Page 103: ...the processor to an I O access issued by the CPU that target ISA I O addresses This applies only to I O addresses that are enabled by the IOBASE and IOLIMIT registers 0 All addresses defined by the IO...

Page 104: ...icate that the D1 power management state is NOT supported 24 22 RO 000b Core Auxiliary Current AUXC hard wired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements 21 RO 0b Core D...

Page 105: ...register 8 RW S 0b Core PME Enable PMEE Indicates that this device does not generate PMEB assertion from any D state 0 PMEB generation not possible from any D State 1 PMEB generation enabled from any...

Page 106: ...require any special action While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or...

Page 107: ...ed as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset Table 50 SS_CAPID Subsystem ID and Vendor ID Capabilities...

Page 108: ...ce is prohibited from doing so If the device writes the same message multiple times only one of those messages is guaranteed to be serviced If all of them must be serviced the device must not generate...

Page 109: ...below 3 1 RO 000b Core Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device Value Number of Messages Requested 000 1 All of...

Page 110: ...s MA Used by system software to assign an MSI address to the device The device handles an MSI by writing the padded contents of the MD register to this address 1 0 RO 00b Core Force DWord Align FDWA h...

Page 111: ...I Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space 7 0 RO 10h Core Capability ID...

Page 112: ...t Value RST PWR Description Table 58 DCAP Device Capabilities Register Bit Access Default Value RST PWR Description 31 16 RO 0000h Core Reserved Not Applicable or Implemented Hard wired to 0 15 RO 1b...

Page 113: ...Reserved Reserved for Extended Tag Field Enable 7 5 RW 000b Core Max Payload Size MPS 000 128B max supported payload for Transaction Layer Packets TLP As a receiver the Device must handle TLPs as lar...

Page 114: ...ull scope of related error reporting Table 59 DCTL Device Control Register Sheet 2 of 2 Bit Access Default Value RST PWR Description Table 60 DSTS Device Status Register Bit Access Default Value RST P...

Page 115: ...s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in t...

Page 116: ...t Capabilities register this bit must be set to 1b For Upstream Ports and components that do not support this optional capability this bit must be hard wired to 0b 19 RO 0b Core Surprise Down Error Re...

Page 117: ...and undesired value from ever existing 14 12 RO 100b Core L0s Exit Latency L0SELAT Indicates the length of time this Port requires to complete the transition from L0s to L0 000 Less than 64 ns 001 64...

Page 118: ...generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and U...

Page 119: ...component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the L0s Exit Latency reported in LCAP 14 12 and the N_FTS value adverti...

Page 120: ...k When disabling ASPM L1 software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link ASPM L1 must only be enabled on the Downs...

Page 121: ...must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hard wired to 0b 12 RO 1b Core Slot Clock Configuration SCC 0 The device uses a...

Page 122: ...Description 31 19 RW O 0000h Core Physical Slot Number PSN Indicates the physical slot number attached to this Port BIOS Requirement This field must be initialized by BIOS to a value that assigns a s...

Page 123: ...n This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation 4 RO 0b Core Reserved for Power I...

Page 124: ...s software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or w...

Page 125: ...only with a value of 0b 4 RO 0b Core Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capab...

Page 126: ...device 7 RO 0b Core Reserved for Electromechanical Interlock Status EIS If an Electromechanical Interlock is implemented this bit indicates the current status of the Electromechanical Interlock Defin...

Page 127: ...t be hard wired to 0b 3 RWC 0b Core Presence Detect Changed PDC A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is...

Page 128: ...nerated as a result of receiving PME messages 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register A PME interrupt is also genera...

Page 129: ...mplementations software must use 0 for writes to bits 17 RO 0b Core PME Pending PMEP Indicates that another PME is pending when the PME Status bit is set When the PME Status bit is cleared by software...

Page 130: ...type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP The default value of this bit is 0b Components that support only the...

Page 131: ...e Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link 3 0 RW 1h Core Target Link Speed TLS For Downstream ports this field sets a...

Page 132: ...tatus 2 Register Sheet 2 of 2 Table 71 PEGLC PCI Express G Legacy Control Register Bit Access Default Value RST PWR Description 31 3 RO 00000000h Core Reserved 2 RW 0b Core PME GPE Enable PMEGPE 0 Do...

Page 133: ...nd Default Value Access Virtual Channel Enhanced Capability Header VCECH 100 103 00010002h RW O RO Port VC Capability Register 1 PVCCAP1 104 107 00000000h RO Port VC Capability Register 2 PVCCAP2 108...

Page 134: ...Register 1 Bit Access Default Value RST PWR Description 31 12 RO 00000h Core Reserved 11 10 RO 00b Core Reserved Reserved for Port Arbitration Table Entry Size 9 8 RO 00b Core Reserved Reserved for Re...

Page 135: ...bility Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO 0000h Core Reserved 7 0 RO 00h Core Reserved for VC Arbitration Capability VCAC Table 76 PVCCTL P...

Page 136: ...f Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Port...

Page 137: ...bitration service This field is valid for RCRBs Root Ports that support peer to peer traffic and Switch Ports but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer tr...

Page 138: ...The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is set by default on Reset as well as...

Page 139: ...Intel CoreTM i7 620LE UE i7 610E i5 520E and Intel Celeron Processor P4500 P4505 Series April 2010 Datasheet Addendum Document Number 323178 002 139 Processor Configuration Registers...

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