Signal Description
Intel
®
Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
April 2010
22
Document Number: 323178-002
SA_RAS#
RAS Control Signal:
Used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
O
DDR3
SA_CAS#
CAS Control Signal:
Used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
O
DDR3
SA_DM[7:0]
Data Mask:
These signals are used to mask
individual bytes of data in the case of a partial
write and to interrupt burst writes. When activated
during writes, the corresponding data groups in
the SDRAM are masked. There is one SA_DM[7:0]
for every data byte lane.
O
DDR3
SA_DQS[8]
ECC Data Strobe
: SA_DQS[8] is the data strobe
for the ECC check data bits SA_DQ[71:64]
Note
: Not required for non-ECC mode
I/O
DDR3
SA_DQS[7:0]
Data Strobes:
SA_DQS[7:0] and its complement
signal group make up a differential strobe pair. The
data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS#[7:0] during read
and write transactions
I/O
DDR3
SA_DQS#[8]
ECC Data Strobe Complement
: SA_DQS#[8] is
the complement strobe for the ECC check data bits
SA_DQ[71:64]
Note
: Not required for non-ECC mode
I/O
DDR3
SA_DQS#[7:0]
Data Strobe Complements:
These are the
complementary strobe signals.
I/O
DDR3
SA_DQ[71:64]
ECC Check Data Bits:
SA_DQ[71:64] are the ECC
check data bits for Channel A.
Note
: Not required for non-ECC mode
I/O
DDR3
SA_DQ[63:0]
Data Bus:
Channel A data signal interface to the
SDRAM data bus.
I/O
DDR3
SA_MA[15:0]
Memory Address:
These signals are used to
provide the multiplexed row and column address
to the SDRAM.
O
DDR3
SA_CK[1:0]
SDRAM Differential Clock:
Channel A SDRAM
Differential clock signal pair. The crossing of the
positive edge of SA_CK and the negative edge of
its complement SA_CK# are used to sample the
command and control signals on the SDRAM.
O
DDR3
SA_CK#[1:0]
SDRAM Inverted Differential Clock:
Channel A
SDRAM Differential clock signal-pair complement.
O
DDR3
SA_CKE[1:0]
Clock Enable:
(1 per rank) Used to:
- Initialize the SDRAMs during power-up
- Power-down SDRAM ranks
- Place all SDRAM ranks into and out of self-refresh
during STR
O
DDR3
SA_CS#[1:0]
Chip Select:
(1 per rank) Used to select particular
SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
O
DDR3
SA_ODT[1:0]
On Die Termination:
Active Termination Control.
O
DDR3
Table 7.
Memory Channel A (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type
