Power Management
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Datasheet
No notification to the system occurs upon entry to C1/C1E.
4.2.5.3
Package C3 State
A processor enters the package C3 low power state when:
•
At least one core is in the C3 state.
•
The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform.
•
The platform has not granted a request to a package C6 state but has allowed a
package C6 state.
In package C3-state, the L3 shared cache is snoopable.
4.2.5.4
Package C6 State
A processor enters the package C6 low power state when:
•
At least one core is in the C6 state.
•
The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable
in
this state. The processor remains in package C6 state as long as any part of the L3
cache is active.
4.2.5.5
Power Status Indicator (PSI#) and DPRSLPVR#
PSI# and DPRSLPVR# are signals used to optimize VR efficiency over a wide power
range depending on amount of activity within the processor core. The PSI# signal is
utilized by the processor core to:
•
Improve intermediate and light load efficiency of the voltage regulator when the
processor is active (P-states).
•
Optimize voltage regulator efficiency in very low power states. Assertion of
DPRSLPVR# indicates that the processor core is in a C6 low power state.
The VR efficiency gains result in overall platform power savings and extended battery
life.
4.3
IMC Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
