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Intel Celeron P4000 Series, Datasheet

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Intel Celeron P4000 Series Datasheet Download Page 12

Features Summary

12

Datasheet

Dual-channel symmetric (Interleaved)

Dual-channel asymmetric

•

Command launch modes of 1n/2n

•

Partial Writes to memory using Data Mask (DM) signals

•

On-Die Termination (ODT) 

•

Intel® Fast Memory Access (Intel® FMA):

— Just-in-Time Command Scheduling

— Command Overlap

— Out-of-Order Scheduling

1.3.2

PCI Express*

•

The Processor PCI Express ports are fully compliant to the 

PCI Express Base 

Specification Revision 2.0

.

— One 16-lane PCI Express* port intended for graphics attach.

•

Gen1 (2.5 GT/s) PCI Express* frequency is supported.

•

Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per 
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this 
interface. This also does not account for packet overhead and link maintenance.

•

Maximum theoretical bandwidth on interface of 4 GB/s in each direction 
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.

•

Hierarchical PCI-compliant configuration mechanism for downstream devices.

•

Traditional PCI style traffic (asynchronous snooped, PCI ordering).

•

PCI Express extended configuration space. The first 256 bytes of configuration 
space aliases directly to the PCI compatibility configuration space. The remaining 
portion of the fixed 4-KB block of memory-mapped space above that (starting at 
100h) is known as “extended configuration space”.

•

PCI Express Enhanced Access Mechanism. Accessing the device configuration space 
in a flat memory mapped fashion.

•

Automatic discovery, negotiation, and training of link out of reset.

•

Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).

•

Peer segment destination posted write traffic (no peer-to-peer read traffic) in 
Virtual Channel 0:

— DMI -> PCI Express Port 0

•

64-bit downstream address format, but the processor never generates an address 
above 64 GB (Bits 63:36 will always be zeros).

•

64-bit upstream address format, but the processor responds to upstream read 
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are 

Summary of Contents for Celeron P4000 Series

Page 1: ...Document Number 324471 001 Intel Celeron Mobile Processor P4000 and U3000 Series Datasheet Revision 001 October 2010...

Page 2: ...ATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of...

Page 3: ...Memory Interface 20 2 1 1 System Memory Technology Supported 20 2 1 2 System Memory Timing Support 21 2 1 3 System Memory Organization Modes 21 2 1 4 Rules for Populating Memory Slots 23 2 1 5 Techno...

Page 4: ...hics Power Management 51 4 6 1 Intel Display Power Saving Technology 5 0 Intel DPST 5 0 51 4 6 2 Graphics Render C State 51 4 6 3 Graphics Performance Modulation Technology 51 4 6 4 Intel Smart 2D Dis...

Page 5: ...ckage Mechanical Information 179 Figures Figure 1 1 Intel Celeron P4000 and U3000 mobile processor series on the Calpella Platform 10 Figure 2 2 Intel Flex Memory Technology Operation 22 Figure 2 3 Du...

Page 6: ...ination of Thread Power States at the Core Level 43 Table 4 14 P_LVLx to MWAIT Conversion 43 Table 4 15 Coordination of Core Power States at the Package Level 46 Table 4 16 Targeted Memory State Condi...

Page 7: ...ons 99 Table 7 43 DDR3 Signal Group DC Specifications 100 Table 7 44 Control Sideband and TAP Signal Group DC Specifications 101 Table 7 45 PCI Express DC Specifications 102 Table 7 46 eDP DC Specific...

Page 8: ...8 Datasheet Revision History Revision Number Description Revision Date 001 Initial release October 2010...

Page 9: ...ries Chipset formerly Ibex Peak M Intel Celeron P4000 and U3000 mobile processor series is designed for the Calpella platform and is offered in rPGA988A and BGA1288 package respectively Included in th...

Page 10: ...tel 5 Series Chipset PCH DDR3 SO DIMMs PCI Express x16 8 PCI Express x1 Ports 2 5 GT s 14 Ports PCI 6 Ports 3 Gb s SPI Digital Display x 3 Intel Flexible Display Interface PCI Express WiMax SPI Flash...

Page 11: ...with a maximum of one SO DIMM per channel Single and dual channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 800 MT s SV...

Page 12: ...n x16 Gen 1 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first...

Page 13: ...face second generation DMI2 Four lanes in each direction 2 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 2 5 Gb s resulting in a real bandwidth per pair of 2...

Page 14: ...a communication channel between a PECI client the processor and a PECI master the PCH 1 3 5 Intel HD Graphics Controller The integrated graphics controller contains a refresh of the fifth generation g...

Page 15: ...l downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate Two sideband signals for Display synchronizat...

Page 16: ...er Saving Technology Intel DPST Graphics Render C State RC6 1 5 Thermal Management Support Digital Thermal Sensor Adaptive Thermal Monitor THERMTRIP and PROCHOT support On Demand Mode Open and Closed...

Page 17: ...curity of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information G MCH Legacy component Graphics Memory Controller Hub GPU Graphics Processing U...

Page 18: ...hese devices are usually but not always mounted on a single side of a SO DIMM SCI System Control Interrupt Used in ACPI protocol Storage Conditions A non operational state The processor may be install...

Page 19: ...ss Base Specification 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http...

Page 20: ...le sided x8 stacked unbuffered non ECC Raw Card F double sided x8 planar unbuffered non ECC DDR3 DRAM Device Technology Standard 1 Gb and 2 Gb technologies and addressing are supported for x16 and x8...

Page 21: ...ate and memory configuration NOTES 1 System memory timing support is based on availability and is subject to change 2 1 3 System Memory Organization Modes The IMC supports two memory organization mode...

Page 22: ...Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 6...

Page 23: ...te between addresses that sit on opposite channels with this memory organization so in most cases bandwidth is limited to a single channel This mode is used when Intel Flex Memory Technology is disabl...

Page 24: ...t system memory protocol 2 1 5 2 Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted...

Page 25: ...25 GHz results in 2 5 Gb s direction which provides a 250 MB s communications channel in each direction 500 MB s total That is close to twice the data rate of classic PCI The fact that 8b 10b encoding...

Page 26: ...ates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrit...

Page 27: ...ired to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mec...

Page 28: ...Express supporting up to 1 GB s of bandwidth in each direction Note Only DMI x4 configuration is supported 2 3 1 DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI...

Page 29: ...d by the planes The surfaces are then blended in the pipes and the display timings are transitioned from display core clock to the pixel dot clock 2 4 1 3D and Video Engines for Graphics Processing Th...

Page 30: ...from the edges 2 4 1 2 4 Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The...

Page 31: ...ectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory an...

Page 32: ...vers that data to a display pipe This is clocked by the Core Display Clock 2 4 2 1 1 Planes A and B Planes A and B are the main display planes and are associated with Pipes A and B respectively The tw...

Page 33: ...encoding logic and send the data to the display device i e LVDS HDMI DVI SDVO etc All display interfaces connecting external displays are now repartitioned and driven from the PCH with the exception o...

Page 34: ...orting pixel and framing data from the display engine Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling Intel FD...

Page 35: ...DTS values for fan speed control 2 6 Interface Clocking 2 6 1 Internal Clocking Requirements Table 2 4 Processor Reference Clocks Reference Input Clocks Input Frequency Associated PLL BCLK BCLK 133 M...

Page 36: ...T x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platforms By using Intel VT x a V...

Page 37: ...hnology Driver The processor core die and the integrated graphics and memory controller core die have an individual TDP limit If one component is not consuming enough thermal power to reach its TDP th...

Page 38: ...o RAM STR Context saved to memory S3 Hot is not supported by the processor G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot...

Page 39: ...using device self refresh Table 4 8 PCIe Link States State Description L0 Full on Active transfer state L0s First Active Power Management low power state Low exit latency L1 Lowest Active Power Manag...

Page 40: ...p S State Processor Core C State Processor State System Clocks Description G0 S0 C0 Full On On Full On G0 S0 C1 C1E Auto Halt On Auto Halt G0 S0 C3 Deep Sleep On Deep Sleep G0 S0 C6 Deep Power Down On...

Page 41: ...a lower voltage by signaling the target voltage on the VID 6 0 pins All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested am...

Page 42: ...C states are automatically resolved by the processor For thread and core C states a transition to and from C0 is required before entering any other C state Figure 4 9 Idle Power Management Breakdown...

Page 43: ...t up before using the P_LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as follows The BIOS can write to the C state range field of the PMG_IO_CAPTURE MSR to restri...

Page 44: ...ode is being executed 4 2 4 2 Core C1 C1E State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler r...

Page 45: ...e to C3 or C3 Deep Power Down Technology code named C6 state to C1 is based on each core s immediate residency history Upon each core Deep Power Down Technology code named C6 state request the core C...

Page 46: ...r snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memo...

Page 47: ...state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when At least one cor...

Page 48: ...heir architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as an...

Page 49: ...RAM operations associated with the Clock Enable CKE signals which the SDRAM controller supports The processor drives four CKE pins to perform these operations 4 3 2 1 Initialization Role of CKE During...

Page 50: ...MM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should...

Page 51: ...met The graphics VR will lower the graphics voltage rail VAXG into a lower voltage state 0 3 V The render frequency clock will shut down 4 6 3 Graphics Performance Modulation Technology Graphics Perfo...

Page 52: ...Power Management 52 Datasheet 4 7 Thermal Power Management See Section 5 Thermal Management on page 53 for all graphics thermal power management related features...

Page 53: ...not the absolute worst case power of each component It could for example be exceeded under a synthetic worst case condition or under short power spikes In production a range of power is to be expected...

Page 54: ...ry controller operating at its minimum thermal power The integrated graphics operates at its maximum thermal power level while the processor core consumes the remaining thermal power budget In both ca...

Page 55: ...nded to establish the full cooling capability within 10 C of the Tj max specifications Some processors may have a different Tj max value please refer to the processor Specification Update for details...

Page 56: ...tate CPU Core W Int Gfx Memory Controller w Pkg Concurrent Power w 3 13 CPU Core GHz Int Gfx MHz CPU Core Extreme W 6 7 Int Gfx Extreme W 6 7 MCP Thermal Power Limit W CPU Core C Int Gfx Memory Contro...

Page 57: ...e MCP components could potentially cause a component to reach its Tj max invoking undesirable component hardware auto throttling It is expected that when running the TDP workload power sharing control...

Page 58: ...t vs performance for their system price and performance targets 5 2 Thermal Management Features This section will cover thermal management features for the processor 5 2 1 Processor Core Thermal Featu...

Page 59: ...al solution that can maintain TDP within its intended usage range 5 2 1 1 1 Frequency VID Control Upon TCC activation the processor core attempts to dynamically reduce processor core power by lowering...

Page 60: ...n transitioning to a target core operating voltage a new VID code to the voltage regulator is issued The voltage regulator must support dynamic VID steps to support this method During the voltage chan...

Page 61: ...temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as par...

Page 62: ...specific register and programming details 5 2 1 3 PROCHOT Signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature Tj max This will ac...

Page 63: ...pact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of...

Page 64: ...ulation Based On Demand Mode I O emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through I O writes to ACPI defined processor clo...

Page 65: ...agement The thermal sensor may be programmed to cause hardware throttling and or software interrupts Hardware throttling includes render thermal throttling and main memory programmable throttling thre...

Page 66: ...e interrupt 5 2 2 1 5 Thermal Sensor Accuracy Taccuracy The error associated with DTS measurement will not exceed 5 C within the operating range Integrated graphics and memory controller may not opera...

Page 67: ...e able to assert PM_EXT_TS 0 and or PM_EXT_TS 1 if the pre programmed thermal limits conditions are met or exceeded An external thermal sensor with a serial interface may be placed next to a SO DIMM o...

Page 68: ...ment Control Interface PECI The Platform Environment Control Interface PECI is a one wire interface that provides a communication channel between Intel processor and chipset components to external mon...

Page 69: ...t also incur a larger time lag between fast DTS temperature changes and the value read via PECI Within the processor the DTS converts an analog signal into a digital value representing the temperature...

Page 70: ...0 Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCIe specification FDI Intel Flexible Display interface signals These signals are compati...

Page 71: ...data groups in the SDRAM are masked There is one SA_DM 7 0 for every data byte lane O DDR3 SA_DQS 7 0 Data Strobes SA_DQS 7 0 and its complement signal group make up a differential strobe pair The da...

Page 72: ...gnal Used with SB_CAS and SB_WE along with SB_CS to define the SRAM Commands O DDR3 SB_CAS CAS Control Signal Used with SB_RAS and SB_WE along with SB_CS to define the SRAM Commands O DDR3 SB_DM 7 0 D...

Page 73: ...nal pair complement O DDR3 SB_CKE 1 0 Clock Enable 1 per rank Used to Initialize the SDRAMs during power up Power down SDRAM ranks Place all SDRAM ranks into and out of self refresh during STR O DDR3...

Page 74: ...on resistor I A COMP3 Impedance compensation must be terminated on the system board using a precision resistor I A PM_SYNC Power Management Sync A sideband signal to communicate power management statu...

Page 75: ...ts No Connect Test Point Non Critical to Function Table 6 25 PCI Express Graphics Interface Signals Signal Name Description Direction Buffer Type PEG_RX 15 0 PEG_RX 15 0 PCI Express Graphics Receive D...

Page 76: ...xed with PEG_RX 2 I O PCI Express eDP_HPD Embedded DisplayPort Hot Plug Detect Nominally eDP_HPD is multiplexed with PEG_RX 12 When reversed eDP_HPD is multiplexed with PEG_RX 3 I PCI Express eDP_ICOM...

Page 77: ...CH Direct Media Interface transmit differential pair O DMI Table 6 28 PLL Signals Signal Name Description Direction Buffer Type BCLK BCLK Differential bus clock input to the processor I Diff Clk BCLK_...

Page 78: ...TDI provides the serial input needed for JTAG specification support I CMOS TDO Test Data Output O CMOS TDI_M Test Data In for the GPU Memory core Tie TDI_M and TDO_M together on the motherboard I CMOS...

Page 79: ...rical specifications protocols and functions can be found in the RS Platform Environment Control Interface PECI Specification Revision 2 0 I O Asynchronous PROCHOT Processor Hot PROCHOT goes active wh...

Page 80: ...the PCH I Asynchronous CMOS SM_DRAMPWROK SM_DRAMPWROK Processor Input Connects to PCH DRAMPWROK I Asynchronous CMOS VTTPWRGOOD VTTPWRGOOD Processor Input The processor requires this input signal to be...

Page 81: ...sor core I A PROC_DPRSLPVR Processor output signal to Intel MVP 6 5 controller to indicate that the processor is in the package C6 state O CMOS PSI Processor Power Status Indicator This signal is asse...

Page 82: ...respectively O CMOS VTT_SELECT The VTT_SELECT signal is used to select the correct VTT voltage level for the processor O CMOS VCC_SENSE VSS_SENSE Voltage Feedback Signals to an Intel MVP 6 5 Compliant...

Page 83: ...acitors BGA only PWR Table 6 33 Ground and NCTF Signal Name Description Direction Buffer Type VSS Processor ground node GND VSS_NCTF Non Critical to Function The pins are for package mechanical reliab...

Page 84: ...Signal Description 84 Datasheet TDI_M Pull Up VTT 44 55 k PREQ Pull Up VTT 44 55 k CFG 17 0 Pull Up VTT 5 14 k Table 6 34 Processor Internal Pull Up Pull Down Signal Name Pull Up Pull Down Rail Value...

Page 85: ...perly designed Caution Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 35 Failure to do so can result in timing violations or...

Page 86: ...cifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core freque...

Page 87: ...1 1750 0 0 1 1 0 1 1 1 1625 0 0 1 1 1 0 0 1 1500 0 0 1 1 1 0 1 1 1375 0 0 1 1 1 1 0 1 1250 0 0 1 1 1 1 1 1 1125 0 1 0 0 0 0 0 1 1000 0 1 0 0 0 0 1 1 0875 0 1 0 0 0 1 0 1 0750 0 1 0 0 0 1 1 1 0625 0 1...

Page 88: ...0 6000 1 0 0 1 0 0 1 0 5875 1 0 0 1 0 1 0 0 5750 1 0 0 1 0 1 1 0 5625 1 0 0 1 1 0 0 0 5500 1 0 0 1 1 0 1 0 5375 1 0 0 1 1 1 0 0 5250 1 0 0 1 1 1 1 0 5125 1 0 1 0 0 0 0 0 5000 1 0 1 0 0 0 1 0 4875 1 0...

Page 89: ...0 1 1 1 0 0 1250 1 1 0 1 1 1 1 0 1125 1 1 1 0 0 0 0 0 1000 1 1 1 0 0 0 1 0 0875 1 1 1 0 0 1 0 0 0750 1 1 1 0 0 1 1 0 0625 1 1 1 0 1 0 0 0 0500 1 1 1 0 1 0 1 0 0375 1 1 1 0 1 1 0 0 0250 1 1 1 0 1 1 1...

Page 90: ...ation of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resis...

Page 91: ...BCLK BCLK PEG_CLK PEG_CLK DPLL_REF_SSCLK DPLL_REF_SSCLK Differential b CMOS Output BCLK_ITP BCLK_ITP DDR3 Reference Clocks2 Differential c DDR3 Output SA_CK 1 0 SA_CK 1 0 SB_CK 1 0 SB_CK 1 0 DDR3 Com...

Page 92: ...PM_EXT_TS 1 CFG 17 0 Single Ended qb CMOS Input RSTIN Single Ended r CMOS Output PROC_DPRSLPVR VID 6 VTT_SELECT Single Ended s CMOS Bi directional VID 5 3 CSC 2 0 VID 2 0 MSID 2 0 Single Ended t Anal...

Page 93: ...hin the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each...

Page 94: ...D precautions should always be taken to avoid high static voltages or electric fields NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications mus...

Page 95: ...evel rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 7 Nominal temperature and humidity conditions and durations are given and te...

Page 96: ...14 for the minimum typical and maximum VCC allowed for a given current The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current 5 Processor...

Page 97: ...D iffe r e n tia l R e m o te S e n s e r e q u ir e d V C C S e t P o i n t E r r o r T o l e r a n c e i s p e r b e l o w T o l e r a n c e V C C C O R E V I D V o l t a g e R a n g e V I D 1 5 3 m...

Page 98: ...05 1 1025 V 1 Voltage for the memory controller and shared cache defined across VTT_SENSE and VSS_SENSE_VTT 0 9765 1 05 1 1235 V 2 VDDQ DC AC Processor I O supply voltage for DDR3 DC AC specification...

Page 99: ...core voltage See Figure 7 15 TOLAXG VAXG Tolerance See Figure 7 15 Non VR LL contribution Non VR Load Line Contribution for VAXG rPGA BGA 4 4 25 m LLAXG VAXG Loadline 7 m ICCMAX_VAXG Max Current for I...

Page 100: ...MP resistance must be provided on the system board with 1 resistors COMP resistors are to VSS Table 7 43 DDR3 Signal Group DC Specifications Symbol Parameter Alpha Group Min Typ Max Units Notes1 VIL I...

Page 101: ...n p s Input Low Voltage 0 64 VTT V 2 3 VIH m n p s Input High Voltage 0 76 VTT V 2 3 5 VIL g Input Low Voltage 0 25 VTT V 2 3 VIH g Input High Voltage 0 80 VTT V 2 3 5 VIL ga Input Low Voltage 0 4 VT...

Page 102: ...of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 20 must be within the specified range by the time Detect is entered 10 Low impedance defined du...

Page 103: ...ECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control More detailed information may be found in the Platform Environment Control Inter...

Page 104: ...tes1 Vin Input Voltage Range 0 150 VTT V Vhysteresis Hysteresis 0 1 VTT N A V Vn Negative edge Threshold Voltage 0 275 VTT 0 500 VTT V Vp Positive edge Threshold Voltage 0 550 VTT 0 725 VTT V Isource...

Page 105: ...e for the rPGA988A and BGA1288 package respectively Table 8 48 and Table 8 51 provides a listing of all processor pins ordered alphabetically by pin number for the rPGA988A and BGA1288 package respect...

Page 106: ..._CKE 0 VTT0 SA_DQS 3 SA_DQ 3 0 VDDQ VSS SA_DQS 3 SA_DQ 2 6 SA_DM 3 VTT0 SA_DQ 27 VSS SA_DQ 2 4 VTT0 VSS SA_DQ 2 9 SA_DQ 18 VTT1 SA_DIM M _VREF VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 SA_DQ 2 3 SA_DQS 2 SA_DQ 19...

Page 107: ...6 2 SA_DQS 7 GFX_VID 3 GFX_VID 1 VAXG VSS VAXG VAXG VSS VAXG PM_EXT_ TS 1 SA_DQ 6 3 VSS VSS GFX_VID 2 VAXG VSS VAXG VAXG VSS VAXG PM_EXT_ TS 0 VCCPWR GOOD_1 SA_DM 7 GFX_VID 4 GFX_VID 0 VAXG VSS VAXG V...

Page 108: ...T T1 V TT 1 VT T1 R SVD DMI_TX 1 DM I_T X 3 FDI_TX 4 F DI_T X 4 V SS F DI_T X 7 FDI_ TX 7 F PEG_RX 3 P EG_RX 5 PEG_RX 8 P EG_RX 6 PE G_ RX 6 VS S P EG_T X 11 PEG_TX 11 VSS VT T1 VSS DMI_TX 1 DM I_T X...

Page 109: ...J SB_DIM M_VREF RSVD_T P VSS VTT0 VSS VTT0 VSS SA_DQ 16 SA_DQ S 2 VSS SA_DM 2 SB_DQ 16 VSS SB_DQ S 2 SB_DM 2 VSS VDDQ H RSVD COMP1 VTT_SE LECT VTT0 VTT0 VTT0 VTT0 SA_DQ 21 VSS SA_DQ 17 SA_DQ 20 VSS S...

Page 110: ...g I A26 PEG_ICOMPO Analog I A27 VSS GND A28 PEG_RX 13 PCIe I A29 VSS GND A30 PEG_RX 15 PCIe I A31 PEG_RX 15 PCIe I A32 PEG_RX 11 PCIe I A33 RSVD_NCTF A34 RSVD_NCTF A35 VSS_NCTF AA1 RSVD_TP AA2 RSVD_TP...

Page 111: ...0 DDR3 O AD9 RSVD_TP AD10 VSS GND Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir AD26 VCC REF AD27 VCC REF AD28 VCC REF AD29 VCC REF AD30 VCC REF AD31 VCC REF...

Page 112: ...5 VCC REF AH1 SB_DM 4 DDR3 O AH2 SB_DQS 4 DDR3 I O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir AH3 VSS GND AH4 SB_DQ 39 DDR3 I O AH5 SA_DQ 32 DDR3 I O AH6...

Page 113: ...DQ 41 DDR3 I O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir AK5 SB_DQ 44 DDR3 I O AK6 SA_DQ 34 DDR3 I O AK7 SA_DQ 35 DDR3 I O AK8 SA_DQ 44 DDR3 I O AK9 SA_D...

Page 114: ...GND Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir AM6 SB_DQ 42 DDR3 I O AM7 SA_DM 5 DDR3 O AM8 VSS GND AM9 SA_DQ 52 DDR3 I O AM10 SA_DQ 49 DDR3 I O AM11 VSS...

Page 115: ...N34 VSS GND AN35 ISENSE Analog I AP1 RSVD_NCTF AP2 VSS GND Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir AP3 SB_DQ 48 DDR3 I O AP4 VSS GND AP4 VSS GND AP5 SB...

Page 116: ...AT1 VSS_NCTF Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir AT2 RSVD_TP AT3 RSVD_NCTF AT4 SB_DQ 50 DDR3 I O AT5 SB_DQ 54 DDR3 I O AT6 SB_DQ 55 DDR3 I O AT7 SB...

Page 117: ...D_NCTF C1 RSVD_NCTF Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir C2 SB_DQ 12 DDR3 I O C3 SB_DQ 2 DDR3 I O C4 SB_DQ 7 DDR3 I O C5 SB_DQS 0 DDR3 I O C6 SA_DQ...

Page 118: ...E1 SB_DM 1 DDR3 O E2 VSS GND E3 SB_DQS 1 DDR3 I O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir E4 SB_DQ 4 DDR3 I O E5 VSS GND E6 SA_DQ 10 DDR3 I O E7 SA_DQ...

Page 119: ...DDR3 I O G3 VSS GND G4 SB_DQ 15 DDR3 I O G5 SB_DQ 21 DDR3 I O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir G6 VSS GND G7 SA_DQ 20 DDR3 I O G8 SA_DQ 17 DDR3...

Page 120: ...R3 I O J6 SB_DQ 18 DDR3 I O J7 SA_DQ 22 DDR3 I O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir J8 SA_DQ 19 DDR3 I O J9 SA_DQS 2 DDR3 I O J10 SA_DQ 23 DDR3 I...

Page 121: ...O M3 SB_CKE 0 DDR3 O M4 SB_DQ 30 DDR3 I O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir M5 SB_DQS 3 DDR3 I O M6 SA_DQ 25 DDR3 I O M7 SA_DM 3 DDR3 O M8 SA_DQ...

Page 122: ...EF R28 VCC REF R29 VCC REF R30 VCC REF R31 VCC REF Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir R32 VCC REF R33 VCC REF R34 VCC REF R35 VCC REF T1 SA_MA 7 D...

Page 123: ...W4 VDDQ REF W5 SB_BS 1 DDR3 O W6 VSS GND W7 VDDQ REF W8 SB_CK 0 DDR3 O Table 8 48 rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir W9 SB_CK 0 DDR3 O W10 VTT0 REF W26 VSS...

Page 124: ...MOS I CFG 17 AK30 CMOS I COMP0 AT26 Analog I COMP1 G16 Analog I COMP2 AT24 Analog I COMP3 AT23 Analog I DBR AN25 O DMI_RX 0 B24 DMI I DMI_RX 1 D23 DMI I DMI_RX 2 B23 DMI I DMI_RX 3 A22 DMI I DMI_RX 0...

Page 125: ...Ie I PEG_RX 11 A32 PCIe I PEG_RX 12 C30 PCIe I Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir PEG_RX 13 A28 PCIe I PEG_RX 14 B29 PCIe I PEG_RX 15 A30 PCIe I PEG...

Page 126: ...CMOS O PROCHOT AN26 Async GTL I O PSI AN33 Async CMOS O RESET_OBS AP26 Async CMOS O RSTIN AL14 CMOS I RSVD A19 RSVD A20 RSVD AB9 RSVD AC9 RSVD AG9 RSVD AH15 RSVD AH25 Table 8 49 rPGA988A Processor Pin...

Page 127: ...umber Buffer Type Dir RSVD_TP V4 RSVD_TP V5 RSVD_TP W2 RSVD_TP W3 SA_BS 0 AC3 DDR3 O SA_BS 1 AB2 DDR3 O SA_BS 2 U7 DDR3 O SA_CAS AE1 DDR3 O SA_CK 0 AA6 DDR3 O SA_CK 1 Y6 DDR3 O SA_CK 0 AA7 DDR3 O SA_C...

Page 128: ...11 DDR3 I O SA_DQ 47 AL8 DDR3 I O Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir SA_DQ 48 AN8 DDR3 I O SA_DQ 49 AM10 DDR3 I O SA_DQ 50 AR11 DDR3 I O SA_DQ 51 AL...

Page 129: ...ble 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir SB_DQ 0 B5 DDR3 I O SB_DQ 1 A5 DDR3 I O SB_DQ 2 C3 DDR3 I O SB_DQ 3 B3 DDR3 I O SB_DQ 4 E4 DDR3 I O SB_DQ 5 A6 DDR3...

Page 130: ...S 4 AG2 DDR3 I O SB_DQS 5 AL5 DDR3 I O SB_DQS 6 AP5 DDR3 I O SB_DQS 7 AR7 DDR3 I O Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir SB_DQS 0 D5 DDR3 I O SB_DQS 1...

Page 131: ...21 REF VAXG AP16 REF VAXG AP18 REF VAXG AP19 REF VAXG AP21 REF Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VAXG AR16 REF VAXG AR18 REF VAXG AR19 REF VAXG AR2...

Page 132: ...F VCC P35 REF VCC R26 REF VCC R27 REF VCC R28 REF Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VCC R29 REF VCC R30 REF VCC R31 REF VCC R32 REF VCC R33 REF VCC...

Page 133: ...OS I O CSC 2 VID 5 AM33 CMOS I O VID 6 AM35 CMOS O VSS A23 GND VSS A27 GND VSS A29 GND Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VSS A9 GND VSS AA10 GND VS...

Page 134: ...D VSS AL6 GND VSS AL9 GND VSS AM11 GND Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VSS AM14 GND VSS AM17 GND VSS AM2 GND VSS AM20 GND VSS AM25 GND VSS AM27 G...

Page 135: ...GND VSS E35 GND VSS E5 GND VSS E8 GND Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VSS F16 GND VSS F19 GND VSS F22 GND VSS F25 GND VSS F27 GND VSS F30 GND VS...

Page 136: ...49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VSS V10 GND VSS W26 GND VSS W27 GND VSS W28 GND VSS W29 GND VSS W30 GND VSS W31 GND VSS W32 GND VSS W33 GND VSS W34 GND...

Page 137: ...3 REF VTT0 J14 REF VTT0 J15 REF VTT0 J16 REF VTT0 K10 REF VTT0 L10 REF VTT0 N10 REF VTT0 P10 REF VTT0 T10 REF Table 8 49 rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir VTT...

Page 138: ...A _D Q 4 2 S A _ D Q S 5 S A _D Q 4 4 V S S S A _D Q S 4 S A _D Q 3 7 S A _ C S 0 S A _ B S 1 S A _C K 1 B G S B _ D Q 5 8 S B _ D Q S 7 S A _D M 5 V S S S A _ D M 4 V D DQ V S S B F S B _ D Q 5 7 S...

Page 139: ...0 V D D Q S A _ M A 1 1 V D D Q S A _D Q 2 7 V S S S A _ D Q 2 9 V S S S A _D Q 2 2 V S S S A _ D Q 1 1 S B _ D Q 7 B H S A _ M A 3 S A _ M A 4 S A _D Q 3 1 S A _ D Q 3 0 S A _D Q 1 8 S A _ D Q 2 1 S...

Page 140: ...V S S V C A P 2 VC AP 2 V S S V CC VS S VC C V SS V CC V S S V CC V SS VC C VC C P LL VC CP LL P T DI_M T RS T V CC N R ES E T_ O B S PR O CH O T T MS V SS C AT E R R V S S V CC VS S VC C V SS V CC V...

Page 141: ...SS P E G _T X 11 P EG _T X 12 PE G _ T X 13 V S S P EC I T H ER M T R IP VS S VT T _S E N S E FD I_T X 4 F D I_T X 4 F D I_T X 1 F D I_ T X 1 F D I_T X 2 N PE G _R X 3 P EG _ T X 2 PE G _T X 1 2 P EG...

Page 142: ...S I CFG 13 AE2 CMOS I CFG 14 AD1 CMOS I CFG 15 AF8 CMOS I CFG 16 AF6 CMOS I CFG 17 AB7 CMOS I COMP0 AE66 Analog I COMP1 AD69 Analog I COMP2 AC70 Analog I COMP3 AD71 Analog I DBR W71 O DC_TEST_A5 A5 DC...

Page 143: ...CMOS O Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 3 of 37 Pin Name Pin Buffer Type Dir GFX_VID 4 AN71 CMOS O GFX_VID 5 AM67 CMOS O GFX_VID 6 AM70 CMOS O GFX_VR_EN AH69 CMOS O ISENSE A4...

Page 144: ..._TX 4 A38 PCIe O PEG_TX 5 G32 PCIe O PEG_TX 6 B33 PCIe O PEG_TX 7 B35 PCIe O PEG_TX 8 L30 PCIe O PEG_TX 9 A31 PCIe O PEG_TX 10 B32 PCIe O Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 5 of...

Page 145: ...1 BK36 DDR3 O SA_CK 0 BP35 DDR3 O SA_CK 1 BH36 DDR3 O SA_CKE 0 BF20 DDR3 O SA_CKE 1 BK24 DDR3 O SA_CS 0 BH40 DDR3 O SA_CS 1 BJ47 DDR3 I O SA_DM 0 BB10 DDR3 O SA_DM 1 BJ10 DDR3 I O SA_DM 2 BM15 DDR3 O...

Page 146: ...O SA_DQ 53 BJ57 DDR3 I O SA_DQ 54 BK64 DDR3 I O Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 9 of 37 Pin Name Pin Buffer Type Dir SA_DQ 55 BK61 DDR3 I O SA_DQ 56 BJ63 DDR3 I O SA_DQ 57 BF...

Page 147: ...1288 Processor Ball List by Ball Name Sheet 11 of 37 Pin Name Pin Buffer Type Dir SB_DQ 7 BH2 DDR3 I O SB_DQ 8 BG4 DDR3 I O SB_DQ 9 BG1 DDR3 I O SB_DQ 10 BR6 DDR3 I O SB_DQ 11 BR8 DDR3 I O SB_DQ 12 BJ...

Page 148: ...B_DQS 3 BT19 DDR3 I O SB_DQS 4 BT52 DDR3 I O SB_DQS 5 BV55 DDR3 I O SB_DQS 6 BU63 DDR3 I O Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 13 of 37 Pin Name Pin Buffer Type Dir SB_DQS 7 BG69...

Page 149: ...AN28 REF Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 15 of 37 Pin Name Pin Buffer Type Dir VAXG AN30 REF VAXG AN32 REF VAXG_SENSE AF12 Analog O VCAP0 AK50 PWR VCAP0 AK53 PWR VCAP0 AK57 P...

Page 150: ...K59 PWR VCAP2 AK60 PWR VCAP2 AK62 PWR VCAP2 R59 PWR VCAP2 R60 PWR Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 17 of 37 Pin Name Pin Buffer Type Dir VCAP2 U59 PWR VCAP2 U60 PWR VCAP2 W59...

Page 151: ...0 REF Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 19 of 37 Pin Name Pin Buffer Type Dir VCC N42 REF VCC N44 REF VCC N48 REF VCC N51 REF VCC N55 REF VCC P60 REF VCC R41 REF VCC R44 REF VC...

Page 152: ...61 CMOS O VID 1 D61 CMOS O VID 2 D62 CMOS O Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 21 of 37 Pin Name Pin Buffer Type Dir CSC 0 VID 3 A62 CMOS I O CSC 1 VID 4 B63 CMOS I O CSC 2 VID...

Page 153: ...GND VSS AC5 GND VSS AC64 GND Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 23 of 37 Pin Name Pin Buffer Type Dir VSS AC67 GND VSS AD4 GND VSS AD42 GND VSS AD46 GND VSS AD50 GND VSS AD53 G...

Page 154: ...5 GND VSS AL62 GND VSS AM64 GND Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 25 of 37 Pin Name Pin Buffer Type Dir VSS AM8 GND VSS AN37 GND VSS AN4 GND VSS AN41 GND VSS AN44 GND VSS AN48...

Page 155: ...Y12 GND VSS AY14 GND VSS AY15 GND Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 27 of 37 Pin Name Pin Buffer Type Dir VSS AY17 GND VSS AY19 GND VSS AY21 GND VSS AY23 GND VSS AY24 GND VSS A...

Page 156: ...ND VSS BK10 GND VSS BK34 GND Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 29 of 37 Pin Name Pin Buffer Type Dir VSS BK53 GND VSS BK60 GND VSS BK63 GND VSS BL1 GND VSS BL20 GND VSS BL28 GN...

Page 157: ...G15 GND VSS G20 GND VSS G24 GND Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 31 of 37 Pin Name Pin Buffer Type Dir VSS G30 GND VSS G43 GND VSS G47 GND VSS G48 GND VSS G53 GND VSS G57 GND...

Page 158: ...all List by Ball Name Sheet 33 of 37 Pin Name Pin Buffer Type Dir VSS W53 GND VSS W57 GND VSS W6 GND VSS W62 GND VSS W69 GND VSS_SENSE F63 Analog O VSS_SENSE_VTT R12 Analog O VSSAXG_SENSE AF10 Analog...

Page 159: ...VTT0 U30 REF Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 35 of 37 Pin Name Pin Buffer Type Dir VTT0 U32 REF VTT0 U33 REF VTT0 U35 REF VTT0 W23 REF VTT0 W24 REF VTT0 W26 REF VTT0 W28 REF...

Page 160: ...GND A38 PEG_TX 4 PCIe O A40 VSS GND A41 ISENSE Analog I Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 37 of 37 Pin Name Pin Buffer Type Dir A43 VCC REF A45 VSS GND A47 VCC REF A48 VSS GND...

Page 161: ...ND AB39 VSS GND Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 3 of 37 Pin Pin Name Buffer Type Dir AB41 VCC REF AB42 VSS GND AB44 VCC REF AB46 VSS GND AB48 VCC REF AB50 VSS GND AB51 VCC...

Page 162: ...G REF AF19 VAXG REF AF21 VAXG REF Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 5 of 37 Pin Pin Name Buffer Type Dir AF23 VAXG REF AF24 VAXG REF AF26 VAXG REF AF28 VAXG REF AF30 VTT0 REF...

Page 163: ...OS I AJ70 VSS GND AK1 CFG 2 CMOS I Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 7 of 37 Pin Pin Name Buffer Type Dir AK2 CFG 3 CMOS I AK4 CFG 4 CMOS I AK7 BCLK DIFF CLK I AK8 BCLK DIFF...

Page 164: ...MON CMOS O Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 9 of 37 Pin Pin Name Buffer Type Dir AL71 GFX_DPRSLPVR CMOS O AM10 VTT0 REF AM2 CFG 1 CMOS I AM5 SM_DRAMPWROK Async CMOS I AM7 VC...

Page 165: ...AR41 VCAP1 PWR AR42 VSS GND Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 11 of 37 Pin Pin Name Buffer Type Dir AR44 VCAP1 PWR AR46 VSS GND AR48 VCAP0 PWR AR50 VSS GND AR51 VCAP0 PWR AR...

Page 166: ...T0_DDR REF AW23 VTT0_DDR REF Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 13 of 37 Pin Pin Name Buffer Type Dir AW24 VTT0_DDR REF AW26 VTT0_DDR REF AW28 VTT0_DDR REF AW30 VTT0_DDR REF A...

Page 167: ...CIe I Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 15 of 37 Pin Pin Name Buffer Type Dir B23 PEG_RX 10 PCIe I B25 PEG_RX 9 PCIe I B26 PEG_RX 8 PCIe I B28 PEG_RX 7 PCIe I B30 PEG_TX 9 PC...

Page 168: ...DDR3 I O BD14 VSS GND Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 17 of 37 Pin Pin Name Buffer Type Dir BD15 VDDQ REF BD17 VDDQ REF BD19 VDDQ REF BD21 VDDQ REF BD23 VDDQ REF BD24 VDDQ...

Page 169: ...DDR3 I O BG24 SA_DQ 30 DDR3 I O Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 19 of 37 Pin Pin Name Buffer Type Dir BG25 SA_DQ 31 DDR3 I O BG32 SA_MA 4 DDR3 O BG34 SA_MA 3 DDR3 O BG36 V...

Page 170: ...I O BK32 SA_MA 6 DDR3 O BK34 VSS GND BK36 SA_CK 1 DDR3 O BK43 SA_CAS DDR3 O Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 21 of 37 Pin Pin Name Buffer Type Dir BK44 SA_DQS 4 DDR3 I O BK...

Page 171: ...0 SB_MA 1 DDR3 O BP33 SA_MA 1 DDR3 O Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 23 of 37 Pin Pin Name Buffer Type Dir BP35 SA_CK 0 DDR3 O BP39 SM_RCOMP 1 Analog BP42 VSS GND BP46 SB_C...

Page 172: ...3 O BU32 VSS GND BU33 SB_CK 0 DDR3 O Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 25 of 37 Pin Pin Name Buffer Type Dir BU35 VDDQ REF BU37 VSS GND BU39 SB_CK 1 DDR3 O BU40 VDDQ REF BU42...

Page 173: ...VD D10 VSS GND D12 PEG_RCOMPO Analog I D13 VSS GND D15 PEG_RX 15 PCIe I D17 VSS GND D19 PEG_RX 13 PCIe I Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 27 of 37 Pin Pin Name Buffer Type D...

Page 174: ...5 PCIe I G28 PEG_RX 4 PCIe I Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 29 of 37 Pin Pin Name Buffer Type Dir G30 VSS GND G32 PEG_TX 5 PCIe O G34 PEG_RX 2 PCIe I G38 PEG_RX 1 PCIe I G...

Page 175: ...VSS GND Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 31 of 37 Pin Pin Name Buffer Type Dir K60 VCC REF K62 BPM 4 GTL I O K64 VSS GND K65 BPM 3 GTL I O K69 BPM 6 GTL I O K71 BCLK_ITP DI...

Page 176: ...ync GTL I O N70 RESET_OBS Async CMOS O P1 FDI_TX 3 FDI O Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 33 of 37 Pin Pin Name Buffer Type Dir P4 VSS GND P34 PEG_RX 3 PCIe I P60 VCC REF P6...

Page 177: ...2 VSS GND U44 VCC REF Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 35 of 37 Pin Pin Name Buffer Type Dir U46 VSS GND U48 VCC REF U50 VSS GND U51 VCC REF U53 VSS GND U55 VCC REF U57 VSS...

Page 178: ...50 VSS GND W51 VCC REF W53 VSS GND W55 VCC REF W57 VSS GND W59 VCAP2 PWR W60 VCAP2 PWR W62 VSS GND W64 VCAP0_VSS_SENSE W66 VCAP0_SENSE W69 VSS GND W71 DBR O Y2 DPLL_REF_SSCLK DIFF CLK I Y67 VCCPWRGOOD...

Page 179: ...Datasheet 179 Processor Pin and Signal Information 8 2 Package Mechanical Information Figure 8 25 rPGA Mechanical Package Sheet 1 of 2...

Page 180: ...Processor Pin and Signal Information 180 Datasheet Figure 8 26 rPGA Mechanical Package Sheet 2 of 2...

Page 181: ...Datasheet 181 Processor Pin and Signal Information Figure 8 27 BGA Mechanical Package Sheet 2 of 2...

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