Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor, Datasheet

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Electrical Specifications
36 Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
Notes:
1. 1300 mVpp swing is recommended when CPU to CPU or CPU to IOH length is within 2” of PDG max trace
length. Note that default value is 1200 mVpp.
2. Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above
3.2 GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the
receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can
allow the transmitter AC CM noise to pass.
3. Measured with neighboring lines being quiet and the remaining lines toggling PRBS patterns.
4. DC CM can be relaxed to 0.20 and 0.30 Vdiffp-p swing if RX has wide DC common mode range.
5. Based on transmitting a PRBS pattern.
V
Tx-cm-ac-pin
Transmitter output AC common
mode, defined as ((V
D+
+ V
D-
)/2 -
V
Tx-cm-dc-pin
)
-0.0375 0.0375 Fraction of
V
Tx-diff-pp-pin
2
TX
duty-pin
Average of absolute UI-UI jitter -0.06 0.06 UI
TX
jitUI-UI-1E-7-pin
UI-UI jitter measured at Tx output
pins with 1E-7 probability.
-0.085 0.085 UI 3
TX
jitUI-UI-1E-9-pin
UI-UI jitter measured at Tx output
pins with 1E-9 probability.
-0.09 0.09 UI
TX
clk-acc-jit-N_UI-1E-7
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-7
probability.
0 0.15 UI
TX
clk-acc-jit-N_UI-1E-9
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-9
probability.
0 0.17 UI
T
Tx-data-clk-skew-pin
Delay of any data lane relative to
clock lane, as measured at Tx
output
-0.5 0.5 UI
V
Rx-diff-pp-pin
Voltage eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
155 1400 mV 2, 5
T
Rx-diff-pp-pin
Timing eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9 (UI)
0.61 1 UI
T
Rx-data-clk-skew-pin
Delay of any data lane relative to
the clock lane, as measured at the
end of Tx+ channel. This
parameter is a collective sum of
effects of data clock mismatches
in Tx and on the medium
connecting Tx and Rx.
-1 4 UI
V
Rx-CLK
Forward CLK Rx input voltage
sensitivity (differential pp)
150 mV
V
Rx-cm-dc-pin
DC common mode ranges at the
Rx input for any data or clock
channel
90 350 mV
V
Rx-cm-ac-pin
AC common mode ranges at the
Rx input for any data or clock
channel, defined as:
((V
D+
+ V
D-
/2 - V
RX-cm-dc-pin
)
-50 50 mV
Table 2-10. Intel ® Itanium ® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel ® QPI at 6.4 GT/s (Sheet 2 of 2)
Symbol Parameter Min Nom Max Unit Notes