Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet Download

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Intel

Itanium

Processor 9300 Series and 9500 Series Datasheet

163

Signal Definitions

FORCEPR_N

When logic 0, forces processor power reduction.
Refer to the

Intel

Itanium

9300 Series Processor and Intel

Itanium

Processor

9500 Series Platform Design Guide

for a detailed signal description.

LRGSCLSYS

The header mode is selected by the LRGSCLSYS strapping pin value sampled only

during COLD reset. LRGSCLSYS, when tied to VCCIO using a 50 ohm resistor, puts

the processor in extended header mode, and LRGSCLSYS, when tied to GND, puts

the processor in standard header mode.

MEM_THROTTLE_L

When this pin is asserted on the Intel

Itanium

Processor 9300 Series, the

internal memory controllers throttle the memory command issue rate to a

configurable fraction of the nominal command rate settings. This pin is not used on

the Intel

Itanium

9500 Processor Series.

PIR_SCL

(Processor Information ROM Serial Clock): The PIR_SCL input clock is used to clock

data into and out of the on package PIROM device. This signal applies to the

EEPROM, which is composed of the PIROM and the OEM Scratch PAD.

PIR_SDA

I/O

(Processor Information ROM Serial Data): The PIR_SDA pin is a bidirectional signal

for serial data transfer. This signal applies to the EEPROM, which is composed of the

PIROM and the OEM Scratch PAD.

PIR_A0, PIR_A1

(Processor Information ROM Address[0:1]): The PIR_A[0:1] pins are used as the

PIROM memory address selection signals. This bus applies to the EEPROM, which is

composed of the PIROM and the OEM Scratch PAD.

SM_WP

WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch

EEPROM is write-protected when this input is pulled high to VCC33_SM.

PRBMODE_REQ_N

Input from Extended Debug Port (XDP) to make a probe mode request.

PRBMODE_RDY_N

Output to XDP to acknowledge probe mode request.

PROCHOT_N

The assertion of PROCHOT_N (processor hot) indicates that the processor die

temperature has reached its thermal limit.

PROCTYPE

PROCTYPE output informs the platform the processor type. PROCTYPE is tied to VSS

internally to indicate the Intel

Itanium

9300 Processor Series and VCC33_SM

internally to indicate the Intel

Itanium

9500 Processor Series. This pin does not

require a platform pull-up or pull-down.

PWRGOOD

The processor requires this signal to be a clean indication that all the processor

clocks and power supplies are stable and within their specifications. “Clean” implies

that the signal will remain low (capable of sinking leakage current), without

glitches, from the time that the power supplies are turned on until they come within

specification. The signal must then transition monotonically to a high state.

PWRGOOD can be driven inactive at any time, but clocks and power must again be

stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to

protect internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

RESET_N

Asserting the RESET_N signal resets the processor to a known state and invalidates

its internal caches without writing back any of their contents. BOOTMODE[0:1]

signals are sampled during all RESET_N assertions for selecting appropriate

BOOTMODE.

RSVD

These pins are reserved and must be left unconnected.

SKTID[2:0]

Socket ID strapping pins.

To pull any of these inputs high, they should be strapped

to VCCIO, and to pull them low, they should be strapped to VSS. SKTID[2:0]

partially determine the node address.

SMBCLK

The SMBus Clock (SMBCLK) signal is an input clock to the system management

logic which is required for operation of the system management features of the

Intel

Itanium

Processor 9300 Series and Intel

Itanium

9500 Series

processors. This clock is driven by the SMBus controller and is asynchronous to

other clocks in the processor. This is an open drain signal. Intel

Itanium

Processor 9300 Series and Intel

Itanium

9500 Series are Slave only.

SMBDAT

I/O

The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal

provides the single-bit mechanism for transferring data between SMBus devices.

This is an open drain signal. Intel

Itanium

Processor 9300 Series and Intel

Itanium

9500 Series are Slave only.

Table 7-1.

Signal Definitions for the Intel

Itanium

Processor 9300 Series and Intel

Itanium

9500 Series (Sheet 5 of 8)

Name

Type

Description

Summary of Contents for BX80569Q9550 - Core 2 Quad 2.83 GHz Processor

Page 1: ... 20 MB L3 Cache 9330 Intel Itanium Processor Quad Core 1 46 1 33 GHz with 16 MB L3 Cache 9320 Intel Itanium Processor Dual Core 1 60 GHz Fixed Frequency with 10 MB L3 Cache 9310 Intel Itanium Processor Eight Core 2 53 GHz with 32 MB LLC Cache 9560 Intel Itanium Processor Four Core 2 40 GHz with 32 MB LLC Cache 9550 Intel Itanium Processor Eight Core 2 13 GHz with 24 MB LLC Cache 9540 Intel Itanium...

Page 2: ...ndefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to devia...

Page 3: ...bsolute Maximum Ratings 39 2 5 2 Intel Itanium Processor 9500 Series Absolute Maximum Ratings 39 2 6 Processor DC Specifications 39 2 6 1 Flexible Motherboard Guidelines for the Intel Itanium Processor 9300 Series 40 2 6 2 Flexible Motherboard Guidelines for the Intel Itanium Processor 9500 Series 43 2 6 3 Intel Itanium Processor 9300 Series Uncore Core and Cache Tolerances 44 2 6 4 Intel Itanium ...

Page 4: ...Package Markings 130 5 Thermal Specifications 133 5 1 Thermal Features 133 5 1 1 Digital Thermometer 134 5 1 2 Thermal Management 135 5 1 3 Thermal Alert 136 5 1 4 TCONTROL 137 5 1 5 Thermal Warning 137 5 1 6 Thermal Trip 137 5 1 7 PROCHOT 138 5 1 8 FORCEPR_N Signal Pin 138 5 1 9 Ararat Voltage Regulator Thermal Signals 138 5 2 Package Thermal Specifications and Considerations 139 5 3 Storage Cond...

Page 5: ... Point Representation 57 2 17 Supported Power up Voltage Sequence Timing Requirements for the Intel Itanium Processor 9300 Series 66 2 18 Supported Power up Sequence Timing Requirements for Intel Itanium Processor 9500 Series 67 2 19 Supported Power down Voltage Sequence Timing Requirements 69 2 20 RESET_N and SKITID Timing for Warm and Cold Resets 70 4 1 Processor Package Assembly Sketch 119 4 2 ...

Page 6: ... Series 40 2 16 FMB 130W Current Specifications for the Intel Itanium Processor 9300 Series 41 2 17 FMB 155W 185W Current Specifications for the Intel Itanium Processor 9300 Series 42 2 18 FMB Voltage Specifications for the Intel Itanium Processor 9500 Series 43 2 19 FMB 170W and 130W Current Specifications for the Intel Itanium Processor 9500 Series 44 2 20 VCCUNCORE Static and Transient Toleranc...

Page 7: ...l Table Intel Itanium Processor 9500 Series 110 3 7 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9300 Series 111 3 8 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series 113 3 9 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9300 Series 114 3 10 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series 116...

Page 8: ...9300 Series and 9500 Series Datasheet Revision History Document Number Revision Number Description Date 322821 002 Initial release of the 9300 9500 document November 2012 322821 001 Initial release of the document February 2010 ...

Page 9: ...ant execution resources Additionally it focuses on dynamic run time optimizations to enable the compiled code schedule to flow at high throughput This strategy increases the synergy between hardware and software and leads to greater overall performance The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series system interface with its 4 full width and 2 half width Intel Quick...

Page 10: ...Introduction 10 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 11: ...anagement Built in processor information ROM PIROM Built in programmable EEPROM Hot Plug Socket Hot add and hot removal Double Device Data Correction DDDC for x4 DRAMs plus correction of a single bit error Single Device Data Correction SDDC for x8 DRAMs plus correction of a single bit error Intel QuickPath Interconnect Dynamic Link Width Reduction Intel QuickPath Interconnect Clock Fail Safe Featu...

Page 12: ...essors and a system interface unit Each processor core provides a 6 wide 8 stage deep execution pipeline The resources consist of six integer units six multimedia units two load and two store units three branch units and two floating point units each capable of extended double and single precision arithmetic The hardware employs dynamic prefetch branch prediction a register scoreboard and non bloc...

Page 13: ...DRAMs plus correction support of a single bit error Single Device Data Correction SDDC for x8 and x4 DRAMs plus correction of a single bit error Intel QuickPath Interconnect Dynamic Link Width Reduction Intel QuickPath Interconnect Clock Fail Safe Feature Intel QuickPath Interconnect Hot Add and Removal Memory DIMM and Rank Sparing Memory Scrubbing Memory Mirroring and Memory Migration Intel Turbo...

Page 14: ...metic The hardware employs dynamic prefetch branch prediction a register scoreboard and non blocking caches to optimize for compile time non determinism 32 additional stacked general registers are provided over the Intel Itanium Processor 9300 Series and hardware support is provided for denormal unnormal and pseudo normal operands for floating point software assist offloading New instructions on t...

Page 15: ...s the System Interface Each processor core has it own Caching Agent CPE The CPE interfaces between the processor core and the Intel QuickPath Interconnect The Intel Itanium Processor 9300 Series processor has two Home Agents Bbox The Bbox interfaces between the memory controller and the Intel QuickPath Interconnect and supports a directory cache Each Bbox interfaces with a memory controllers Zbox ...

Page 16: ... and Cbox provide the supports for the two Intel QPI Caching Agents The processor has two Home Agents Bbox The Bbox interfaces between the memory controller and the Intel QuickPath Interconnect and supports a directory cache Each memory controller supports two Intel Scalable Memory Interconnects Intel SMI in lockstep The Intel SMI are the interconnects to Scalable Memory Buffer The Intel Itanium P...

Page 17: ...or 9500 Series processor power through a special built in microcontroller that manipulates voltage and frequency PAL communicates requested P states to this controller through internal registers As shown in Figure 1 3 Itanium architecture based firmware consists of several major components Processor Abstraction Layer PAL System Abstraction Layer SAL Unified Extensible Firmware Interface UEFI and A...

Page 18: ...y is not found the processor raises a Key Miss fault If a matching Key is found access to the page is qualified by additional read write and execute protection checks specified by the matching protection key register If these checks fail a Key Permission fault is raised Upon receipt of a Key Miss or Key Permission fault software can implement the desired security policy for the protection domain S...

Page 19: ...ported Intel QPI Link self healing Supported Supported Intel QPI Clock fail safe Supported Supported Intel QPI Data scrambling Supported Required Intel QPI Periodic retraining Not Supported Required1 Integrated memory controllers 2 2 Intel SMI Interface Intel 7500 Scalable Memory Buffer 4 8 GT s Intel 7500 Scalable Memory Buffer 4 8 GT s Intel 7510 Scalable Memory Buffer 6 4 GT s Intel SMI Hot plu...

Page 20: ...ferent core frequencies cache sizes and mixing Intel Itanium Processor 9300 Series with Intel Itanium Processor 9500 Series is not supported and has not been validated by Intel Operating system support for multiprocessing with mixed components should also be considered 1 6 Terminology In this document the processor refers to the Intel Itanium Processor 9300 Series and or Intel Itanium Processor 95...

Page 21: ...e following documents Note Contact your Intel representative or check http developer intel com for the latest revision of the reference documents Document Name Intel Itanium Processor 9300 Series and 9500 Series Specification Update Intel Itanium Architecture Software Developer s Manual Volume 1 Application Architecture Intel Itanium Architecture Software Developer s Manual Volume 2 System Archite...

Page 22: ...Introduction 22 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 23: ...ng of a pair of opposite polarity D D signals is VSS Termination resistors are provided on the processor silicon and are terminated to VSS thus eliminating the need to terminate the links on the system board for the Intel QuickPath Interconnect and FB DIMM signals When designing a system Intel strongly recommends that design teams perform analog simulations of the Intel QuickPath Interconnect and ...

Page 24: ...N 10 0 FBD1SBO C D P N 10 0 VSS XDPOCPD_N 7 0 TRIGGER_N 1 0 XDPOCPFRAME_N XDPOCP_STRB_IN_N PRBMODE_REQST_N XDPOCP_STRB_OUT_N PRBMODE_RDY_N VCCIO Table 2 2 Signal Groups Sheet 1 of 3 Signal Group Buffer Type Signals 1 2 3 Differential System Reference Clock Differential CMOS In Differential Pair SYSCLK SYSCLK_N SYSUTST_REFCLK_N SYSUTST_REFCLK Intel QuickPath Interconnect Signal Groups Differential ...

Page 25: ...r up Single ended GTL Input PWRGOOD RESET_N Thermal Single ended GTL Open Drain Output GTL Input PROCHOT_N THERMTRIP_N THERMALERT_N FORCEPR_N VID Port4 Intel Itanium Processor 9300 Series Single ended CMOS Output VID_VCCCORE 6 0 VID_VCCCACHE 5 0 VID_VCCUNCORE 6 0 SVID Port4 Intel Itanium Processor 9500 Series Single ended GTL Output SVID_CLK GTL I O SVD_DATIO GTL Input SVID_ALERT_N Voltage Regulat...

Page 26: ... types including inputs outputs and input outputs include an on die pull up resistor between 4 kOhms and 8 7 kOhms Recommended values for external pull downs on the inputs and input output signals must meet the Vil specification for that buffer Table 2 2 Signal Groups Sheet 3 of 3 Signal Group Buffer Type Signals 1 2 3 Table 2 3 Intel QuickPath Interconnect Intel Scalable Memory Interconnect Refer...

Page 27: ...3 7 Defined as the total variation of all crossing voltages of Rising SYSCLK and falling SYSCLK_N This is the maximum allowed variance in Vcross for any particular system See Figure 2 2 8 Defined as the maximum instantaneous voltage including overshoot See Figure 2 2 9 Defined as the minimum instantaneous voltage including undershoot See Figure 2 2 10 TStable is the time the differential clock mus...

Page 28: ...I For Intel QPI slow boot up speed the signaling rate is defined as 1 4 the rate of the system reference clock For example a 133 MHz system reference clock would have a forwarded clock frequency of 33 33 MHz and the signaling rate would be 66 67 MT s The transfer rates available for the processor are shown in Table 2 4 Transmitter and receiver parameters for Intel QPI slow mode Intel QPI and Intel...

Page 29: ... of the differential transmitter output data or clock 6 12 V ns VTx diff pp pin Transmitter differential swing 900 1300 mV RTX Transmitter termination resistance 37 4 47 6 Ω 4 ZTX_LINK_DETECT Link Detection Resistor 500 2000 Ω VTX_LINK_DETECT Link Detection Resistor Pull up Voltage max VCCIO V TDATA_TERM_SKEW Intel QPI Skew between first to last data termination meeting ZRX_LOW_CM_DC 600 UI 2 TDAT...

Page 30: ...urn loss from 2GHz to 4GHz 6 dB 7 Table 2 6 Intel Itanium Processor 9300 Series Receiver Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 4 8 GT Sheet 1 of 2 Symbol Parameter Min Nom Max Units Notes RRX RX termination resistance 37 4 47 6 Ω 3 TRx data clk skew pin Delay of any data lane relative to the clock lane as measured at the end of Tx channel This parameter is a coll...

Page 31: ...4 Events SMI BERLane Bit Error Rate per lane valid for 4 8 and 6 4 GT s 1 0E 12 Events Figure 2 6 TX Equalization Diagram Table 2 6 Intel Itanium Processor 9300 Series Receiver Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 4 8 GT Sheet 2 of 2 Symbol Parameter Min Nom Max Units Notes C 1 C2 C0 C1 Vsust Vpre Vpost Vpre A C 1 C0 C1 C2 Vsust A C 1 C0 C1 C2 Vpost A C 1 C0 C1 ...

Page 32: ...cessor 9500 Series This section contains information for slow boot up speed 1 4 frequency of the reference clock 4 8 GT s and 6 4 GT s for Intel QPI and Intel SMI For Intel QPI slow boot up speed the signaling rate is defined as 1 4 the rate of the system reference clock For example a 133 MHz system reference clock would have a forwarded clock frequency of 33 33 MHz and the signaling rate would be...

Page 33: ...6 66 MT s see note 1 2 40 GHz 4 8 GT s 3 2 GHz 6 4 GT s Notes 1 This speed is the 1 4 SysClk Frequency Table 2 8 Intel Itanium Processor 9500 Series Link Speed Independent Specifications Sheet 1 of 2 Symbol Parameter Min Nom Max Unit Notes UIavg Average UI size at G GT s Where G 4 8 6 4 and so on 0 999 nominal 1000 G 1 001 nominal psec Tslew rise fall pin Defined as the slope of the rising or fall...

Page 34: ...ition for the receiver when only the minimum termination is connected Table 2 9 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel QPI Channel at 4 8 GT s Sheet 1 of 2 Symbol Parameter Min Nom Max Unit Notes VTx diff pp pin Transmitter differential swing 900 1400 mV 1 ZTX_LOW_CM_DC DC resistance of Tx terminations at half the single ended swing which is usually...

Page 35: ... clock channel measured with a cumulative probability of 1E 9 UI 0 63 1 UI TRx data clk skew pin Delay of any data lane relative to the clock lane as measured at the end of Tx channel This parameter is a collective sum of effects of data clock mismatches in Tx and on the medium connecting Tx and Rx 1 3 UI VRx CLK Forward CLK Rx input voltage sensitivity differential pp 180 mV VRx cm dc pin DC comm...

Page 36: ...lity 0 09 0 09 UI TXclk acc jit N_UI 1E 7 p p accumulated jitter out of transmitter over 0 n N UI where N 12 measured with 1E 7 probability 0 0 15 UI TXclk acc jit N_UI 1E 9 p p accumulated jitter out of transmitter over 0 n N UI where N 12 measured with 1E 9 probability 0 0 17 UI TTx data clk skew pin Delay of any data lane relative to clock lane as measured at Tx output 0 5 0 5 UI VRx diff pp pi...

Page 37: ...mode defined as average of VD and VD 0 23 0 27 Fraction of VTx diff pp pin 3 VTx cm ac pin Transmitter output AC common mode defined as VD VD 2 VTx cm dc pin 0 0375 0 0375 Fraction of VTx diff pp pin TXduty UI pin This is computed as absolute difference between average value of all UI with that of average of odd UI which in magnitude would equal absolute difference between average of all UI and av...

Page 38: ...um ratings listed in Table 2 13 are applicable for the 130 W 155 W and 185 W parts Table 2 14 specifies absolute maximum and minimum ratings for the Intel Itanium Processor 9500 Series Within operational maximum and minimum limits the processor functionality and long term reliability can be expected The processor maximum ratings listed in Table 2 14 are applicable for the 130 W and 170 W parts At ...

Page 39: ...oot and undershoot voltage guidelines for input output and I O signals are outlined in Section 2 6 4 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 2 6 Processor DC Specifications Table 2 15 through Table 2 35 list the DC specifications for the Intel Itanium Processor 9300 Series and 9500 Series and are valid only while meeting specification...

Page 40: ...eter Min Typ Max Units Notes VIDRange VCCCORE VID Range 0 8 1 1 1 35 V UVIDRange VCCUNCORE VID Range 0 8 1 1 1 35 V VCCUNCORE Processor uncore supply voltage See Table 2 20 and Figure 2 10 V 2 1 Notes 1 The voltage specification requirements are measured across the VCCUNCORESENSE and VSSUNCORESENSE pins using an oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum capacitance...

Page 41: ...be and or the scope at 1 MHz BW limit capture waveform B channel 2 Step 2 calculate A B use scope Math function subtract channel 1 channel 2 Table 2 16 FMB 130W Current Specifications for the Intel Itanium Processor 9300 Series Symbol Parameter Max Units Notes ICC_CORE ICC for core 151 A ICC_CORE_TDC Thermal Design Current for Core 100 A 1 Notes 1 ICC_CORE_TDC is the sustained DC equivalent curren...

Page 42: ...P can be as high as 130A peak to peak dICC_CORE dt Slew rate for core at Ararat output 154 A us ICC_UNCORE ICC for uncore 50 A ICC_UNCORE_TDC Thermal Design Current for Uncore 43 A 3 3 ICC_UNCORE_TDC is the sustained DC equivalent current that the processor uncore is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regula...

Page 43: ...ltage See Table 2 24 and Figure 2 14 V 2 3 4 2 These voltages are target only A variable voltage source should exist on systems in th e event that a different voltage is required See the Ararat II Voltage Regulator Module Design Guide for more information 3 Uncore and Core voltage and Current Rating are at the Package Pad 4 The voltage specification requirements are measured across the VCCCORESENS...

Page 44: ...ture and asserting the VR_FAN_N VR_THERMALERT_N VR_THERMTRIP_N signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only VR_THERMALTERT_N is monitored by the processor Please see the Ararat II Voltage Regulator Module Design Guide for further details The processor is capable of drawing ICC_CORE_TDC indefinitely ICC_CORE_STEP Max Load step for core 1...

Page 45: ...efer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 VDC max VID Rll ICC 5 mV VDC min VID Rll ICC 35mV Rll 4 mW ICC_UNCORE V CC_Max VCC_Typ VCC_Min 0 VID 0 VID 0 02 VID 0 04 5 VID 0 02 VID 0 04 VID 0 06 10 VID 0 04 VID 0 06 VID 0 08 15 VID 0 06 VID 0 08 VID 0 1 20 VID 0 08 VID 0 1 VID 0 12 25 VID 0 1 VID 0 12 VID 0 14 30 VID 0 12 VID 0 14...

Page 46: ... 0 07 40 VID 0 034 VID 0 054 VID 0 074 45 VID 0 038 VID 0 058 VID 0 078 50 VID 0 043 VID 0 063 VID 0 083 55 VID 0 047 VID 0 067 VID 0 087 60 VID 0 051 VID 0 071 VID 0 091 65 VID 0 055 VID 0 075 VID 0 095 70 VID 0 06 VID 0 08 VID 0 1 75 VID 0 064 VID 0 084 VID 0 104 80 VID 0 068 VID 0 088 VID 0 108 85 VID 0 072 VID 0 092 VID 0 112 90 VID 0 077 VID 0 097 VID 0 117 95 VID 0 081 VID 0 101 VID 0 121 10...

Page 47: ... for voltage regulator circuits must be taken from processor VCC and VSS pins Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 VDC max VID Rll ICC 4 mV VDC nom VID Rll ICC 19 mV VDC min VID Rll ICC 34mV Rll 0 85 mΩ Figure 2 11 VCCCORE Static and Transient Tolerance for Intel Itanium Processor 9300 Series Table 2 21 VCCCORE Static and...

Page 48: ...de for socket load line guidelines and VR implementation 4 VDC max VID Rll ICC 5 mV VDC min VID Rll ICC 35 mV Rll 3 45 mW ICC_CACHE V CC_Max VCC_Typ VCC_Min 0 VID 0 VID 0 02 VID 0 04 5 VID 0 017 VID 0 037 VID 0 057 10 VID 0 035 VID 0 055 VID 0 075 15 VID 0 052 VID 0 072 VID 0 092 20 VID 0 069 VID 0 089 VID 0 109 25 VID 0l 086 VID 0 106 VID 0 126 30 VID 0 104 VID 0 124 VID 0 144 35 VID 0 121 VID 0 ...

Page 49: ...ENSE and VSSUNCORESENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins Refer to the Ararat II Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 VDC max VID Rll ICC 15 mV VDC min VID Rll ICC 15 mV Rll 1 25 mOhm ICC_UNCORE V CC_Max VCC_Typ VCC_Min 0 VID 0 015 VID VID 0 015 5 VID 0 00875 VID 0 0...

Page 50: ...oad Line for the Intel Itanium Processor 9500 Series 0 1650 0 1450 0 1250 0 1050 0 0850 0 0650 0 0450 0 0250 0 0050 0 0150 0 20 40 60 80 100 120 Normalized VccUnCore V IccUnCore A VccUnCore Tolerance Band VccUnCore ACMax V VccUnCore DCMax V Normalized VccUnCore V VccUnCore DCMin V VccUnCore ACMin V VccUnCore Tolerance Band 0 1650 0 1450 0 1250 0 1050 0 0850 0 0650 0 0450 0 0250 0 0050 0 0150 0 20 ...

Page 51: ...CC and VSS pins Refer to the Ararat II Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 VDC max VID Rll ICC 15 mV VDC nom VID Rll ICC VDC min VID Rll ICC 15 mV Rll 2 mOhms ICC_CORE V CC_Max VCC_Typ VCC_Min 0 VID 0 015 VID VID 0 015 5 VID 0 005 VID 0 010 VID 0 025 10 VID 0 005 VID 0 020 VID 0 035 15 VID 0 015 VID 0 030 VID 0 045 20 VID 0 025 VID 0 040 VI...

Page 52: ...t or undershoot waveform occurs every other clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot waveform occurs one time in every 200 clock cycles The highest frequency of assertion of any differential signal is every active edge of its associated clock not the reference clock So an AF 1 indicates that the specific overshoot or undershoot waveform occurs every cycle 2 6...

Page 53: ...vershoot for single ended signals 1 36 V VMIN US SE Undershoot for single ended signals 0 22 V VABSMAX OS SE Absolute Max for single ended signals 1 46 V VABSMIN US SE Absolute Min for single ended signals 0 32 V VMAX OS DIFF Overshoot for Intel QPI and Intel SMI signals 1 3 V VMAX US DIFF Undershoot for Intel QPI and Intel SMI signals 0 3 V VABSMAX OS DIFF Absolute Max for Intel QPI and Intel SMI...

Page 54: ... the input at the top of the package sensed by the processor VOH and VOL are for the output levels on the package pins at the bottom of the package VOL Output Low Voltage V 1 2 3 4 Table 2 29 TAP and System Management Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 VCCIO 0 5 0 2 V VIH Input High Voltage VCCIO 0 5 0 2 VCCIO V VOH Output High Voltage VCCIO 0 2 VCC...

Page 55: ...OH Output High Voltage VCCIO 0 1 VCCIO V 1 Notes 1 These parameters are not tested and are based on design simulations VOL Output Low Voltage 0 0 1 V 1 IOLeak Output Leakage Current 200 200 µA 1 2 2 Leakage to VSS with pin held at 1 1 V and leakage to 1 1 V with pin held at VSS Table 2 32 SVID Group DC Specifications for the Intel Itanium Processor 9500 Series Symbol Parameter Min Max Unit Notes V...

Page 56: ...IILeak Input Leakage Current 1000 200 µA 2 2 With input leakage current measured at the pin with 0V and with 1 1V supplied to the pin System designers are advised to check the tolerance of their voltage regulator solutions to ensure Vpin of 1 1 V IOLeak Output Leakage Current 1000 200 µA Table 2 35 PIROM Signal Group DC Specifications Symbol Parameter Min TYP Max Unit Notes VIL Input Low Voltage 0...

Page 57: ...rocessor 9500 Series can drive different VID_VCCCORE and VID_VCCUNCORE settings during normal operation Table 2 36 and Table 2 37 specify the voltage levels corresponding to the state of VID_VCCCORE and VID_VCCUNCORE for the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series respectively A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level...

Page 58: ...000 0C 0 0 0 1 1 0 0 1 4625 3A 0 1 1 1 0 1 0 0 8875 0D 0 0 0 1 1 0 1 1 4500 3B 0 1 1 1 0 1 1 0 8750 0E 0 0 0 1 1 1 0 1 4375 3C 0 1 1 1 1 0 0 0 8625 0F 0 0 0 1 1 1 1 1 4250 3D 0 1 1 1 1 0 1 0 8500 10 0 0 1 0 0 0 0 1 4125 3E 0 1 1 1 1 1 0 0 8375 11 0 0 1 0 0 0 1 1 4000 3F 0 1 1 1 1 1 1 0 8250 12 0 0 1 0 0 1 0 1 3875 40 1 1 1 0 0 0 0 0 8125 13 0 0 1 0 0 1 1 1 3750 41 1 1 1 0 0 0 1 0 8000 14 0 0 1 0 1...

Page 59: ...450 03 0 0 0 0 0 0 1 1 0 260 2A 0 0 1 0 1 0 1 0 0 455 04 0 0 0 0 0 1 0 0 0 265 2B 0 0 1 0 1 0 1 1 0 460 05 0 0 0 0 0 1 0 1 0 270 2C 0 0 1 0 1 1 0 0 0 465 06 0 0 0 0 0 1 1 0 0 275 2D 0 0 1 0 1 1 0 1 0 470 07 0 0 0 0 0 1 1 1 0 280 2E 0 0 1 0 1 1 1 0 0 475 08 0 0 0 0 1 0 0 0 0 285 2F 0 0 1 0 1 1 1 1 0 480 09 0 0 0 0 1 0 0 1 0 290 30 0 0 1 1 0 0 0 0 0 485 0A 0 0 0 0 1 0 1 0 0 295 31 0 0 1 1 0 0 0 1 0 ...

Page 60: ... 0 0 845 51 0 1 0 0 0 0 0 1 0 650 79 0 1 1 1 1 0 0 1 0 850 52 0 1 0 0 0 0 1 0 0 655 7A 0 1 1 1 1 0 1 0 0 855 53 0 1 0 0 0 0 1 1 0 660 7B 0 1 1 1 1 0 1 1 0 860 54 0 1 0 1 0 1 0 0 0 665 7C 0 1 1 1 1 1 0 0 0 865 55 0 1 0 1 0 1 0 1 0 670 7D 0 1 1 1 1 1 0 1 0 870 56 0 1 0 1 0 1 1 0 0 675 7E 0 1 1 1 1 1 1 0 0 875 57 0 1 0 1 0 1 1 1 0 680 7F 0 1 1 1 1 1 1 1 0 880 58 0 1 0 1 1 0 0 0 0 685 80 1 0 0 0 0 0 0...

Page 61: ... 0 1 245 A1 1 0 1 0 0 0 0 1 1 050 C9 1 1 0 0 1 0 0 1 1 250 A2 1 0 1 0 0 0 1 0 1 055 CA 1 1 0 0 1 0 1 0 1 255 A3 1 0 1 0 0 0 1 1 1 060 CB 1 1 0 0 1 0 1 1 1 260 A4 1 0 1 0 0 1 0 0 1 065 CC 1 1 0 0 1 1 0 0 1 265 A5 1 0 1 0 0 1 0 1 1 070 CD 1 1 0 0 1 1 0 1 1 270 A6 1 0 1 0 0 1 1 0 1 075 CE 1 1 0 0 1 1 1 0 1 275 A7 1 0 1 0 0 1 1 1 1 080 CF 1 1 0 0 1 1 1 1 1 280 A8 1 0 1 0 1 0 0 0 1 085 D0 1 1 0 1 0 0 0...

Page 62: ...380 BC 1 0 1 1 1 1 0 0 1 185 E4 1 1 1 0 0 1 0 0 1 385 BD 1 0 1 1 1 1 0 1 1 190 E5 1 1 1 0 0 1 0 1 1 390 BE 1 0 1 1 1 1 1 0 1 195 E6 1 1 1 0 0 1 1 0 1 395 BF 1 0 1 1 1 1 1 1 1 200 E7 1 1 1 0 0 1 1 1 1 400 C0 1 1 0 0 0 0 0 0 1 205 E8 1 1 1 0 1 0 0 0 1 405 C1 1 1 0 0 0 0 0 1 1 210 E9 1 1 1 0 1 0 0 1 1 410 C2 1 1 0 0 0 0 1 0 1 215 EA 1 1 1 0 1 0 1 0 1 415 C3 1 1 0 0 0 0 1 1 1 220 EB 1 1 1 0 1 0 1 1 1 ...

Page 63: ...1 5625 24 1 0 0 1 0 0 1 1625 05 0 0 0 1 0 1 1 5500 25 1 0 0 1 0 1 1 1500 06 0 0 0 1 1 0 1 5375 26 1 0 0 1 1 0 1 1375 07 0 0 0 1 1 1 1 5250 27 1 0 0 1 1 1 1 1250 08 0 0 1 0 0 0 1 5125 28 1 0 1 0 0 0 1 1125 09 0 0 1 0 0 1 1 5000 29 1 0 1 0 0 1 1 1000 0A 0 0 1 0 1 0 1 4875 2A 1 0 1 0 1 0 1 0875 0B 0 0 1 0 1 1 1 4750 2B 1 0 1 0 1 1 1 0750 0C 0 0 1 1 0 0 1 4625 2C 1 0 1 1 0 0 1 0625 0D 0 0 1 1 0 1 1 45...

Page 64: ...ilarly CPUN is not compatible with CPUN 2 2 All CPUs in the system or hard partition must have the same core clock speed or speed range and the same cache size 3 All Intel QPI links must have the same data rate except for Intel QPI links which are disabled or in slow mode Additionally for the Intel Itanium Processor 9300 Series 4 If variable frequency mode VFM is enabled in one CPU it must be enab...

Page 65: ...of its output voltages can be found in the Ararat 170 Watt Voltage Regulator Module Design Guide for the Intel Itanium Processor 9300 Series and the Ararat II Voltage Regulator Module Design Guide for the Intel Itanium Processor 9500 Series When the platform asserts PWRGOOD to the processor the Intel Itanium Processor 9300 Series requires a minimum of 10 ms to complete its internal reset sequence ...

Page 66: ...CUNCORE VID Value VCCCORE VID Value VCCCACHE VID Value VRPWRGD 0us SYSCLK 133MHz 1000mS 10ms Core and Cache Vids may change to vfuse values Core Vid may change in response to power manager 0us 0us 0us 0us 0us 0us 100ms 1uS 1us 0us 0us 0us Uncore Vid may change to on die fuse based value 200 ms 1us pulled to VSS on package for Intel Itanium processor9300 series VCC33_SM for other products 0uS 0us p...

Page 67: ...V PROCTYPE VCCIO VCCA 1 8V VCC 12V 0us VROUTPUT_ENABLE0 RESET_N PWRGOOD VCCCORE 1 4 VCCUNCORE SVID VR_READY 1V Vstrap V hfuse 0us SYSCLK 133MHz 0us VR_PROCTYPE Pulled to 3 3VSM pin on platform Pulled to Ararat s internal 3 3Vrail on Ararat itself 15ms 0us svid changes tovfuse values svid_vcccore may changein response to power manager VCCVUNCOREREADY svids change to hfuse values Vhfuse 0 9V Pwrgdre...

Page 68: ...0 high for Intel Itanium Processor 9300 Series 1 1 μs VCCIO stable before VROUTPUT_ENABLE0 high for Intel Itanium Processor 9500 Series 2 1 ms VROUTPUT_ENABLE0 high to VRPWRGOOD high for Intel Itanium Processor 9300 Series 1 200 ms VROUTPUT_ENABLE0 high to VR_READY for Intel Itanium Processor 9500 Series 2 200 ms VCCUNCORE time to stabilize 1 1 5 ms Delay from VCCUNCORE at programmed VID value to ...

Page 69: ...erent reset cases The LRGSCLSYS pin is sampled only during the PWRGOOD and cold reset period The BOOTMODE 2 0 and FLASHROM_CFG 1 0 pins are sampled during the assertion of all resets except warm logic resets Figure 2 19 Supported Power down Voltage Sequence Timing Requirements R E S E T _ N P W G O O D V R _ O U T P U T _ E N 1 3 3 M H z V ID s V C C C O R E V C C U N C O R E V C C A V C C C A C H...

Page 70: ... pulse width Intel Itanium Processor 9300 Series 10 ms T5 RESET_N asserted pulse width Intel Itanium Processor 9500 Series 15 ms T6 SKTID 2 0 as rst modifier error hold after PWRGOOD deasserted 0 ns T7 SKTID 2 0 as socket id LRGSCLSYS BOOTMODE 2 0 FLASHROM_CFG 1 0 setup to PWRGOOD deasserted 0 ns T8 SKTID 2 0 as socket id LRGSCLSYS hold after RESET_N deasserted 0 ns T9 SKTID 1 0 as rst modifier se...

Page 71: ...anium Platform Debug Port Design Guide DPDG T11 RESET_N deasserted delay to SKTID 2 deasserted as error in 100 ns T12 SKTID 2 as error in asserted pulse width 3 SYSCLK cycles T13 BOOTMODE 2 0 FLASHROM_CFG 1 0 hold after RESET_N deasserted 1 us T14 BOOTMODE 2 FLASHROM_CFG 1 0 setup to RESET_N asserted 0 ns Table 2 40 RESET_N and SKTID Timing Sheet 2 of 2 Parameter Description MIN MAX UNIT ...

Page 72: ...Electrical Specifications 72 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 73: ...I L36 CSI0RNDAT 10 Differential I L38 CSI0RNDAT 11 Differential I N37 CSI0RNDAT 12 Differential I P36 CSI0RNDAT 13 Differential I R37 CSI0RNDAT 14 Differential I T36 CSI0RNDAT 15 Differential I T38 CSI0RNDAT 16 Differential I U36 CSI0RNDAT 17 Differential I V38 CSI0RNDAT 18 Differential I W37 CSI0RNDAT 19 Differential I K37 CSI0RPCLK Differential I A33 CSI0RPDAT 0 Differential I C34 CSI0RPDAT 1 Di...

Page 74: ...35 CSI1RNDAT 4 Differential I Table 3 1 Pin List by Pin Name Sheet 3 of 33 Pin Number Pin Name Signal Buffer Type Direction AP36 CSI1RNDAT 5 Differential I AP37 CSI1RNDAT 6 Differential I AN37 CSI1RNDAT 7 Differential I AM36 CSI1RNDAT 8 Differential I AL37 CSI1RNDAT 9 Differential I AJ37 CSI1RNDAT 10 Differential I AH38 CSI1RNDAT 11 Differential I AG36 CSI1RNDAT 12 Differential I AF38 CSI1RNDAT 13...

Page 75: ... O A21 CSI2RNCLK Differential I J22 CSI2RNDAT 0 Differential I Table 3 1 Pin List by Pin Name Sheet 5 of 33 Pin Number Pin Name Signal Buffer Type Direction H21 CSI2RNDAT 1 Differential I G20 CSI2RNDAT 2 Differential I F21 CSI2RNDAT 3 Differential I E23 CSI2RNDAT 4 Differential I E20 CSI2RNDAT 5 Differential I D21 CSI2RNDAT 6 Differential I C21 CSI2RNDAT 7 Differential I B20 CSI2RNDAT 8 Differenti...

Page 76: ...SI2TPDAT 17 Differential O Table 3 1 Pin List by Pin Name Sheet 7 of 33 Pin Number Pin Name Signal Buffer Type Direction V31 CSI2TPDAT 18 Differential O W31 CSI2TPDAT 19 Differential O AU21 CSI3RNCLK Differential I AN18 CSI3RNDAT 0 Differential I AL17 CSI3RNDAT 1 Differential I AM16 CSI3RNDAT 2 Differential I AN17 CSI3RNDAT 3 Differential I AP19 CSI3RNDAT 4 Differential I AR19 CSI3RNDAT 5 Differen...

Page 77: ...l O AH31 CSI3TPDAT 12 Differential O AG30 CSI3TPDAT 13 Differential O Table 3 1 Pin List by Pin Name Sheet 9 of 33 Pin Number Pin Name Signal Buffer Type Direction AF32 CSI3TPDAT 14 Differential O AE32 CSI3TPDAT 15 Differential O AC32 CSI3TPDAT 16 Differential O AC33 CSI3TPDAT 17 Differential O AB31 CSI3TPDAT 18 Differential O AA33 CSI3TPDAT 19 Differential O H18 CSI4RNCLK Differential I B15 CSI4R...

Page 78: ...CSI5TNDAT 5 Differential O AK18 CSI5TNDAT 6 Differential O Table 3 1 Pin List by Pin Name Sheet 11 of 33 Pin Number Pin Name Signal Buffer Type Direction AG19 CSI5TNDAT 7 Differential O AJ20 CSI5TNDAT 8 Differential O AL21 CSI5TNDAT 9 Differential O AK22 CSI5TPCLK Differential O AH13 CSI5TPDAT 0 Differential O AJ14 CSI5TPDAT 1 Differential O AK15 CSI5TPDAT 2 Differential O AH16 CSI5TPDAT 3 Differe...

Page 79: ...H3 FBD0NBICLKBN0 Differential I AH4 FBD0NBICLKBP0 Differential I Table 3 1 Pin List by Pin Name Sheet 13 of 33 Pin Number Pin Name Signal Buffer Type Direction AL6 FBD0REFSYSCLKN Differential I AL7 FBD0REFSYSCLKP Differential I V4 FBD0SBOAN 0 Differential O W1 FBD0SBOAN 1 Differential O V2 FBD0SBOAN 2 Differential O U1 FBD0SBOAN 3 Differential O T1 FBD0SBOAN 4 Differential O N3 FBD0SBOAN 5 Differe...

Page 80: ...fferential I J9 FBD1NBICP 10 Differential I Table 3 1 Pin List by Pin Name Sheet 15 of 33 Pin Number Pin Name Signal Buffer Type Direction F10 FBD1NBICP 11 Differential I L11 FBD1NBICP 12 Differential I M10 FBD1NBICP 13 Differential I Y9 FBD1NBICP 14 Differential I AB6 FBD1NBIDN 0 Differential I AA6 FBD1NBIDN 1 Differential I W7 FBD1NBIDN 2 Differential I W6 FBD1NBIDN 3 Differential I U5 FBD1NBIDN...

Page 81: ...ential O B4 FBD1SBODN 9 Differential O G6 FBD1SBODN 10 Differential O H2 FBD1SBODP 0 Differential O H3 FBD1SBODP 1 Differential O G5 FBD1SBODP 2 Differential O F3 FBD1SBODP 3 Differential O E2 FBD1SBODP 4 Differential O D4 FBD1SBODP 5 Differential O C6 FBD1SBODP 6 Differential O Table 3 1 Pin List by Pin Name Sheet 17 of 33 Pin Number Pin Name Signal Buffer Type Direction D6 FBD1SBODP 7 Differenti...

Page 82: ...Name Signal Buffer Type Direction C37 RSVD D1 RSVD D38 RSVD F1 RSVD F38 RSVD G1 RSVD G38 RSVD H13 RSVD J20 RSVD L13 RSVD M13 RSVD M20 RSVD M21 RSVD M36 RSVD M4 RSVD P10 RSVD Intel Itanium Processor 9300 Series SVID_CLK2 Intel Itanium Processor 9500 Series P27 RSVD R10 RSVD Intel Itanium Processor 9300 Series SVID_DATIO Intel Itanium Processor 9500 Series R27 RSVD T11 RSVD Intel Itanium Processor 9...

Page 83: ...r Other Table 3 1 Pin List by Pin Name Sheet 21 of 33 Pin Number Pin Name Signal Buffer Type Direction AG35 VCCIO Power Other AH12 VCCIO Power Other AH22 VCCIO Power Other AH27 VCCIO Power Other AK13 VCCIO Power Other AK17 VCCIO Power Other AK23 VCCIO Power Other AL15 VCCIO Power Other AL25 VCCIO Power Other AL35 VCCIO Power Other AM14 VCCIO Power Other AM19 VCCIO Power Other AM29 VCCIO Power Othe...

Page 84: ...er Other E12 VCCIO_FBD Power Other E5 VCCIO_FBD Power Other F8 VCCIO_FBD Power Other Table 3 1 Pin List by Pin Name Sheet 23 of 33 Pin Number Pin Name Signal Buffer Type Direction H7 VCCIO_FBD Power Other J1 VCCIO_FBD Power Other J4 VCCIO_FBD Power Other N4 VCCIO_FBD Power Other T10 VCCIO_FBD Power Other T3 VCCIO_FBD Power Other W5 VCCIO_FBD Power Other Y2 VCCIO_FBD Power Other T12 VFUSERM I AN1 V...

Page 85: ... AG37 VSS Power Other AG5 VSS Power Other Table 3 1 Pin List by Pin Name Sheet 25 of 33 Pin Number Pin Name Signal Buffer Type Direction AG7 VSS Power Other AH10 VSS Power Other AH15 VSS Power Other AH18 VSS Power Other AH20 VSS Power Other AH23 VSS Power Other AH25 VSS Power Other AH26 VSS Power Other AH30 VSS Power Other AH35 VSS Power Other AH5 VSS Power Other AJ12 VSS Power Other AJ13 VSS Powe...

Page 86: ...wer Other AR31 VSS Power Other AR36 VSS Power Other Table 3 1 Pin List by Pin Name Sheet 27 of 33 Pin Number Pin Name Signal Buffer Type Direction AR6 VSS Power Other AT1 VSS Power Other AT12 VSS Power Other AT14 VSS Power Other AT19 VSS Power Other AT24 VSS Power Other AT29 VSS Power Other AT34 VSS Power Other AT4 VSS Power Other AT9 VSS Power Other AU12 VSS Power Other AU17 VSS Power Other AU22 ...

Page 87: ...Other G12 VSS Power Other G14 VSS Power Other Table 3 1 Pin List by Pin Name Sheet 29 of 33 Pin Number Pin Name Signal Buffer Type Direction G17 VSS Power Other G2 VSS Power Other G22 VSS Power Other G27 VSS Power Other G32 VSS Power Other G37 VSS Power Other G7 VSS Power Other H10 VSS Power Other H15 VSS Power Other H20 VSS Power Other H25 VSS Power Other H30 VSS Power Other H35 VSS Power Other H...

Page 88: ... VSS Power Other R4 VSS Power Other Table 3 1 Pin List by Pin Name Sheet 31 of 33 Pin Number Pin Name Signal Buffer Type Direction R6 VSS Power Other T29 VSS Power Other T34 VSS Power Other T4 VSS Power Other T9 VSS Power Other U12 VSS Power Other U2 VSS Power Other U27 VSS Power Other U3 VSS Power Other U32 VSS Power Other U35 VSS Power Other U37 VSS Power Other U7 VSS Power Other V10 VSS Power O...

Page 89: ...CSI2RNDAT 13 Differential I A26 CSI2RPDAT 13 Differential I A27 VCCA Power Other A28 VCCA Power Other A29 VSS Power Other A30 CSI2RPDAT 17 Differential I A31 VCCA Power Other A32 VCCA Power Other A33 CSI0RPDAT 0 Differential I A34 VSS Power Other A35 RSVD A36 VSS Power Other A37 RSVD A38 RSVD AA1 VCCIO_FBD Power Other AA2 FBD0SBOBN 8 Differential O AA3 FBD0SBOBP 8 Differential O AA4 VSS Power Othe...

Page 90: ...PDAT 17 Differential O AC34 CSI1TNDAT 16 Differential O Table 3 2 Pin List by Pin Number Sheet 3 of 32 Pin Number Pin Name Signal Buffer Type Direction AC35 VSS Power Other AC36 VSS Power Other AC37 CSI1RNDAT 17 Differential I AC38 CSI1RPDAT 17 Differential I AD1 FBD0NBIBN 10 Differential I AD2 FBD0NBIBP 10 Differential I AD3 VSS Power Other AD4 FBD0SBOBP 5 Differential O AD5 FBD0SBOBP 7 Different...

Page 91: ...SS Power Other AG3 FBD0NBIBP 7 Differential I AG4 VCCIO_FBD Power Other Table 3 2 Pin List by Pin Number Sheet 5 of 32 Pin Number Pin Name Signal Buffer Type Direction AG5 VSS Power Other AG6 FBD0SBOBP 4 Differential O AG7 VSS Power Other AG8 XDPOCPD 1 _N I O AG9 XDPOCPD 3 _N I O AG10 XDPOCPD 5 _N I O AG11 XDPOCPFRAME_N I O AG12 VSS Power Other AG13 CSI5TNDAT 0 Differential O AG14 VCCIO Power Othe...

Page 92: ...8 VSS Power Other Table 3 2 Pin List by Pin Number Sheet 7 of 32 Pin Number Pin Name Signal Buffer Type Direction AJ9 XDPOCPD 2 _N I O AJ10 XDPOCPD 6 _N I O AJ11 XDPOCP_STRB_IN_N I AJ12 VSS Power Other AJ13 VSS Power Other AJ14 CSI5TPDAT 1 Differential O AJ15 CSI5TNDAT 2 Differential O AJ16 VSS Power Other AJ17 CSI5TPDAT 4 Differential O AJ18 VSS Power Other AJ19 CSI5TPDAT 5 Differential O AJ20 CS...

Page 93: ...Differential I Table 3 2 Pin List by Pin Number Sheet 9 of 32 Pin Number Pin Name Signal Buffer Type Direction AL13 CSI5RPDAT 0 Differential I AL14 VSS Power Other AL15 VCCIO Power Other AL16 CSI3RPDAT 1 Differential I AL17 CSI3RNDAT 1 Differential I AL18 VSS Power Other AL19 VSS Power Other AL20 CSI3TNDAT 0 Differential O AL21 CSI5TNDAT 9 Differential O AL22 CSI5TPDAT 9 Differential O AL23 CSI3TP...

Page 94: ...2 Differential I Table 3 2 Pin List by Pin Number Sheet 11 of 32 Pin Number Pin Name Signal Buffer Type Direction AN15 VSS Power Other AN16 CSI3RPDAT 3 Differential I AN17 CSI3RNDAT 3 Differential I AN18 CSI3RNDAT 0 Differential I AN19 CSI3RPDAT 4 Differential I AN20 VSS Power Other AN21 CSI3TNDAT 3 Differential O AN22 CSI3TPDAT 4 Differential O AN23 CSI3TNDAT 4 Differential O AN24 CSI3TPDAT 5 Dif...

Page 95: ...7 CSI5RPCLK Differential I AR18 CSI3RPDAT 5 Differential I Table 3 2 Pin List by Pin Number Sheet 13 of 32 Pin Number Pin Name Signal Buffer Type Direction AR19 CSI3RNDAT 5 Differential I AR20 CSI3RPDAT 9 Differential I AR21 VSS Power Other AR22 CSI3RPDAT 10 Differential I AR23 VCCIO Power Other AR24 VSS Power Other AR25 CSI3TPDAT 6 Differential O AR26 VSS Power Other AR27 CSI3RPDAT 15 Differentia...

Page 96: ...ifferential I AU22 VSS Power Other Table 3 2 Pin List by Pin Number Sheet 15 of 32 Pin Number Pin Name Signal Buffer Type Direction AU23 CSI3RNDAT 11 Differential I AU24 CSI3RPDAT 13 Differential I AU25 CSI3RNDAT 13 Differential I AU26 CSI3RNDAT 14 Differential I AU27 VSS Power Other AU28 CSI3RNDAT 16 Differential I AU29 CSI3RPDAT 18 Differential I AU30 CSI3RNDAT 18 Differential I AU31 CSI3RPDAT 1...

Page 97: ...ferential I B26 CSI2RPDAT 12 Differential I Table 3 2 Pin List by Pin Number Sheet 17 of 32 Pin Number Pin Name Signal Buffer Type Direction B27 VSS Power Other B28 CSI2RNDAT 16 Differential I B29 CSI2RPDAT 16 Differential I B30 CSI2RNDAT 17 Differential I B31 CSI2RPDAT 18 Differential I B32 VSS Power Other B33 CSI0RNDAT 0 Differential I B34 CSI0RNDAT 2 Differential I B35 CSI0RPDAT 2 Differential ...

Page 98: ... CSI2TPDAT 6 Differential O D30 VSS Power Other Table 3 2 Pin List by Pin Number Sheet 19 of 32 Pin Number Pin Name Signal Buffer Type Direction D31 VSS Power Other D32 VCCIO Power Other D33 VSS Power Other D34 CSI0RNDAT 1 Differential I D35 CSI0RNDAT 3 Differential I D36 CSI0RPDAT 4 Differential I D37 CPU_PRES2_N I O D38 RSVD E1 VSS Power Other E2 FBD1SBODP 4 Differential O E3 FBD1SBOCLKDP0 Diffe...

Page 99: ...TNDAT 7 Differential O F34 VSS Power Other Table 3 2 Pin List by Pin Number Sheet 21 of 32 Pin Number Pin Name Signal Buffer Type Direction F35 VCCIO Power Other F36 CSI0RNDAT 6 Differential I F37 CSI0RPDAT 6 Differential I F38 RSVD G1 RSVD G2 VSS Power Other G3 FBD1SBODN 1 Differential O G4 FBD1SBODN 2 Differential O G5 FBD1SBODP 2 Differential O G6 FBD1SBODN 10 Differential O G7 VSS Power Other ...

Page 100: ...fferential I H38 VR_THERMTRIP_N O Table 3 2 Pin List by Pin Number Sheet 23 of 32 Pin Number Pin Name Signal Buffer Type Direction J1 VCCIO_FBD Power Other J2 FBD0SBOAN 10 Differential O J3 VSS Power Other J4 VCCIO_FBD Power Other J5 VSS Power Other J6 VSS Power Other J7 FBD1NBIDN 11 Differential I J8 VSS Power Other J9 FBD1NBICP 10 Differential I J10 FBD1NBICP 7 Differential I J11 FBD1NBICN 7 Dif...

Page 101: ...fferential O L3 FBD0SBOAN 7 Differential O L4 VSS Power Other Table 3 2 Pin List by Pin Number Sheet 25 of 32 Pin Number Pin Name Signal Buffer Type Direction L5 FBD1NBIDP 7 Differential I L6 FBD1NBIDP 10 Differential I L7 FBD1NBIDN 10 Differential I L8 FBD1NBICLKCN0 Differential I L9 VSS Power Other L10 PROCHOT_N O L11 FBD1NBICP 12 Differential I L12 FBD1NBICN 12 Differential I L13 RSVD L14 VSS P...

Page 102: ...fferential I N8 FBD1NBIDN 8 Differential I Table 3 2 Pin List by Pin Number Sheet 27 of 32 Pin Number Pin Name Signal Buffer Type Direction N9 FBD1NBICP 5 Differential I N10 VSS Power Other N11 TRST_N I N12 TDO O N27 FLASHROM_CLK O N28 FLASHROM_CFG 0 I N29 FLASHROM_CS 3 _N O N30 VSS Power Other N31 CSI2TPDAT 13 Differential O N32 CSI0TNDAT 12 Differential O N33 CSI0TPDAT 12 Differential O N34 CSI0...

Page 103: ...T9 VSS Power Other T10 VCCIO_FBD Power Other Table 3 2 Pin List by Pin Number Sheet 29 of 32 Pin Number Pin Name Signal Buffer Type Direction T11 RSVD1 Intel Itanium Processor 9300 Series SVID_ALERT_N2 Intel Itanium Processor 9500 Series T12 VFUSERM I T27 VCCIO Power Other T28 FLASHROM_DATI I T29 VSS Power Other T30 CSI2TPDAT 14 Differential O T31 CSI2TNDAT 16 Differential O T32 CSI2TPDAT 16 Diffe...

Page 104: ...ther W9 FBD1NBICP 0 Differential I W10 RSVD W11 VSS Power Other W12 RSVD W27 RSVD W28 VSS Power Other W29 TESTHI 2 I Table 3 2 Pin List by Pin Number Sheet 31 of 32 Pin Number Pin Name Signal Buffer Type Direction W30 CSI2TNDAT 19 Differential O W31 CSI2TPDAT 19 Differential O W32 CSI0TNDAT 19 Differential O W33 VSS Power Other W34 CSI0TPDAT 18 Differential O W35 VCCIO Power Other W36 CSI0RPDAT 19...

Page 105: ...able for the Intel Itanium Processor 9300 Series Table 3 3 is a two dimensional table of the Intel Itanium Processor 9300 Series package top side J1 connector Table 3 3 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4 A VID_VCCCORE 1 NO CONNECT VID_VCCCORE 2 NO CONNECT A B VID_VCCCORE 3 VID_VCCCORE 4 B C VID_VCCCORE 5 VID_VCCCORE 6 C D VCCCORE D ...

Page 106: ...CORE AJ AK VCCCORE AK AL VSS AL AM VSS AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU Reserved NO CONNECT Reserved NO CONNECT AU AV VSSCACHESENSE VCCCACHESENSE AV AW VROUTPUT_ENABLE0 CPU_PRESA_N AW AY VR_PROCTYPE_0 VR_PROCTYPE_1 AY Table 3 3 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 1 2 3 4 1 2 3 4 Table 3 4 Top Side J1 Connector Two Dimens...

Page 107: ...UNCORE R T VSS T U VSS U V VSS V W VCCUNCORE W Y VCCUNCORE Y AA VCCUNCORE AA AB VCCUNCORE AB AC VSS AC AD VSS AD AE VSS AE AF VCCUNCORE AF AG VCCUNCORE AG AH VCCUNCORE AH AJ VCCUNCORE AJ AK VSS AK AL VSS AL AM VCCCORE AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT Table 3 4 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 3 1 2 3 4 1 2 3 4 ...

Page 108: ...ONNECT AV AW VROUTPUT_ENABLE0 VCCUNCORE AW AY VR_PROCTYPE_0 VR_PROCTYPE_1 AY Table 3 4 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 3 of 3 1 2 3 4 1 2 3 4 Table 3 5 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4 A VID_VCCUNCORE 1 NO CONNECT VID_VCCUNCORE 3 NO CONNECT A B VID_VCCUNCORE 2 VID_VCCUNCORE 5 B...

Page 109: ... VSS W Y VCCUNCORE Y AA VCCUNCORE AA AB VCCUNCORE AB AC VSS AC AD VSS AD AE VCCUNCORE AE AF VCCUNCORE AF AG VSS AG AH VSS AH AJ VCCCORE AJ AK VCCCORE AK AL VSS AL AM VSS AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU Reserved NO CONNECT Reserved NO CONNECT AU AV VCCCORESENSE VR_THERMTRIP_N AV AW VSSCORESENSE VR_THERMALERT_N AW AY VID_VCCCORE 0 CPU_PRESB_N AY Table 3 5 Top Side J2 Connector ...

Page 110: ... A NO CONNECT NO CONNECT NO CONNECT NO CONNECT A B NO CONNECT VR_READY B C RESERVED RESERVED C D VCCCORE D E VSS E F VSS F G VCCCORE G H VCCCORE H J VCCCORE J K VCCCORE K L VSS L M VSS M N VSS N P VSS P R VCCCORE R T VCCCORE T U VCCCORE U V VCCCORE V W VSS W Y VSS Y AA VSS AA AB VSS AB AC VCCCORE AC AD VCCCORE AD AE VCCCORE AE AF VCCCORE AF AG VSS AG AH VSS AH AJ VSS AJ AK VSS AK 1 2 3 4 ...

Page 111: ...P VCCCORE AP AR VSS AR AT VSS AT AU VSS NO CONNECT VSS NO CONNECT AU AV CPU_PRESB_N VR_THERMTRIP_N AV AW NO CONNECT VR_THERMALERT_N AW AY NO CONNECT NO CONNECT AY Table 3 6 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 2 1 2 3 4 1 2 3 4 Table 3 7 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4 A Reser...

Page 112: ...AD AE VCCCACHE AE AF VCCCACHE AF AG VSS AG AH VSS AH AJ VCCCORE AJ AK VCCCORE AK AL VSS AL AM VSSVSS AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU Reserved NO CONNECT Reserved NO CONNECT AU AV CPU_PRESB_N VSSUNCORESENSE AV AW VID_VCCUNCORE 0 VCCUNCORESENSE AW AY Reserved Reserved AY Table 3 7 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 1 2 3...

Page 113: ...ble 3 8 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 1 of 2 1 2 3 4 A NO CONNECT NO CONNECT NO CONNECT NO CONNECT A B VR_FAN_N NO CONNECT B C NO CONNECT NO CONNECT C D VCCCORE D E VSS E F VSS F G VCCCORE G H VCCCORE H J VCCCORE J K VSS K L VSS L M VCCCORE M N VCCCORE N P VCCCORE P R VCCCORE R T VSS T U VSS U V VSS V W VCCUNCORE W Y VCCUNCORE Y AA VCCUNCORE ...

Page 114: ...E AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU SVID_DATA NO CONNECT SVID_CLK NO CONNECT AU AV VSS VSS AV AW SVID_ALERT_N CPU_PRESB_N AW AY NO CONNECT Reserved AY Table 3 8 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 2 1 2 3 4 1 2 3 4 Table 3 9 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4...

Page 115: ...CUNCORE AB AC VSS AC AD VSS AD AE VCCUNCORE AE AF VCCUNCORE AF AG VSS AG AH VSS AH AJ VCCCORE AJ AK VCCCORE AK AL VSS AL AM VSS AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU VCCIO NO CONNECT Reserved NO CONNECT AU AV Reserved Reserved AV AW Reserved CPU_PRESA_N AW AY Reserved Reserved AY Table 3 9 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 ...

Page 116: ...onnector Table 3 10 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 1 of 2 1 2 3 4 A NO CONNECT NO CONNECT NO CONNECT NO CONNECT A B RESERVED RESERVED B C RESERVED RESERVED C D VCCCORE D E VSS E F VSS F G VCCCORE G H VCCCORE H J VCCCORE J K VCCCORE K L VSS L M VSS M N VSS N P VSS P R VCCCORE R T VCCCORE T U VCCCORE U V VCCCORE V W VSS W Y VSS Y AA VSS AA AB VS...

Page 117: ... VCCCORE AL AM VCCCORE AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU VCCIO NO CONNECT VSS NO CONNECT AU AV Reserved RESERVED AV AW CPU_PRESA_N NO CONNECT AW AY NO CONNECT NO CONNECT AY Table 3 10 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 2 1 2 3 4 1 2 3 4 ...

Page 118: ...Pin Listing 118 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 119: ...as the mating surface for the processor component thermal solutions such as a heatsink The bottom side of the package has 1248 lands a 38 x 38 mm pad array which interfaces with the LGA1248 socket Figure 4 1 shows a sketch of the processor package components and how they are assembled together The package components shown in Figure 4 1 include the following 1 Integrated Heat Spreader IHS 2 Process...

Page 120: ... the Intel Itanium Processor 9500 Series processor are shown in Figure 4 6 Figure 4 7 Figure 4 8 and Figure 4 9 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions will include 1 Package reference with tolerances total height length width and so on 2 IHS parallelism and tilt 3 Land dimensions 4 Top side and back side component keepout dimension...

Page 121: ...el Itanium Processor 9300 Series and 9500 Series Datasheet 121 Mechanical Specifications 4 2 Intel Itanium Processor 9300 Series Figure 4 2 Intel Itanium Processor 9300 Series Package Drawing Sheet 1 of 4 ...

Page 122: ...Mechanical Specifications 122 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Figure 4 3 Intel Itanium Processor 9300 Series Processor Package Drawing Sheet 2 of 4 ...

Page 123: ...Intel Itanium Processor 9300 Series and 9500 Series Datasheet 123 Mechanical Specifications Figure 4 4 Intel Itanium Processor 9300 Series Package Drawing Sheet 3 of 4 ...

Page 124: ...Mechanical Specifications 124 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Figure 4 5 Intel Itanium Processor 9300 Series Package Drawing Sheet 4 of 4 ...

Page 125: ...Intel Itanium Processor 9300 Series and 9500 Series Datasheet 125 Mechanical Specifications Figure 4 6 Intel Itanium Processor 9500 Series Package Drawing Sheet 1 of 4 ...

Page 126: ...Mechanical Specifications 126 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Figure 4 7 Intel Itanium Processor 9500 Series Package Drawing Sheet 2 of 4 ...

Page 127: ...Intel Itanium Processor 9300 Series and 9500 Series Datasheet 127 Mechanical Specifications Figure 4 8 Intel Itanium Processor 9500 Series Package Drawing Sheet 3 of 4 ...

Page 128: ...Mechanical Specifications 128 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Figure 4 9 Intel Itanium Processor 9500 Series Package Drawing Sheet 4 of 4 ...

Page 129: ...package handling loads may be experienced during heatsink removal Note 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4...

Page 130: ...ustrated in Figure 4 10 Notes 1 VID Visual Identification Is a unique number which can be used for the purpose of tracking the processor It is used by Intel to retrieve processor related information 2 FPO Finish Process Order Is a unique number It can be used for tracking purposes It is used by Intel to retrieve processor and shipping order information Table 4 3 Processor Package Insertion Specifi...

Page 131: ...Intel Itanium Processor 9300 Series and 9500 Series Datasheet 131 Mechanical Specifications Figure 4 10 Processor Marking Zones A B C Top Side G F E H Bottom Side ...

Page 132: ...Mechanical Specifications 132 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 133: ...ing in higher performance For the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series base frequency is based on an activity factor determined by the highest known activity factor in benchmark suites Boost frequency is available when the processor is not power limited The Intel Itanium Processor 9500 Series enables Intel Turbo Boost Technology featuring sustained boost Proc...

Page 134: ...its and set QR_CSR_IPF_THERM_STATUS valid 1 b0 5 1 1 1 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9300 Series Table 5 1 shows the processor thermal sensor accuracy with respect to the DT readout for the an Intel Itanium Processor 9300 Series The margin of error is relative to PROCHOT and represents the typical 3 sigma range This data is for a large sample of parts It shou...

Page 135: ... is operating at boost frequency then the thermal management system will instruct the processor to go to base voltage and frequency After a delay if the processor temperature is below the TPROCHOT threshold normal operation will resume including the Intel Itanium Processor 9300 Series being allowed to operate at boost frequency if appropriate If T TPROCHOT the Intel Itanium Processor 9500 Series t...

Page 136: ...r and the frequency and voltage control resides completely on the processor In order to reduce the processor power while throttling some execution units on the processor are shut down limiting the processor to executing only one instruction per cycle When the PROCHOT threshold is crossed and the processor enters low power mode a CMCI is sent to the OS and to the System Abstraction Layer SAL This i...

Page 137: ...ed life Note that no internal response is generated by the processor at TCONTROL Customers can utilize THERMALERT_N as an interrupt to program an alternative temperature monitoring threshold value to provide margin in their cooling solution design See Intel Itanium Processor 9300 Series Thermal Mechanical Design Guide for additional guidance on implementing a compliant processor thermal solution 5...

Page 138: ...conditions The thermal environment is outside of the limits defined for full performance operation The processor power consumption is unbalanced due to very high activity factors in some cores coupled with very low activity factors in others 5 1 8 FORCEPR_N Signal Pin FORCEPR_N is an input pin that will force the processor into one of two modes The default mode is the same state as PROCHOT_N The p...

Page 139: ...roxy for power dissipation due to the variation in work load imbalances between cores TDPmax is 185 W or 155 W or 130 W depending on the SKU The combined max short term 250 ms power for the Ararat supplies VCC_CORE VCC_UNCORE and VCC_CACHE is limited to 230 W and the total of all supplies is limited to 250 W for the 185 W SKUs TCASE cannot be used as proxy for power dissipation due to the variatio...

Page 140: ...s used by customers Provided as general guidance only Intel board products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40 C to 70 C and Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Table specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition b...

Page 141: ...ffect the long term reliability of the processor 4 Device storage temperature qualification methods follow JESD22 A119 low temp and JESD22 A103 high temp standards Table 5 5 Storage Condition Ratings Symbol Parameter Min Max Notes Tabs storage The minimum maximum device storage temperature beyond which damage latent or otherwise may occur when subjected to for any length of time 55 C 125 C 1 2 3 4...

Page 142: ...Thermal Specifications 142 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 143: ...essor s control status registers CSRs This chapter is devoted to the PIROM field definitions of the memory component For details of SMBus transactions used to access processor Control and Status Registers CSRs refer to the RS Intel Itanium 9300 Processor External Design Specification or the RS Intel Itanium Processor 9500 Series External Design Specification The PIROM consists of the following sec...

Page 144: ...0 if not present 7 07h Package Data Address Hex Byte pointer Pointer to the section of PIROM containing Processor Package Data 0x4F 0x00 if not present 8 08h Part Number Data Address Hex Byte pointer Pointer to the section of PIROM containing Processor Part Number Data 0x56 0x00 if not present 9 09h Thermal Reference Data Address Hex Byte pointer Pointer to the section of PIROM containing Processo...

Page 145: ...tel Itanium Processor 9300 Series Core Count 0x26 RESERVED 0x27 Intel Itanium Processor 9500 Series 4 bcd digits Intel Itanium Processor 9300 Series 2 bcd digits 0x26 2 Hex digits 0x27 Intel Itanium Processor 9500 Series Maximum Specified operating frequency of this part in MHz Intel Itanium Processor 9300 Series Number of available cores in the processor 0x26 Intel Itanium Processor 9500 Series 1...

Page 146: ...digits Minimum Memory Transfer rate for this part in MT s 800 MT s 000800 GT s 3Ch 00 3Dh 08 3Eh 00 61 3Dh 62 3Eh 63 3Fh Uncore Voltage ID 4 bcd digits Voltage in four 4 bit Hex digits in mV 1200 mV 1200 3Fh 00 40h 12 64 40h 65 41h Uncore Voltage Tolerance High 2 Hex digits Edge finger tolerance in mV 20 mV 0x14 66 42h Uncore Voltage Tolerance Low 2 Hex digits Edge finger tolerance in mV 20 mV 0x1...

Page 147: ...0 4Dh 0x00 77 4Dh 78 4Eh Checksum Hex Add up by byte and take 2 s complement Package 79 4Fh Package Revision Five 8 bit ASCII Hex characters Package Revision Tracking Number Revision 0INT3 4Fh 0x30 50h 0x49 51h 0x4E 52h 0x54 53h 0x33 80 50h 81 51h 82 52h 83 53h 84 54h Substrate Revision Software ID Intel Itanium Processor 9300 Series RESERVED Intel Itanium Processor 9500 Series Hex 2 bit substrate...

Page 148: ... Itanium Processor 9500 Series 104 68h 105 69h RESERVED Hex Reserved for future use 69h 0x00 106 6Ah Checksum Hex Add up by byte and take 2 s complement Thermal Reference 107 6Bh THERMALERT_N hot assertion 2 Hex digits Recommended THERMALERT_N assertion threshold value 10C below PROCHOT_N 0x0A 108 6Ch THERMALERT_N hot deassertion hysteresis 2 Hex digits Recommended THERMALERT_N deassertion thresho...

Page 149: ...re use Intel Itanium Processor 9500 Series Flag 0x4387FBFF 72h 0xFF 73h 0xFB 74h 0x87 75h 0x43 Intel Itanium Processor 9300 Series 72h 0x00 73h 0x00 74h 0x00 75h 0x00 Intel Itanium Processor 9500 Series 115 73h 116 74h 117 75h 118 76h RESERVED Hex Reserved for future use 76h 0x00 77h 0x00 119 77h 120 78h Package Feature Flags Hex Bit 7 4 reserved Bit 3 THERMALERT_N threshold values present Bit 2 S...

Page 150: ...he tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed the PIROM MSB 0 or the Scratch EEPROM MSB 1 6 3 Memory Component Addressing The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series PIR_A 1 0 pins are used as the memory address selection signal...

Page 151: ...ssor 9500 Series Package VCC33_SM SM_WP THERMALERT_N VCC A0 A2 SCL SDA SPDCLK SPDDAT BOOTMODE 1 SKTID 0 SKTID 2 SMBCLK SMBDAT AT 34C02C U2 EEPRO M SPDCLK SPDDAT BOOTMODE 1 SKTID 0 SKTID 2 SMBCLK SMBDAT VSS To From Platform WP THERMALERT_N A1 SKTID 1 SKTID 1 BOOTMODE 0 BOOTMODE 0 To From Platform 0 1uF C579 PIR_A1 PIR_A0 PIR_SDA PIR_SCL Intel Itanium processor D ie U 1 ...

Page 152: ...d voltage regulator field VCCA and VCCIO voltage specs The sample or production field is a two bit LSB aligned value 0x00 indicates unlocked PIROM section This is the case in most samples 0x01 indicates a locked PIROM section Some samples and all production parts will be locked The required voltage regulator field for the Intel Itanium Processor 9300 Series is 0x00 The required voltage regulator f...

Page 153: ...des minimum operating link transfer rate for the Intel QuickPath Interconnect Systems may need to read this offset to decide if all installed processors support the same link transfer rate This does not relate to the link power up transfer rate of 1 4th Ref Clk This value is represented by 6 bcd digits 6 4 4 3 Intel QuickPath Interconnect Version Number Offset 34h 37h provides the Intel QuickPath ...

Page 154: ...stored as 3Fh 00h 40h 12h 6 4 4 8 Uncore Voltage Tolerance Offset 41h and 42h contain the Uncore voltage tolerances high and low respectively These use a decimal to Hexadecimal conversion Example 20 mV tolerance would be saved as 14h 6 4 5 Cache Data This section contains cache related data 6 4 5 1 L3 Cache Size Offset 46h 47h is the L3 cache size field The field reflects the size of the level thr...

Page 155: ...cting the Intel part number for the processor This information is typically marked on the outside of the processor If the part number is less than 7 characters a leading space is inserted into the value Example A processor with a part number of 80546KF will have data as 46h 4bh 36h 34h 35h 30h 38h starting at offset 56h 6 4 7 2 Processor Electronic Signature Offset 5Dh 64h contains a unique 64 bit...

Page 156: ...thout powering on the processor 6 4 9 1 Processor Core Feature Flags For the Intel Itanium Processor 9300 Series offset 72h 75h contains a copy of results in EDX 31 0 from Function 1 of the CPUID instruction These details provide instruction and feature support by product family These fields are RESERVED for the Intel Itanium Processor 9500 Series processor 6 4 9 2 Package Feature Flags Offset 78h...

Page 157: ...section Checksums are automatically calculated and programmed The first step in calculating the checksum is to add each byte from the field to the next subsequent byte The second step is to take the 2 s complement of the first step This value is the checksum Example For a byte string of AA445Ch the resulting checksum will be B6h AA 10101010 44 01000100 5C 0101100 First step add the bytes AA 44 5C ...

Page 158: ...System Management Bus Interface 158 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 159: ... the bottom of the package are part of a daisy chain that indicates to the platform that the processor and Ararat are properly installed into the socket Motherboard routing guidelines for these pins are documented in the Intel Itanium 9300 Series Processor and Intel Itanium Processor 9500 Series Platform Design Guide CSI 5 0 R P N CLK I The receive clock signals are inputs to the Intel Itanium Pro...

Page 160: ..._N O Side band signaling for system management Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide for pin considerations ERROR 1 _N O Side band signaling for system management Assertion on this pin indicates that an error reset response is required from the platform Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Proces...

Page 161: ... Series and Intel Itanium 9500 Series FBD0NBI A B P N 12 0 I These differential pair data signals generated from the branch zero channel A and B of FB DIMMs are input to the processor Example FBD0NBIAP 0 represent FB DIMM branch 0 northbound data input lane 0 signal of channel A and positive bit of the differential pair FBD0NBI A B P N 13 I These signals are spare lanes and are intended for Reliab...

Page 162: ...mple FBD1SBOCP 0 represents FB DIMM branch 1 southbound data output lane 0 signal of channel C and positive bit of the differential pair FBD1SBO C D P N 10 O These signals are spare lanes and are intended for Reliability Availability and Serviceability RAS coverage on the Intel Itanium 9500 Processor Series These signals are not used by Intel Itanium 9300 Processor Series FLASHROM_CFG 2 0 I These ...

Page 163: ...300 Processor Series and VCC33_SM internally to indicate the Intel Itanium 9500 Processor Series This pin does not require a platform pull up or pull down PWRGOOD I The processor requires this signal to be a clean indication that all the processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current wi...

Page 164: ...d until VCCA VCCIO VCC33_SM and VCC 12 V Ararat are stabilized SYSUTST_REFCLK SYSUTST_REFCLK_N I These serve as reference clocks for the processor socket logic analyzer interposer device during debug It is not used by the processor and is not connected internally to the die Electrical specifications on these clocks are identical to SYSCLK SYSCLK_N TCK I Test Clock TCK provides the clock input for ...

Page 165: ...CORE_VID VCCUNCORE_VID and VID_VCCCACHE Voltage ID pads are used to support automatic selection of VCCCORE VCCUNCORE and VCCCACHE by the Intel Itanium 9300 Processor Series The VCCCORE VCCUNCORE and VCCCACHE Voltage Regulator Ararat outputs must be disabled prior to these pins becoming invalid The VID pins are needed to support processor voltage specification variations The VCCCORE VCCUNCORE and V...

Page 166: ...active and the voltage regulator s startup sequence begins When this signal is pulled down the Ararat Voltage regulator should shut down VCCCORE VCCUNCORE and VCCCACHE Intel Itanium 9300 Processor Series only See Ararat 170W Voltage Regulator Module Design Guide and or Ararat II Voltage Regulator Module Design Guide for platform requirements on driving this signal VRPWRGD Ararat VR_READY Ararat II...

Page 167: ... 9500 Series Absolute Maximum Ratings 39 2 6 Processor DC Specifications 39 2 6 1 Flexible Motherboard Guidelines for the Intel Itanium Processor 9300 Series 40 2 6 2 Flexible Motherboard Guidelines for the Intel Itanium Processor 9500 Series 43 2 6 3 Intel Itanium Processor 9300 Series Uncore Core and Cache Tolerances 44 2 6 4 Intel Itanium Processor 9500 Series Uncore and Core Tolerances 49 2 6 ...

Page 168: ...1 Thermal Features 133 5 1 1 Digital Thermometer 134 5 1 2 Thermal Management 135 5 1 3 Thermal Alert 136 5 1 4 TCONTROL 137 5 1 5 Thermal Warning 137 5 1 6 Thermal Trip 137 5 1 7 PROCHOT 138 5 1 8 FORCEPR_N Signal Pin 138 5 1 9 Ararat Voltage Regulator Thermal Signals 138 5 2 Package Thermal Specifications and Considerations 139 5 3 Storage Conditions Specifications 140 6 System Management Bus In...

Page 169: ...int Representation 57 2 17 Supported Power up Voltage Sequence Timing Requirements for the Intel Itanium Processor 9300 Series 66 2 18 Supported Power up Sequence Timing Requirements for Intel Itanium Processor 9500 Series 67 2 19 Supported Power down Voltage Sequence Timing Requirements 69 2 20 RESET_N and SKITID Timing for Warm and Cold Resets 70 4 1 Processor Package Assembly Sketch 119 4 2 Int...

Page 170: ...170 Intel Itanium Processor 9300 Series and 9500 Series Datasheet ...

Page 171: ...tions for the Intel Itanium Processor 9300 Series 41 2 17 FMB 155W 185W Current Specifications for the Intel Itanium Processor 9300 Series 42 2 18 FMB Voltage Specifications for the Intel Itanium Processor 9500 Series 43 2 19 FMB 170W and 130W Current Specifications for the Intel Itanium Processor 9500 Series 44 2 20 VCCUNCORE Static and Transient Tolerance for Intel Itanium Processor 9300 Series ...

Page 172: ...ries 110 3 7 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9300 Series 111 3 8 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series 113 3 9 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9300 Series 114 3 10 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series 116 4 1 Processor Loading Specifications 1...

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