Intel 82547EI, Design Manual

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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Contents
1.0 Introduction......................................................................................................................... 1
1.1 Scope............................................................................................................................................ 1
1.2 Reference Documents .................................................................................................................. 2
1.3 Product Codes .............................................................................................................................. 2
2.0 System Data Port Interfaces .............................................................................................. 3
2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device ................................................. 3
2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller ............................................... 4
2.2.1
Generation/Distribution of Reference Voltages ............................................................... 4
2.2.2 CSA Port Resistive Compensation .................................................................................. 5
3.0 Ethernet Component Design Guidelines ............................................................................ 7
3.1 General Design Considerations for Ethernet Controllers.............................................................. 7
3.1.1
Crystal Selection Parameters .......................................................................................... 7
3.1.2 Reference Crystal .......................................................................................................... 10
3.1.3 Reference Crystal Selection .......................................................................................... 11
3.1.4 Circuit Board .................................................................................................................. 11
3.1.5 Temperature Changes................................................................................................... 11
3.1.6 Integrated Magnetics Module ........................................................................................ 12
3.2 Designing with the 82562EZ(EX) Platform LAN Connect Device............................................... 12
3.2.1
82562EZ/EX PLC Device LAN Disable Guidelines ....................................................... 12
3.2.2 Serial EEPROM for 82562EZ(EX) Implementations...................................................... 13
3.2.3 Magnetics Modules for 82562EZ(EX) PLC Device........................................................ 14
3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations .............................................. 14
3.2.5 82562EZ(EX) Device Test Capability ............................................................................14
3.3 Designing with the 82547GI(EI) Gigabit Ethernet Controller ...................................................... 14
3.3.1
82547GI(EI) Ethernet Controller LAN Disable Guidelines ............................................. 14
3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations ....................................... 15
3.3.3 EEPROM Map Information ............................................................................................ 17
3.3.4 Magnetics Modules for 82547GI(EI) Controller Applications ......................................... 17
3.3.5 Power Supplies for the 82547GI(EI) Device .................................................................. 17
3.3.6 82547GI(EI) Controller Power Supply Filtering.............................................................. 18
3.3.7 82547GI(EI) Controller Power Management and Wake Up........................................... 18
3.3.8 82547GI(EI) Device Test Capability .............................................................................. 19
4.0 Ethernet Component Layout Guidelines .......................................................................... 21
4.1 General Layout Considerations for Ethernet Controllers ............................................................ 21
4.1.1
Guidelines for Component Placement ........................................................................... 21
4.1.2 Crystals.......................................................................................................................... 22
4.1.3 Board Stack Up Recommendations............................................................................... 22
4.1.4 Differential Pair Trace Routing....................................................................................... 23
4.1.5 Signal Trace Geometry.................................................................................................. 24
4.1.6 Trace Length and Symmetry .........................................................................................24
4.1.7 Impedance Discontinuities............................................................................................. 25
4.1.8 Reducing Circuit Inductance.......................................................................................... 25
4.1.9 Signal Isolation .............................................................................................................. 25
4.1.10 Power and Ground Planes............................................................................................. 25