Intel 82547EI, Design Manual

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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
15
For best results, do not attempt to use the LAN_POWER_GOOD signal for a LAN disable input.
This pin is intended to operate as a power-on reset connected to a power monitor circuit.
The input of FLSH_SO (ball P9) is the LAN_DISABLE signal. It is sampled on the rising edge of
LAN_PWR_GOOD and/or RST#. The signal must be held valid for 80 ns after either rising edge.
If sampled high, the LAN functions normally. If sampled low, then the following occurs:
1. The LAN is disabled.
2. The PHY is powered down.
3. Most MAC clock domains are gated.
4. Most functional blocks are held in reset.
5. The device is in a low power state – equivalent to D3 w/ no wake or manageability.
Note: To use this configuration for the 82562EZ(EX) Platform LAN Connect device, be sure the AND
gate U1 is populated. Depopulate the 0
Ω
resistor R2.
Figure 6. 82547GI(EI) LAN Disable Circuitry
3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations
The 82547GI(EI) Gigabit Ethernet Controller can use either a Microwire* or an SPI* serial
EEPROM. The EEPROM mode is selected on the EEMODE input (ball C4). A pull-up resistor to
Vcc denotes SPI*. A pull-down resistor to ground denotes Microwire. Several words of the
EEPROM are accessed automatically by the device after reset to provide pre-boot configuration
data before it is accessed by host software. The remainder of the EEPROM space is available to
software for storing the MAC address, serial numbers, and additional information.
IO
Control
Hub 5
Super IO
Chip
82547GI(EI)
RST#
RST# (B9)
RSM_RST#
R1
10 K
R2
0 Ohm
Pop = Y
LAN_PWR_GOOD
(A9)
82562EZ(EX) Disable Circuit
U1
FLSH_SO
(P9)
Pop = Y means populate this option