Intel 82547EI, Design Manual

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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
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3.3.8 82547GI(EI) Device Test Capability
The 82547GI(EI) Gigabit Ethernet Controller contains a test access port conforming to the IEEE
1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls
to pads accessible by your test equipment. Be sure to connect the TRST# input to ground through a
pull-down resistor (approximately 1k value) so that the test capability cannot be invoked by
mistake.
A BSDL (Boundary Scan Definition Language) file describing the 82547GI(EI) device is available
for use in your test environment.
The controller also contains an XOR test tree mechanism for simple board tests. Details of XOR
tree operation may be obtained through your Intel representative.