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A-19

INSTRUCTION SET REFERENCE

EST

EXTENDED STORE WORD. Stores the
value of the source (leftmost) word operand
into the destination (rightmost) operand.

This instruction allows you to move data from
the lower register file to anywhere in the 16-
Mbyte address space.

ext. indirect: (DEST)

←

(SRC)

ext indexed: (DEST)

←

(SRC) + 24-bit disp

SRC, DEST

EST

wreg, [treg]

ext. indirect: (00011100) (treg) (wreg)

ext. indexed: (00011101) (treg) (disp-low)

(disp-high) (disp-ext) (wreg)

NOTE:

For 20-bit addresses, the offset
must be in the range of +524287
to –524288.

PSW Flag Settings

—

ESTB

EXTENDED STORE BYTE. Stores the value
of the source (leftmost) byte operand into
the destination (rightmost) operand.

This instruction allows you to move data from
the lower register file to anywhere in the 16-
Mbyte address space.

ext. indirect: (DEST)

←

(SRC)

ext indexed: (DEST)

←

(SRC) + 24-bit disp

SRC, DEST

ESTB breg,

[treg]

ext. indirect: (00011110) (treg) (breg)

ext. indexed: (00011111) (treg) (disp-low)

(disp-high) (disp-ext) (breg)

NOTE:

For 20-bit addresses, the offset
must be in the range of +524287
to –524288.

PSW Flag Settings

—

EXT

SIGN-EXTEND INTEGER INTO LONG-
INTEGER. Sign-extends the low-order word
of the operand throughout the high-order
word of the operand.

if DEST.15 = 1 then

(high word DEST)

←

0FFFFH

else

(high word DEST)

←

end_if

EXT lreg

(00000110) (lreg)

PSW Flag Settings

✓

—

Table A-6. Instruction Set (Continued)

Mnemonic

Operation

Instruction Format

Summary of Contents for 80C196NU

Page 1: ...8XC196NP 80C196NU Microcontroller User s Manual...

Page 2: ...8XC196NP 80C196NU Microcontroller User s Manual August 1995 Order Number 272479 002...

Page 3: ...ns the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your produc...

Page 4: ...OVERVIEW 2 1 TYPICAL APPLICATIONS 2 1 2 2 DEVICE FEATURES 2 2 2 3 BLOCK DIAGRAM 2 2 2 3 1 CPU Control 2 3 2 3 2 Register File 2 3 2 3 3 Register Arithmetic logic Unit RALU 2 4 2 3 3 1 Code Execution 2...

Page 5: ...Floating Point Operations 4 5 4 1 12 Extended Instructions 4 5 4 2 ADDRESSING MODES 4 6 4 2 1 Direct Addressing 4 7 4 2 2 Immediate Addressing 4 7 4 2 3 Indirect Addressing 4 7 4 2 3 1 Extended Indire...

Page 6: ...n Registers SFRs 5 12 5 3 WINDOWING 5 13 5 3 1 Selecting a Window 5 14 5 3 2 Addressing a Location Through a Window 5 16 5 3 2 1 32 byte Windowing Example 5 18 5 3 2 2 64 byte Windowing Example 5 18 5...

Page 7: ...r Multiplexed Interrupts 6 11 6 5 2 Modifying Interrupt Priorities 6 13 6 5 3 Determining the Source of an Interrupt 6 15 6 6 INITIALIZING THE PTS CONTROL BLOCKS 6 17 6 6 1 Specifying the PTS Count 6...

Page 8: ...1 Synchronous Mode Mode 0 8 4 8 3 2 Asynchronous Modes Modes 1 2 and 3 8 5 8 3 2 1 Mode 1 8 6 8 3 2 2 Mode 2 8 7 8 3 2 3 Mode 3 8 7 8 3 2 4 Mode 2 and 3 Timings 8 7 8 3 2 5 Multiprocessor Communicati...

Page 9: ...0 5 3 Programming the Capture Compare Channels 10 18 10 6 ENABLING THE EPA INTERRUPTS 10 22 10 7 DETERMINING EVENT STATUS 10 22 10 7 1 Using Software to Service the Multiplexed Overrun Interrupts 10 2...

Page 10: ...Ranges 13 7 13 3 2 Controlling Wait States Bus Width and Bus Multiplexing 13 10 13 3 3 Chip select Unit Initial Conditions 13 11 13 3 4 Initializing the Chip select Registers 13 11 13 3 5 Example of...

Page 11: ...USER S MANUAL x APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B 1 FUNCTIONAL GROUPINGS OF SIGNALS B 1 B 2 SIGNAL DESCRIPTIONS B 6 B 3 DEFAULT CONDITIONS B 13 APPENDIX C REGISTER...

Page 12: ...nd Standard Interrupts 6 2 6 2 Standard Interrupt Response Time 6 9 6 3 PTS Interrupt Response Time 6 9 6 4 PTS Select PTSSEL Register 6 11 6 5 Interrupt Mask INT_MASK Register 6 12 6 6 Interrupt Mask...

Page 13: ...ntrol EPAx_CON Registers 10 19 10 11 EPA Interrupt Mask EPA_MASK Register 10 22 10 12 EPA Interrupt Pending EPA_PEND Register 10 23 11 1 Minimum Hardware Connections 11 3 11 2 Power and Return Connect...

Page 14: ...tiplexed Mode 8XC196NP 13 29 13 15 READY Timing Diagram Demultiplexed Mode 80C196NU 13 30 13 16 HOLD HLDA Timing 13 31 13 17 Write control Signal Waveforms 13 34 13 18 Decoding WRL and WRH 13 35 13 19...

Page 15: ...6NP 5 6 5 5 Peripheral SFRs 5 8 5 6 Register File Memory Addresses 5 11 5 7 CPU SFRs 5 12 5 8 Selecting a Window of Peripheral SFRs 5 15 5 9 Selecting a Window of the Upper Register File 5 15 5 10 Win...

Page 16: ...2 I O Port Configuration Guide 11 2 12 1 Operating Mode Control Signals 12 1 12 2 Operating Mode Control and Status Registers 12 2 12 3 80C196NU Clock Modes 12 13 13 1 Example of Internal and External...

Page 17: ...t Values C 5 C 4 Effect of SME and FME Bit Combinations C 7 C 5 ADDRCOMx Addresses and Reset Values C 8 C 6 ADDRMSKx Addresses and Reset Values C 9 C 7 BUSCONx Addresses and Reset Values C 10 C 8 EPAx...

Page 18: ...1 Guide to This Manual...

Page 19: ......

Page 20: ...he MCS 96 microcontroller family to in corporate enhanced 16 bit multiplication instructions for performing multiply accumulate oper ations and a dedicated 32 bit accumulator register for storing the...

Page 21: ...y signals and de scribes the registers that control the external memory interface It discusses the chip selects mul tiplexed and demultiplexed bus modes bus width and memory configurations the bus hol...

Page 22: ...compilers require a zero plus an x preceding a hexadecimal value so FFFFFFH must be written as 0xFFFFFF Consult the manual for your assembler or compiler to determine its specific requirements assert...

Page 23: ...ber For example WSR 7 is bit 7 of the window selection register In some discussions bit names are used register names Register mnemonics are shown in upper case For example TIMER2 is the timer 2 regis...

Page 24: ...es that bits 11 8 are unknown 10XXB binary indicates that the two least significant bits are unknown 1 3 RELATED DOCUMENTS The tables in this section list additional documents that you may find useful...

Page 25: ...sign techniques 270648 Embedded Microcontrollers Datasheets and architecture descriptions for Intel s three industry standard micro controllers the MCS 48 MCS 51 and MCS 96 microcontrollers 270646 Per...

Page 26: ...er 270946 8XC196NP Commercial CHMOS 16 Bit Microcontroller 272459 8XC196NT CHMOS Microcontroller with 1 Mbyte Linear Address Space 272267 80C196NU Commercial CHMOS 16 Bit Microcontroller 272644 Includ...

Page 27: ...dial the telephone number and respond to the system prompts After you select a doc ument the system sends a copy to your fax machine Each document is assigned an order number and is listed in a subjec...

Page 28: ...1793 496340 Europe The toll free BBS available in the U S and Canada offers lists of documents available from FaxBack a master list of files available from the application BBS and a BBS user s guide...

Page 29: ...ApBUILDER files and hypertext manuals and datasheets are available first from the BBS To access the files complete these steps 1 Type F from the BBS Main menu The BBS displays the Intel Apps Files me...

Page 30: ...questions to us Please include your voice telephone number and indicate whether you prefer a response by phone or by fax Outside the U S and Canada please contact your local distributor 1 800 628 868...

Page 31: ......

Page 32: ...2 Architectural Overview...

Page 33: ......

Page 34: ...to handle larger more complex programs and to access more external memory at a faster rate than could earlier MCS 96 microcontrollers The 8XC196NP and 80C196NU are pin compatible and have identical c...

Page 35: ...to the instruction register in the RALU Figure 2 1 8XC196NP and 80C196NU Block Diagram Table 2 1 Features of the 8XC196NP and 80C196NU Device Pins ROM Note 1 Register RAM Note 2 I O Pins Note 3 EPA P...

Page 36: ...n the lower register file the lowest 24 bytes are allocated to the CPU s special function registers SFRs and the stack pointer while the remainder is available as general purpose register RAM The uppe...

Page 37: ...ption of the PSW All registers except the 3 bit bit select register and the 6 bit loop counter are either 16 or 17 bits 16 bits plus a sign extension Some of these registers can reduce the ALU s workl...

Page 38: ...s with the upper register file through the memory control ler except when windowing is used see Chapter 5 Memory Partitions The memory controller contains the prefetch queue the slave program counter...

Page 39: ...includes a 16 bit adder a 3 to 1 multiplexer a 32 bit accumulator register and a control register The multiply accumu late function is enabled by any 16 bit multiplication instruction with a destinat...

Page 40: ...PLLEN1 and PLLEN2 pins this frequency is routed either through the phase locked loop and multiplier or directly to the divide by two cir cuit The multiplier circuitry can double or quadruple the input...

Page 41: ...signal on the CLKOUT pin Because of the complex logic in the clock circuitry the signal on the CLKOUT pin is a de layed version of the internal CLKOUT signal This delay varies with temperature and vol...

Page 42: ...terms of clock periods t For the 80C196NU Table 2 3 details the relationships between the input frequency FXTAL1 the configuration of PLLEN1 and PLLEN2 the operating frequency f the clock period t an...

Page 43: ...to the Divide by two Circuit t Clock Period State Time 50 MHz 00 1 50 MHz 20 ns 40 ns 25 MHz 00 1 25 MHz 40 ns 80 ns 10 2 50 MHz 20 ns 40 ns 12 5 MHz 00 1 12 5 MHz 80 ns 160 ns 10 2 25 MHz 40 ns 80 n...

Page 44: ...the three on chip pulse width modulators The EPORT provides address lines A19 16 to support extended addressing See Chapter 7 I O Ports for more information 2 5 2 Serial I O SIO Port The serial I O SI...

Page 45: ...le on the 80C196NU On circuit emulation ONCE mode electrically isolates the microcontroller from the system See Chapter 12 Special Operating Modes for more information about idle powerdown standby and...

Page 46: ...either high or low depending on the clock multiplier mode you select The 80C196NU requires that you connect an external capacitor to the RPD pin if your design uses both powerdown mode and a clock mul...

Page 47: ...V TAVWL TAVRL TRLDV TRHDZ TRHRL TLHLH TRHLH TSLDV and TWHLH The 80C196NU has an additional power saving mode standby IDLPD 3 The 8XC196NP allows you to change the value of EP_REG to control which memo...

Page 48: ...3 Advanced Math Features...

Page 49: ......

Page 50: ...bit 3 of the destination address is clear address 00H 01H 07H it adds the result of the current instruction to the existing contents of the accumulator This simple example illustrates the results of...

Page 51: ...e following two examples illustrate the contents of the accumulator as a result of positive and negative saturation respectively 7FFFFFFFH 0111 1111 1111 1111 1111 1111 1111 1111 231 1 2147483647 8000...

Page 52: ...1111 1111 1111 1111 0 000 0000 0000 0000 0000 0000 0000 0000 0 1 111 1111 1111 1111 1111 1111 1111 1111 1 000 0000 0000 0000 0000 0000 0000 0000 1 Fractional mode shifts the result of a multiplication...

Page 53: ...locations 0C 0FH You can read from or write to the accumulator register as two words at locations 0CH and 0EH 80C196NU 15 8 Accumulator Value word 1 high byte 7 0 ACC_02 Accumulator Value word 1 low b...

Page 54: ...d 6 SME Saturation Mode Enable Set this bit to enable saturation mode See Table 3 2 In this mode the result of a signed multiplication operation is not allowed to overflow or underflow For unsigned mu...

Page 55: ...ation and sets the STSAT flag Positive saturation changes the accumulator value to 7FFFFFFFH negative saturation changes the accumulator value to 80000000H Accumulation proceeds normally after saturat...

Page 56: ...4 Programming Considerations...

Page 57: ......

Page 58: ...8 Yes 27 through 27 1 128 through 127 None WORD 16 No 0 through 216 1 0 through 65 535 Even byte address INTEGER 16 Yes 215 through 215 1 32 768 through 32 767 Even byte address DOUBLE WORD Note 1 32...

Page 59: ...is the least significant bit There are no alignment restric tions for BYTEs so they may be placed anywhere in the address space 4 1 3 SHORT INTEGER Operands A SHORT INTEGER is an 8 bit signed variable...

Page 60: ...least significant byte of the INTEGER is in the even byte address and the most significant byte is in the next high er odd address The address of an INTEGER is that of its least significant byte the e...

Page 61: ...y as the operand of the EB MOVI instruction For this operation the QUAD WORD variable must reside in the lower reg ister file and must be aligned at an address that is evenly divisible by eight 4 1 9...

Page 62: ...EBMOVI Extended interruptable block move Moves a block of word data from one memory location to another This instruction allows you to move blocks of up to 64K words between any two locations in the a...

Page 63: ...e used with long indexed addressing to access any memory location Extended variations of the indirect and indexed modes support the extended load and store in structions An extended load instruction m...

Page 64: ...se immediate addressing ADD AX 340 AX AX 340 PUSH 1234H SP SP 2 MEM_WORD SP 1234H DIVB AX 10 AL AX 10 AH AX MOD 10 4 2 3 Indirect Addressing The indirect addressing mode accesses an operand by obtaini...

Page 65: ...ion automatically increments the indirect address by one if the destination is an 8 bit register or by two if it is a 16 bit register When your code is assembled the assembler automat ically sets the...

Page 66: ...t and the base address as an indirect address register a WORD The following instructions use short indexed addressing LD AX 12H BX AX MEM_WORD BX 12H MULB AX BL 3 CX AX BL MEM_BYTE CX 3 The instructio...

Page 67: ...extended in dexed addressing In these instructions OFFSET is a 24 bit variable containing the offset and EX is a double word aligned 24 bit register containing the base address ELD AX OFFSET EX AX ME...

Page 68: ...page 00H then you must use the extended load and store instructions ELD ELDB EST and ESTB 4 4 DESIGN CONSIDERATIONS FOR 1 MBYTE DEVICES In general you should avoid creating tables or arrays that cros...

Page 69: ...SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs Also because some SFRs are cleared when read...

Page 70: ...d calling convention adopted by the C programming language has several key fea tures Procedures can always assume that the eight or sixteen bytes of register file memory starting at 1CH can be used as...

Page 71: ...ammed locations in nonvolatile memory or from bus lines that have been pulled high We recommend that you fill unused areas of code with NOPs and periodic jumps to an error rou tine or RST instruction...

Page 72: ...5 Memory Partitions...

Page 73: ......

Page 74: ...external memory configurations for the 1 Mbyte and 64 Kbyte operating modes a method for remapping the 4 Kbyte internal ROM 83C196NP only 5 1 MEMORY MAP OVERVIEW The instructions can address 16 Mbytes...

Page 75: ...and in terrupt vectors and program memory The device fetches its first instruction from location FF2080H Addresses in page FFH exist only in the internal 24 bit address space The implementation of pa...

Page 76: ...FH 002000H 001FFFH 001F00H 001EFFH 001C00H 001BFFH 000400H 0003FFH 000100H 0000FFH 000000H External Memory A2462 03 Page 00H 80C196NP NU External Memory 83C196NP External Memory if CCB1 2 0 A Copy of...

Page 77: ...data bus future SFR expansion Note 5 Indirect indexed extended 001BFF 000400 External device memory or I O connected to address data bus Indirect indexed extended 0003FF 000100 Upper register file reg...

Page 78: ...also be mapped to page 00H see Remapping Internal ROM 83C196NP Only on page 5 22 5 2 2 1 Program Memory in Page FFH Three partitions in page FFH can be used for program memory FF0100 FF1FFFH in exter...

Page 79: ...as shown in Table 5 4 Table 5 3 8XC196NP and 80C196NU Special purpose Memory Addresses 8XC196NP Address Hex 80C196NU Address Hex Description FF207F FF205E FF207F FF2060 Reserved each byte must contai...

Page 80: ...1 also controls ROM remapping For the 80C196NP and 80C196NU the CCBs are stored in exter nal memory locations F2018 F201AH For the 83C196NP the CCBs can be stored either in ex ternal memory locations...

Page 81: ...te 1F9EH Reserved EPA_PEND 1F6EH Reserved Reserved 1F9CH Reserved EPA_MASK 1F6CH Reserved BUSCON5 1F9AH Reserved Reserved 1F6AH ADDRMSK5 H ADDRMSK5 L 1F98H Reserved Reserved 1F68H ADDRCOM5 H ADDRCOM5...

Page 82: ...ntinued Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1F7EH Reserved Reserved 1F4EH Reserved Reserved 1F7CH Reserved Reserved 1F4CH Reserved BUSCON1 1F7AH Reserved Reserved 1...

Page 83: ...d Registers in the lower register file and registers being windowed can be accessed with direct addressing NOTE The register file must not contain code An attempt to execute an instruction from a loca...

Page 84: ...even address that is two bytes for 64 Kbyte mode or four bytes for 1 Mbyte mode greater than the desired starting address Before the CPU exe cutes a subroutine call or interrupt service routine it de...

Page 85: ...ack can be used most efficiently when it is located in the upper register file The following example initializes the top of the upper register file as the stack LD SP 400H Load stack pointer 5 2 4 3 C...

Page 86: ...to the 80C196NU WSR1 selects a 32 or 64 byte segment of high er memory to be windowed into the middle of the lower register file Figure 5 4 Because the areas in the lower register file do not overlap...

Page 87: ...SR values for windowing the upper register file WSR Address Reset State 0014H 00H The window selection register WSR has two functions One bit enables and disables the bus hold protocol The remaining b...

Page 88: ...of Peripheral SFRs Peripheral WSR or WSR1 Value for 32 byte Window 00E0 00FFH or 0060 007FH WSR or WSR1 Value for 64 byte Window 00C0 00FFH or 0040 007FH WSR Value for 128 byte Window 0080 00FFH EPORT...

Page 89: ...location 2 Add the offset to the base address of the window from Table 5 11 The result is the direct address 0360 037F 5BH 2DH 16H 0340 035F 5AH 0320 033F 59H 2CH 0300 031F 58H 02E0 02FF 57H 2BH 15H...

Page 90: ...17H 03C0H 5EH 03A0H 5DH 2EH 0380H 5CH 0360H 5BH 2DH 16H 0340H 5AH 0320H 59H 2CH 0300H 58H 02E0H 57H 2BH 15H 02C0H 56H 02A0H 55H 2AH 0280H 54H 0260H 53H 29H 14H 0240H 52H 0220H 51H 28H 0200H 50H 01E0H...

Page 91: ...location 1F8CH with direct addressing through a 64 byte window Table 5 10 on page 5 17 shows that you need to write 3EH to the window selection register It also shows that the base address of the 64...

Page 92: ...F80 1FDFH 5 3 2 5 Using the Linker Locator to Set Up a Window In this example the linker locator is used to set up a window The linker locator locates the win dow in the upper register file and determ...

Page 93: ...r mine the proper windowing RL196 MOD1 OBJ MOD2 OBJ registers 100h 03ffh windowsize 32 The above linker controls tell the linker to use registers 0100 03FFH for windowing and to use a window size of 3...

Page 94: ...e direct access to the entire lower register file clear bits 6 0 of the window selection register To enable direct access to a particular location in the lower register file you may select a smaller w...

Page 95: ...ed to internal ROM FF2000 FF2FFFH if EA is high and to external memory F2000 F2FFFH if EA is low In either case data in this area must be accessed with extended instructions With remapping enabled CCB...

Page 96: ...nded program counter EPC concatenated with the 16 bit master program counter PC It holds the address of the next in struction to be fetched The page number of the instruction is in the EPC In 1 Mbyte...

Page 97: ...t use extended instructions For extended instructions the CPU provides the page number Figure 5 8 Formation of Extended and Nonextended Addresses The code example below illustrates the use of extended...

Page 98: ...l memory depending on the device the instruc tion address and the value of the EA input 80C196NU Code executes from any page in external memory 80C196NP For devices without internal nonvolatile memory...

Page 99: ...5 5 Data Fetches in the 1 Mbyte and 64 Kbyte Modes Data fetches are the same in the 1 Mbyte and 64 Kbyte modes The device can access data in any page Data accesses to page 00H are nonextended Data acc...

Page 100: ...terface in detail and provides additional examples 5 6 1 Example 1 Using the 64 Kbyte Mode Figure 5 9 shows a system designed for operation in the 64 Kbyte mode Code executes only from page FFH which...

Page 101: ...s FF2FFFH FF2080H Program memory 80C196NP and 80C196NU External flash memory 83C196NP Internal ROM EA 1 external memory EA 0 FF207FH FF2000H Special purpose memory 80C196NP and 80C196NU External flash...

Page 102: ...H which store code and special purpose memory are implemented by internal ROM Data accesses to locations FF2000 FF2FFFH are directed to the flash memory if EA is low and to internal ROM if EA is high...

Page 103: ...External flash memory code or far constants FF00FFH FF0000H Reserved FEFFFFH 030000H Unimplemented 02FFFFH 010000H 128 Kbyte external RAM far data 00FFFFH 003000H External RAM near data 002FFFH 00200...

Page 104: ...83C196NP only The code and data in FF2000 FF2FFFH are implemented by internal ROM Remapping this area into page 00H by setting the REMAP bit CCB1 2 makes the far constants in FF2000 FF2FFFH of ROM acc...

Page 105: ...tants FBFFFFH 020000H Unimplemented 01FFFFH 010000H 64 Kbyte external RAM far data 00FFFFH 008000H 32 Kbyte external RAM near data 007FFFH 003000H Unimplemented 002FFFH 002080H 80C196NP and 80C196NU U...

Page 106: ...6 Standard and PTS Interrupts...

Page 107: ......

Page 108: ...rupts that go through the interrupt controller are serviced by interrupt service routines that you provide The upper and lower interrupt vectors in special purpose memory see Chapter 5 Memory Partitio...

Page 109: ...INT_MASK x 1 No Return Yes Return Reset INT_PEND x Bit Reset PTSSRV x Bit Priority Encoder Highest Priority Interrupt PUSH PC on Stack LJMP to ISR Execute Interrupt Service Routine POP PC from Stack P...

Page 110: ...function input see Bidirec tional Port Pin Configurations on page 7 7 If the EXTINTx interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instruction tha...

Page 111: ...ftware trap and NMI These interrupts are not affected by the EI enable interrupts and DI disable interrupts instructions and they cannot be masked All of these interrupts are serviced by the interrupt...

Page 112: ...onic Interrupt Controller Service PTS Service Name Vector Priority Name Vector Priority Nonmaskable Interrupt NMI INT15 FF203EH 30 EXTINT3 Pin EXTINT3 INT14 FF203CH 14 PTS14 FF205CH 29 EXTINT2 Pin EXT...

Page 113: ...errupt if a momentary negative glitch occurs while the input pin is held high For this reason interrupt inputs should normally be held low when they are inactive 6 3 3 Multiplexed Interrupt Sources Th...

Page 114: ...four state times plus the execution time of the next instruction When a standard interrupt request is acknowledged the hardware clears the interrupt pending bit and forces a call to the address conta...

Page 115: ...lock of data If your code contains routines that transfer large blocks of data you may get a more accurate worst case value if you use the BMOV instruction in your calculation instead of NORML See App...

Page 116: ...Figure 6 3 PTS Interrupt Response Time Cleared Set 1 Mbyte Mode 61 State Times 64 Kbyte Mode 56 State Times A0261 02 1 Mbyte Mode 4 3 2 1 64 Kbyte Mode 11 2 12 39 6 15 3 12 39 6 Ending Instruction End...

Page 117: ...TS in struction to globally enable the PTS When you assign an interrupt to a standard software service routine use the EI enable interrupts instruction to globally enable interrupt servicing NOTE The...

Page 118: ...SEL bit must be set manually to re enable the PTS channel 15 8 EXTINT3 EXTINT2 OVR2_3 OVR0_1 EPA3 EPA2 EPA1 7 0 EPA0 RI TI EXTINT1 EXTINT0 OVRTM2 OVRTM1 Bit Number Function 15 2 Reserved for compatibi...

Page 119: ...POPA restores it 7 0 EPA0 RI TI EXTINT1 EXTINT0 OVRTM2 OVRTM1 Bit Number Function 7 3 1 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit M...

Page 120: ...er PUSHA saves this register on the stack and POPA restores it 7 0 NMI EXTINT3 EXTINT2 OVR2_3 OVR0_1 EPA3 EPA2 EPA1 Bit Number Function 7 0 Setting a bit enables the corresponding interrupt The standa...

Page 121: ...will not allow another interrupt call until after the first instruction of the interrupt service routine is executed 2 The PUSHA instruction saves the contents of the PSW INT_MASK INT_MASK1 and windo...

Page 122: ...e interrupt service routine INT_PEND and INT_PEND1 can be read to determine which interrupts are pending They can also be modified written either to clear pending interrupts or to generate interrupts...

Page 123: ...M1 Bit Number Function 7 3 1 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the corresponding interrupt vector The standa...

Page 124: ...3 EPA2 EPA1 Bit Number Function 7 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the corresponding interrupt vector The s...

Page 125: ...ed data accesses to page 00H You cannot use EP_REG to change pages 6 6 1 Specifying the PTS Count For single and block transfer routines the first location of the PTSCB contains an 8 bit value called...

Page 126: ...R0_1 EPA3 EPA2 EPA1 7 0 EPA0 RI TI EXTINT1 EXTINT0 OVRTM1 OVRTM2 Bit Number Function 15 2 Reserved These bits are undefined 14 3 1 0 A bit is set by hardware to request an end of PTS interrupt for the...

Page 127: ...ser s Point of View for application examples with code Figure 6 12 shows the PTS control block for single transfer mode PTSCON Address PTSPCB 1 The PTS control PTSCON register selects the PTS mode and...

Page 128: ...PTS Source Address low byte 7 0 PTSCON M2 M1 M0 BW SU DU SI DI 7 0 PTSCOUNT Consecutive Byte or Word Transfers Register Location Function PTSDST PTSCB 4 PTS Destination Address Write the destination m...

Page 129: ...e address after each byte or word transfer DU Update PTSDST 0 reload original PTS destination address after each byte or word transfer 1 retain current PTS destination address after each byte or word...

Page 130: ...ocation to another using an 8 bit bus with no wait states See Table 6 4 on page 6 10 for execution times of PTS cycles The PTSCB in Table 6 6 sets up three PTS cycles that will transfer five bytes fro...

Page 131: ...M1 M0 BW SU DU SI DI 7 0 PTSCOUNT Consecutive Block Transfers Register Location Function PTSBLOCK PTSCB 6 PTS Block Size Specifies the number of bytes or words in each block Valid values are 1 32 incl...

Page 132: ...rent PTS destination address after each block transfer is complete SI PTSSRC Autoincrement 0 do not increment the contents of PTSSRC after each byte or word transfer 1 increment the contents of PTSSRC...

Page 133: ...output pulse is T2 The time the output is on is T1 the time the output is off is T2 T1 The formulas for frequency and duty cycle are shown below In most applications the frequency is held constant an...

Page 134: ...owing procedure This example uses the values stored in CSTORE1 and CSTORE2 to control the frequency and duty cycle of a PWM 1 Disable the interrupts and the PTS The DI instruction disables all standar...

Page 135: ...CONST1 selects T1 as first event time Load T1CONTROL with C2H enables timer 1 selects up counting at f 4 and enables the divide by four prescaler 7 Enable the EPA0 interrupt and select PTS service for...

Page 136: ...low byte 15 8 PTSCONST1 H PWM On time high byte 7 0 PTSCONST1 L PWM On time low byte 15 8 PTSPTR1 H Pointer 1 Value high byte 7 0 PTSPTR1 L Pointer 1 Value low byte 7 0 PTSCON M2 M1 M0 TMOD TBIT 7 0...

Page 137: ...EPA0_TIME and toggles the TBIT to one The next timer match occurs at time T2 T1 The EPA toggles the output to zero and initiates the third PTS cycle The PTS actions are the same as in cycle 1 and gene...

Page 138: ...the next timer match occurs the output is toggled and the device executes a normal interrupt ser vice routine which performs these operations 1 The routine writes the new value of T1 in CSTORE1 to PT...

Page 139: ...nerate a PWM waveform in PWM remap mode EPA0 as serts the output and EPA1 deasserts it For each channel an interrupt is generated every T2 pe riod but the comparison times for the channels are offset...

Page 140: ...2H enables timer 1 selects up counting at f 4 and enables the divide by four prescaler 5 Enable the EPA0 and EPA1 interrupts and select PTS service for them Set INT_MASK 7 and INT_MASK1 0 Set PTSSEL 7...

Page 141: ...0 0 0 0 0 0 15 8 PTSCONST1 HI PWM Const 1 Value high byte 7 0 PTSCONST1 LO PWM Const 1 Value low byte 15 8 PTSPTR1 HI Pointer 1 Value high byte 7 0 PTSPTR1 LO Pointer 1 Value low byte 7 0 PTSCON M2 M1...

Page 142: ...1 interrupts continue with EPA0 asserting the output and EPA1 deas serting it Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode These bits specify the PTS mode M2 M1 M0 0 1 0 PW...

Page 143: ...PA1_TIME and set PTSSEL 8 to re enable PTS service for EPA1 This adjustment changes the duty cycle without affecting the period By using two EPA channels in the PWM remap mode you can generate duty cy...

Page 144: ...7 I O Ports...

Page 145: ......

Page 146: ...output pins or serve alternate functions Table 7 1 provides an overview of the device I O ports The remainder of this chapter describes the ports in more detail and explains how to configure the pins...

Page 147: ...Pin Special function Signal s Special function Signal Type Associated Peripheral P1 0 EPA0 I O EPA P1 1 EPA1 I O EPA P1 2 EPA2 I O EPA P1 3 EPA3 I O EPA P1 4 T1CLK I Timer 1 P1 5 T1DIR I Timer 1 P1 6...

Page 148: ...Each bit of Px_MODE controls whether the corresponding pin functions as a standard I O port pin or as a special function signal 0 standard I O port pin 1 special function signal P1_PIN P2_PIN P3_PIN P...

Page 149: ...he pin Input signals are buffered The ports use Schmitt triggered buffers for improved noise immunity The signals are latched into the Px_PIN sample latch and output onto the internal bus when the Px_...

Page 150: ...ructure Vcc Q2 Q1 Px_REG Px_DIR Sample Latch PH1 Clock Internal Bus SFDATA SFDIR Px_MODE Px_PIN D Q 0 1 0 1 Vcc Vcc Q R S Any Write to Px_MODE Weak Pullup Medium Pullup RESET RESET Q3 Q4 Vss Read Port...

Page 151: ...off 3 Px_PIN contains the current value on the pin 4 During reset and until the first write to Px_MODE Q4 is on Table 7 5 Logic Table for Bidirectional Ports in Special function Mode Configuration Com...

Page 152: ...Px_DIR bit Open drain outputs require external pull ups 2 Write to Px_MODE to select either I O or special function mode Writing to Px_MODE regardless of the value written turns off the weak pull ups...

Page 153: ...d I O Signal Px_DIR Px_MODE Px_REG Complementary output driving 0 0 0 0 Complementary output driving 1 0 0 1 Open drain output strongly driving 0 1 0 0 Open drain output high impedance 1 0 1 Input 1 0...

Page 154: ...2 EXTINT0 Writing to P2_MODE 2 sets the EXTINT0 interrupt pending bit INT_PEND 3 After configuring the port pins clear the interrupt pending registers before globally enabling interrupts See Design C...

Page 155: ...faults to the CS0 function This chip select signal detects address ranges that contain the CCBs and FF2080H program start up address See Chapter 13 Interfacing with External Memory for a detailed desc...

Page 156: ...its 6 Enable interrupts optional by executing the EI instruction 7 3 EPORT The EPORT is a four bit bidirectional memory mapped I O port in the 8XC196NP but a stan dard I O port in the 80C196NU For the...

Page 157: ...ailable only on the 80C196NU EP_MODE 1FE1H EPORT Mode Each bit of EP_MODE controls whether the corresponding pin functions as a standard I O port pin or as an extended address signal Setting a bit con...

Page 158: ...ccesses the data multiplexer is set to the 1 Mbyte mode input and EDAR is loaded with the extended address For nonextended data accesses the data multiplexer is set to the 64 Kbyte mode input and EDAR...

Page 159: ...the datasheet for exact specifications When RESET is inactive both Q3 and Q4 are off Q1 and Q2 determine output drive 7 3 1 2 Output Enable If RESET HOLD idle or powerdown is asserted the gates that c...

Page 160: ...Q1 EP_REG EP_MODE Sample Latch PH1 Clock Internal Bus EP_PIN D Q 0 1 Vcc Vcc Weak Pullup Medium Pullup RESET Q3 Q4 Buffer Vss Read Port LE 300ns Delay I O Pin Address Bit from Address MUX EP_DIR POWER...

Page 161: ...op eration of EPORT Table 7 11 Logic Table for EPORT in I O Mode Configuration Complementary Output Open drain Output Input EP_MODE 0 0 0 0 EP_DIR 0 0 0 1 Note 2 1 EP_REG 0 1 0 1 Address Bit X X X X...

Page 162: ...d the implications of changing memory addressing on the fly To change a pin from I O to address clear the EP_REG x bit and set the EP_MODE x bit Clearing EP_REG x is required for compatibility with so...

Page 163: ...space However we recommend that you clear the EP_REG bits for any EPORT pins configured as extended address signals in order to maintain compatibility with soft ware development tools NOTE If any pins...

Page 164: ...ddress that was output If these lines are being used to enable external memory that memory will remain enabled until a different page is accessed During the CCB fetch all EPORT lines are strongly driv...

Page 165: ......

Page 166: ...8 Serial I O SIO Port...

Page 167: ......

Page 168: ...RT The UART has one synchronous mode mode 0 and three asynchronous modes modes 1 2 and 3 for both transmission and reception Figure 8 1 SIO Block Diagram The serial port receives data into the receive...

Page 169: ...tput for data P1 4 T1CLK I Timer 1 Clock External clock source for the baud rate generator input Table 8 2 Serial Port Control and Status Registers Mnemonic Address Description INT_MASK 0013H Interrup...

Page 170: ...ins P2_REG 1FCDH Port 2 Output Data This register holds data to be driven out on the pins of port 2 Set P2_REG 1 for the RXD P2 1 pin Write the desired output data for the TXD P2 0 pin to P2_REG 0 SBU...

Page 171: ...ive timing of these sig nals Note that only mode 0 uses RXD as an open drain output Figure 8 2 Typical Shift Register Circuit for Mode 0 SP_STATUS 1FB9H Serial Port Status This register contains the s...

Page 172: ...nding register is set immediately before the RI flag is set During a transmis sion the TI flag is set immediately after the end of the last eighth data bit is transmitted The TI pending bit in the int...

Page 173: ...ift clock starts when the baud rate generator is initialized The receive shift clock is reset when a start bit high to low transition is received Therefore the transmit clock may not be synchronized w...

Page 174: ...de 2 Mode 3 differs from mode 2 during transmissions in that parity can be enabled in which case the ninth bit becomes the parity bit When parity is disabled data bits 0 7 are written to the serial po...

Page 175: ...the port pins to serve as special function signals and set up the SIO channel 8 4 1 Configuring the Serial Port Pins Before you can use the serial port you must configure the associated port pins to s...

Page 176: ...nsmitted in mode 2 or 3 This bit is cleared after each transmission so it must be set before SBUF_TX is written When SP_CON 2 is set this bit takes on the even parity value 3 REN Receive Enable Settin...

Page 177: ...ts the communications mode and enables or disables the receiver parity checking and nine bit data transmission For the 80C196NU it also enables or disables the divide by two prescaler 7 0 8XC196NP PAR...

Page 178: ...BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0 Bit Number Bit Mnemonic Function 15 CLKSRC Serial Port Clock Source This bit determines whether the serial port is clocked from an...

Page 179: ...ptions and transmissions For the 80C196NU using the internal peripheral clock at 50 MHz the maximum baud rates are doubled 12 5 Mbaud for mode 0 trans missions 8 33 Mbaud for mode 0 receptions and 3 1...

Page 180: ...rs all bits except TXE For this reason we recommend that you copy the contents of the SP_STATUS register into a shadow register and then execute bit test instruc tions such as JBC and JBS on the shado...

Page 181: ...sabled SP_CON 2 0 and the ninth data bit received is high RB8 is set if parity is enabled SP_CON 2 1 and a parity error occurred Reading SP_STATUS clears this bit 6 RI Receive Interrupt This bit is se...

Page 182: ...e RI and TI flags but does not clear the corresponding interrupt pending bits The RI and TI flags in the SP_STATUS and the corresponding interrupt pending bits can be set even if the RI and TI interru...

Page 183: ......

Page 184: ...9 Pulse width Modulator...

Page 185: ......

Page 186: ...ns of the signals and registers discussed in this chapter please refer to Ap pendix B Signal Descriptions and Appendix C Registers 9 1 PWM FUNCTIONAL OVERVIEW The PWM module has three channels each of...

Page 187: ...escription P4 0 PWM0 O Pulse width modulator 0 output with high drive capability P4 1 PWM1 O Pulse width modulator 1 output with high drive capability P4 2 PWM2 O Pulse width modulator 2 output with h...

Page 188: ...loaded into this register causes the PWM to output a low continu ously 0 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle P4_DIR 1FDBH Port 4 Direction...

Page 189: ...the output is switched high Loading PWMx_CONTROL with 00H forces the output to remain low Figure 9 3 shows typical PWM output waveforms The PWM can generate a duty cycle ranging in length from 0 to 99...

Page 190: ...requencies on the 8XC196NP The value of CON_REG0 0 determines the output fre quency by enabling or disabling the clock prescaler Use the following formulas to calculate the output frequency FPWM or ou...

Page 191: ...put frequency by enabling or disabling the divide by two or divide by four clock prescal er NOTE Use the EPA module to produce variable PWM output frequencies see Operating in Compare Mode on page 10...

Page 192: ...96NP CLK0 7 0 80C196NU CLK1 CLK0 Bit Number Bit Mnemonic Function 7 1 NP 7 2 NU Reserved for compatibility with future devices write zeros to these bits 0 NP CLK0 Enable PWM Clock Prescaler This bit c...

Page 193: ...egister determines the duty cycle of the PWM x channel A zero loaded into this register causes the PWM to output a low continuously 0 duty cycle An FFH in this register causes the PWM to have its maxi...

Page 194: ...ing the PWM function To do so follow this sequence 1 Clear the corresponding bit of P4_DIR see Table 9 5 2 Set the corresponding bit of P4_MODE see Table 9 5 3 Set or clear the corresponding bit of P4...

Page 195: ...xternal D A circuitry With proper components a highly accurate 8 bit D A converter can be made using the PWM Figure 9 7 PWM to Analog Conversion Circuitry Buffer to Make Output Swing Rail to Rail 8XC1...

Page 196: ...10 Event Processor Array EPA...

Page 197: ......

Page 198: ...er 1 and timer 2 Figure 10 1 In the input mode the EPA monitors an input pin for an event a rising edge a falling edge or an edge in either direction When the event occurs the EPA records the value of...

Page 199: ...and Timer Counter Signals Port Pin EPA Signal s EPA Signal Type Description P1 3 0 EPA3 0 I O High speed input output for capture compare channels 0 3 P1 4 T1CLK I External clock source for timer 1 P1...

Page 200: ...e mode these registers contain the captured timer value In compare mode these registers contain the time at which an event is to occur In capture mode these registers are buffered to allow two capture...

Page 201: ...the pin The CPU can still write to P1_REG but the pin is unaffected until it is switched back to its standard I O function This feature allows software to configure a pin as standard I O clear P1_MOD...

Page 202: ...ly Figure 10 2 illustrates the timer counter structure Figure 10 2 EPA Timer Counters T2CLK f 4 Timer 1 Overflow T2DIR T2CONTROL 6 Timer 1 T1CLK f 4 Prescaler Module T1CONTROL 2 0 3 T1CONTROL 6 T1DIR...

Page 203: ...her the direction control bit of the timer 2 control register or the direction control assigned to timer 1 controls the count direction This method called cascading can pro vide a slow clock for idle...

Page 204: ...h Table State of X_internal TxCLK State of Y_internal TxDIR Count Direction 0 Increment 1 Increment 0 Increment 1 Increment 0 Decrement 1 Decrement 0 Decrement 1 Decrement Optical Reader TxDIR TxCLK D...

Page 205: ...when a capture overrun occurs reset its own base timer in compare mode reset the opposite timer in both compare and capture mode Each EPA channel has a control register EPAx_CON capture compare chann...

Page 206: ...e is loaded into the buffer and held there After the CPU reads the EPAx_TIME register the contents of the capture buffer are automatically transferred into EPAx_TIME and the EPA interrupt pending bit...

Page 207: ...r Both situations set the overrun interrupt pending bit and if the interrupt is enabled they generate an overrun interrupt Table 10 4 summarizes the possible actions when a valid event oc curs NOTE In...

Page 208: ...cognizes the captured edge as valid The input frequency at which this occurs depends on the length of the interrupt service routine as well as other factors Unless the interrupt service routine includ...

Page 209: ...10 4 2 Operating in Compare Mode When the selected timer value matches the event time value the action specified in the control register occurs i e the pin is set cleared or toggled If the re enable b...

Page 210: ...s 56 state times for external stack usage and 54 state times for internal stack usage see Standard Interrupt Latency on page 6 8 To determine the execution time for an interrupt service routine add up...

Page 211: ...utput You can generate a high speed pulse width modulated output with a pair of EPA channels and the PTS set up in PWM remap mode PWM Remap Mode Example on page 6 32 describes how to configure the EPA...

Page 212: ...5 PROGRAMMING THE EPA AND TIMER COUNTERS This section discusses configuring the port pins for the EPA and the timer counters describes how to program the timers and the capture compare channels and e...

Page 213: ...e and direction control source M2 M1 M0 Clock Source Direction Source 0 0 0 f 4 UD bit T1CONTROL 6 X 0 1 T1CLK pin UD bit T1CONTROL 6 0 1 0 f 4 T1DIR pin 0 1 1 T1CLK pin T1DIR pin 1 1 1 quadrature clo...

Page 214: ...Clock Source Direction Source 0 0 0 f 4 UD bit T2CONTROL 6 X 0 1 T2CLK pin UD bit T2CONTROL 6 0 1 0 f 4 T2DIR pin 0 1 1 T2CLK pin T2DIR pin 1 0 0 timer 1 overflow UD bit T2CONTROL 6 1 1 0 timer 1 sam...

Page 215: ...load the event time into EPAx_TIME To program a capture event you need only write to EPAx_CON Table 10 5 shows the effects of various combinations of EPAx_CON bit settings Table 10 5 Example Control R...

Page 216: ...t pin EPA1 with EPA capture compare channel 1 When the remap feature of EPA3 is enabled EPA capture compare channel 2 shares output pin EPA3 with EPA capture compare channel 3 0 remap feature disabled...

Page 217: ...eference timer rather than only upon the first time match 0 compare function is disabled after a single event 1 compare function always enabled 2 Reserved always write as zero EPAx_CON Continued x 0 3...

Page 218: ...th full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the buffer In Compare Mode RT 0 disables the res...

Page 219: ...rupt pending bit is set each time a match occurs on an enabled event even if the interrupt is specifically masked in the mask register In capture mode an interrupt pending bit is set each time a progr...

Page 220: ...ice routines be cause the PTS cannot determine the exact source of the interrupt When an OVR0_1 or OVR2_3 occurs the user s software service routine can poll the bits of the EPA_PEND register which ha...

Page 221: ...gram were written in the C programming lan guage ASM versions are also available from ApBUILDER NOTE The initialization file 80c196np h used in these examples is available from the Intel Applications...

Page 222: ...A channel 0 to capture edges rising and falling on the EPA0 pin The program also shows how to set up an the EPA interrupt You can add your own code for the interrupt service routine pragma model EX in...

Page 223: ...hows how to service the interrupts with the PTS The PWM signal in this example has a 50 duty cycle pragma model EX include 80c196np h define PTS_BLOCK_BASE 0x98 Create typedef template for the PWM_TOG...

Page 224: ...oid EPA0_TIME PWM_toggle_CB_3 ptscon 0x42 Sample code that could be used to generate a PWM with an EPA channel setbit p1_reg 0x1 init output clrbit p1_dir 0x1 set to output setbit p1_mode 0x1 set spec...

Page 225: ......

Page 226: ...11 Minimum Hardware Considerations...

Page 227: ......

Page 228: ...memory locations FF2000 FF2FFFH reside in external memory For the 83C196NP these locations can reside either in external memory or in internal ROM RPD I Return from Powerdown Timing pin for the return...

Page 229: ...y 80C196NU and the internal clock generators The internal clock generators provide the peripheral clocks CPU clock and CLKOUT signal When using an external clock source instead of the on chip oscillat...

Page 230: ...ator frequency range FOSC and the crystal manufacturer s datasheet for recommended load capacitors 2 The number of VCC and VSS pins varies with package type see datasheet Be sure to connect all VCC pi...

Page 231: ...es of high speed CMOS logic often produce noise spikes on the power supply lines and outputs To minimize noise it is important to follow good design and board lay out techniques We recommend liberal u...

Page 232: ...or In this application the crystal operates in a parallel resonance mode The feedback resis tor Rf consists of paralleled n channel and p channel FETs controlled by the internal powerdown signal In po...

Page 233: ...e noise spikes To reduce this coupling mount the crystal oscillator and ca pacitors near the device and use short direct traces to connect to XTAL1 XTAL2 and VSS To further reduce the effects of noise...

Page 234: ...t power on the interaction between the internal amplifier and its feedback capacitance i e the Miller effect may cause a load of up to 100 pF at the XTAL1 pin if the signal at XTAL1 is weak such as mi...

Page 235: ...egisters CCRs and then fetches the first instruction Figure 11 7 shows the reset sequence timing Figure 11 7 Reset Timing Sequence RESET Pin CLKOUT ALE RD A15 0 A19 16 00H 00H 18H CCB0 201AH 1AH 20H S...

Page 236: ...et Circuitry 11 6 1 Generating an External Reset To reset the device hold the RESET pin low for at least one state time after the power supply is within tolerance and the oscillator has stabilized Whe...

Page 237: ...y not be reset because the capacitor will keep the voltage above VIL Since RESET is asserted for only 16 state times it may be necessary to lengthen and buffer the system reset pulse Figure 11 10 show...

Page 238: ...to FF2080H and resets the special function registers SFRs See Table C 2 on page C 2 for the reset values of the SFRs 11 6 3 Issuing an Illegal IDLPD Key Operand The device resets itself if an illegal...

Page 239: ......

Page 240: ...12 Special Operating Modes...

Page 241: ......

Page 242: ...g mode a rising edge on EXTINTx sets the EXTINTx interrupt pending bit EXTINTx is sampled during phase 2 CLKOUT high The minimum high time is one state time In standby and powerdown modes asserting th...

Page 243: ...r the return from powerdown circuit If your application uses powerdown mode connect a capacitor between RPD and VSS if either of the following conditions is true the internal oscillator is the clock s...

Page 244: ...the corresponding pin functions as a standard I O port pin or as a special function signal Setting a bit configures a pin as a special function signal clearing a bit configures a pin as a standard I...

Page 245: ...ring Power saving Modes 8XC196NP A3161 01 Clock Generators CPU Clocks PH1 PH2 Divide by two Circuit Peripheral Clocks PH1 PH2 CLKOUT Disable Clocks Powerdown Disable Clocks Idle Powerdown XTAL1 XTAL2...

Page 246: ...so the special function registers SFRs and register RAM retain their data and the peripherals and interrupt system remain active Table B 5 on page B 13 lists the val ues of the pins during idle mode...

Page 247: ...ystem bus control signals to become inactive and the peripherals to turn off The phase locked loop PLL circuitry and the on chip oscillator continue to operate Table B 5 on page B 13 lists the values...

Page 248: ...ogic zero which causes the CPU to stop executing instructions the system bus control signals to become inactive the CLKOUT signal to become high and the peripherals to turn off Power consumption drops...

Page 249: ...ESET must be held low until the oscillator and phase locked loop circuitry have stabilized 12 5 3 2 Asserting an External Interrupt Signal The final way to exit powerdown mode is to assert an external...

Page 250: ...nect the external component shown in Figure 12 4 to the RPD pin The discharging of the capac itor causes a delay that allows the oscillator and phase locked loop circuitry to stabilize before the inte...

Page 251: ...prompted by the switching voltage levels strongly drives a logic one quickly pulling the RPD pin back up to VCC see recovery time in Fig ure 12 5 The time constant RC follows an exponential charging c...

Page 252: ...r value in farads TDIS is the worst case discharge time in seconds I is the discharge current in amperes Vt is the threshold voltage NOTE If powerdown is re entered and exited before C1 charges to VCC...

Page 253: ...weakly pulled high or low During ONCE mode RESET must be held high or the device will exit ONCE mode and enter the reset state Holding the ONCE signal high during the rising edge of RESET causes the...

Page 254: ...plier circuitry disabled 0 1 Reserved CAUTION This combination causes the device to enter an unsupported test mode 1 0 Doubled clock doubling circuitry enabled Internal clock is twice the XTAL1 input...

Page 255: ......

Page 256: ...13 Interfacing with External Memory...

Page 257: ......

Page 258: ...e device generates inter nally Internally the device has 24 address lines but only the lower 20 address lines A19 0 are implemented with external pins The absence of the upper four address bits at the...

Page 259: ...te address space NOTE Internally there are 24 address bits however only 20 address lines A19 0 are bonded out The internal address space is 16 Mbytes 000000 FFFFFFH and the external address space is 1...

Page 260: ...0 CCR0 determines whether this pin functions as BHE or WRH CCR0 2 1 selects BHE CCR0 2 0 selects WRH P5 5 WRH BREQ O Bus Request This active low output signal is asserted during a hold cycle when the...

Page 261: ...the pin is configured for its special function see Bidirectional Port Pin Configurations on page 7 7 and the bus hold protocol is enabled Setting bit 7 of the window selection register WSR enables the...

Page 262: ...write is occurring This signal is asserted only during external memory writes The chip configuration register 0 CCR0 determines whether this pin functions as WR or WRL CCR0 2 1 selects WR CCR0 2 0 sel...

Page 263: ...ption ADDRCOM0 ADDRCOM1 ADDRCOM2 ADDRCOM3 ADDRCOM4 ADDRCOM5 1F40H 1F48H 1F50H 1F58H 1F60H 1F68H Address Compare Register This 16 bit register holds the upper 12 bits of the base address of the address...

Page 264: ...mpare ADDRCOMx register specifies the base lowest address of the address range The base address of a 2n byte address range must be on a 2n byte boundary 15 8 BASE19 BASE18 BASE17 BASE16 7 0 BASE15 BAS...

Page 265: ...nt bits of MASK19 8 in the address mask register 15 8 MASK19 MASK18 MASK17 MASK16 7 0 MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8 Bit Number Bit Mnemonic Function 15 12 Reserved for compatib...

Page 266: ...select Setup on page 13 12 for a chip select initialization procedure that avoids this difficulty For an address range satisfying these restrictions set up the ADDRCOMx and ADDRMSKx reg isters as fol...

Page 267: ...er of wait states the bus width and the address data multiplexing for all external bus cycles that access address range x 7 0 DEMUX BW16 WS1 WS0 Bit Number Bit Mnemonic Function 7 DEMUX Address Data M...

Page 268: ...new values The first lines of your program should perform two tasks 1 Set the stack pointer 2 Initialize all of the chip select registers ADDRCOMx ADDRMSKx and BUSCONx by using the procedure in Initi...

Page 269: ...rite to ADDRCOMx to establish the desired base address 2 3 Write to ADDRMSKx to establish the desired address range 2 4 Write the desired bus parameter values to BUSCONx 2 5 Repeat steps 2 1 2 4 for x...

Page 270: ...for CS2 is 8 Kbytes or 213 bytes n 13 The number of bits to be set in MASK19 8 of ADDRMSK2 is 20 n 7 After the 7 most significant bits of MASK19 8 are set ADDRMSK2 contains 0FE0H Results for CS0 and...

Page 271: ...ses on page 13 1 When the device returns from reset the bus controller fetches the CCBs and loads them into the CCRs From this point these CCR bit values define the chip configuration until the device...

Page 272: ...s cycles 0 write strobe mode the BHE WRH pin operates as WRH and the WR WRL pin operates as WRL 1 standard write control mode the BHE WRH pin operates as BHE and the WR WRL pin operates as WR 1 BW16 B...

Page 273: ...he first bus cycle following a chip select output change and the first write cycle following a read cycle See Deferred Bus cycle Mode 80C196NU Only on page 13 40 0 deferred bus cycle mode disabled 1 d...

Page 274: ...he READY pin is active for the CCB0 and CCB1 fetches and can be used to insert additional wait states see Wait States Ready Control on page 13 26 CCB0 can be fetched over a 16 bit bus even though BW16...

Page 275: ...6 pin is active that is the chip responds to external requests for additional wait states The INST pin is low deasserted The AD15 0 pins are active The following port pins are weakly held high P1 7 0...

Page 276: ...D7 0 8XC196 Device 8 bit Data Driven with the data currently on the internal bus AD15 8 8 bit Demultiplexed Bus 16 bit Demultiplexed Bus Bus Control Address Bits 16 19 Address Bits 0 15 16 bit Multipl...

Page 277: ...dress from A19 0 In a 16 bit system the data is on AD15 0 In an 8 bit system the data is on AD7 0 AD15 8 drive the data currently on the high byte of the internal bus In multiplexed mode bottom half o...

Page 278: ...an 8 bit system one data word is transferred as two bytes over AD7 0 in successive bus cycles and AD15 8 drive the upper eight address bits for the entire bus cycle The flexibility of the chip select...

Page 279: ...the 80C196NU are shown in Figures 13 20 through 13 23 CLKOUT and ALE are the same in multiplexed and demultiplexed buses The CLKOUT period is twice the internal oscillator period 2t The bus cycles sh...

Page 280: ...d Demultiplexed 16 bit Buses 8XC196NP CLKOUT RD ALE AD15 0 Address Data WR A19 0 AD15 0 RD WR AD15 0 AD15 0 Data Address Data Data Address Data Address Demultiplexed Multiplexed A2461 02 TRLDV TAVDV T...

Page 281: ...quires two cycles The first cycle accesses the lower byte and the second cycle accesses the upper byte Except for requiring an extra cycle to write the bytes sep arately the timings are the same as on...

Page 282: ...Address A19 0 WR AD7 0 AD7 0 Data Low Address Data Low Address Data Low Address Demultiplexed Multiplexed AD15 8 RD Data AD7 0 Data WR AD7 0 Data High Address High Address Address Data Low Address Da...

Page 283: ...the bus for an external bus cycle the external device can pull the READY signal low to indicate it is not ready In response the bus controller inserts wait states to lengthen the bus cycle until the e...

Page 284: ...imum TCLYX specification or additional unwanted wait states might be added In all cases refer to the datasheets for the current specifications for TAVYV and TCLYX Table 13 11 READY Signal Timing Defin...

Page 285: ...e 13 13 READY Timing Diagram Multiplexed Mode T0013 02 TWLWH 2t TQVWH 2t TCLYX max TAVYV TLHLH 2t TRLRH 2t TAVDV 2t TRLDV 2t Address Out Data In Address Out Data Out CLKOUT READY ALE RD AD15 0 WR AD15...

Page 286: ...RY Figure 13 14 READY Timing Diagram Demultiplexed Mode 8XC196NP T0007 02 TCLYX max TAVDV 2t TWLWH 2t TAVYV TLHLH 2t TRLRH 2t TRLDV 2t TQVWH 2t Data Data Valid CLKOUT READY ALE RD AD15 0 WR AD15 0 BHE...

Page 287: ...196Nx bus it asserts the HOLD signal HOLD is sampled while CLKOUT is low The 8XC196Nx responds by releasing the bus and asserting HLDA During this hold time the address data bus floats and signals CSx...

Page 288: ...CLHAH CLKOUT Low to HLDA High TCLBRL CLKOUT Low to BREQ Low TCLBRH CLKOUT Low to BREQ High THALAZ HLDA Low to Address Float THAHAX HLDA High to Address No Longer Float THALBZ HLDA Low to BHE INST RD W...

Page 289: ...o disable hold requests clear WSR 7 The 8XC196Nx does not take control of the bus immedi ately after HLDEN is cleared Instead it waits for the current hold request to finish and then dis ables the bus...

Page 290: ...ce would try to fetch the chip configuration byte from external memory after RESET was brought high Bus contention would occur because both the external device and the 8XC196Nx would attempt to access...

Page 291: ...es BHE can be used to select the bank of memory that stores the high odd byte Figure 13 10 on page 13 22 illustrates use of the standard mode in a 16 bit system In this example WR writes words to the...

Page 292: ...re 13 18 Decoding WRL and WRH The write strobe mode eliminates the need to externally decode high byte and low byte write sig nals to external 16 bit memory on a 16 bit bus When the write strobe mode...

Page 293: ...bytes are put onto the data bus and the memory controller discards the unwanted byte Figure 13 19 A System with 8 bit and 16 bit Buses 13 9 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest data...

Page 294: ...5 0 read WR AD15 0 write BHE INST AD15 8 TCLCL Address Out Data Data Out Address Out Address Out TCHCL TLHLL Valid A2367 05 TCLLH TRLCL TLLCH TLHLH TLLRL TRLRH TRHLH TAVLL TLLAX TRLDV TRHDZ TRLAZ Addr...

Page 295: ...TCLCL TCLLH TLHLL TRLAZ TRHDZ TAVLL TWLWH TCHWH TWHLH TQVWH TWHBX TRHBX T TRLCL T TCHDV TLHLH TLLCH TLLRL TRHLH TRLRH TAVDV TLLAX TRLDV TLLWL TWHQX TWHAX TRHAX TWHSH TRHSH Address Out Data In Address...

Page 296: ...tem Bus Timing 8XC196NP CLKOUT ALE RD AD15 0 read WR AD15 0 write BHE INST A19 0 CSx TCLCL Valid Valid Address Out TCHCL TLHLL Valid A2368 05 TCLLH TCLDV TLLCH TLHLH TRLCH TRLRH TRHLH TRLDV TRHDZ TAVD...

Page 297: ...when using the 80C196NU in demultiplexed mode with slow memories As shown in Figure 13 24 a delay of 2t occurs in the first bus cycle follow ing a chip select output change and the first write cycle f...

Page 298: ...H EXTERNAL MEMORY Figure 13 24 Deferred Bus cycle Mode Timing Diagram 80C196NU TLHLH 2t TWHLH 2t TRHLH 2t TAVRL 2t TAVDV 2t TAVWL 2t valid valid valid CLKOUT ALE RD AD15 0 WR AD15 0 BHE INST A19 16 CS...

Page 299: ...lexed mode or address data bus multiplexed mode Table 13 16 AC Timing Definitions Symbol Definition The External Memory System Must Meet These Specifications TAVDV Address Valid to Input Data Valid Ma...

Page 300: ...k for external devices TCHWL CLKOUT High to WR Low Time between CLKOUT going high and WR going active TCLCL CLKOUT Cycle Time Normally 2t TCLLH CLKOUT Falling to ALE Rising Use to derive other timings...

Page 301: ...TRLAZ RD Low to Address Float Used to calculate when the device stops driving address on the bus TRLCH RD Low to CLKOUT High Maximum time between RD being asserted and CLKOUT going high TRLCL RD Low t...

Page 302: ...nd chip select output are held after WR inactive TWLCH WR Low to CLKOUT High Minimum and maximum time between WR being asserted and CLKOUT going high TWLCL WR Low to CLKOUT Low Minimum and maximum tim...

Page 303: ......

Page 304: ...A Instruction Set Reference...

Page 305: ......

Page 306: ...jump instructions Table A 4 on page A 5 defines the symbols used in Table A 6 Table A 5 on page A 6 defines the variables used in Table A 6 to represent instruction operands Table A 6 beginning on pag...

Page 307: ...im in ix 9x ORB XORB di im in ix di im in ix Ax LD ADDC di im in ix di im in ix Bx LDB ADDCB di im in ix di im in ix Cx ST BMOV ST STB CMPL STB di in ix di in ix Dx JNST JNH JGT JNC JNVT JNV JGE JNE...

Page 308: ...2op Note 2 di im in ix di im in ix 8x CMP DIVU Note 2 di im in ix di im in ix 9x CMPB DIVUB Note 2 di im in ix di im in ix Ax SUBC LDBZE di im in ix di im in ix Bx SUBCB LDBSE di im in ix di im in ix...

Page 309: ...gnificant bit of the operand changes during the shift For divide operations the quotient is stored in the low order half of the destination operand and the remainder is stored in the high order half T...

Page 310: ...er bit 1 specified register bit 0 JNC C 0 C 1 JNH C 0 OR Z 1 C 1 AND Z 0 JC C 1 C 0 JH C 1 AND Z 0 C 0 OR Z 1 JGE N 0 N 1 JGT N 0 AND Z 0 N 1 OR Z 1 JLT N 1 N 0 JLE N 1 OR Z 1 N 0 AND Z 0 JNST ST 0 ST...

Page 311: ...The value must be in the range of 00 FCH ptr2_reg A double pointer register used with the EBMOVI instruction Must be aligned on an address that is evenly divisible by 8 The value must be in the range...

Page 312: ...lag Settings Z N C V VT ST ADDB 2 operands ADD BYTES Adds the source and destination byte operands and stores the sum into the destination operand DEST DEST SRC DEST SRC ADDB breg baop 011101aa baop b...

Page 313: ...ttings Z N C V VT ST 0 0 AND 3 operands LOGICAL AND WORDS ANDs the two source word operands and stores the result into the destination operand The result has ones in only the bit positions in which bo...

Page 314: ...of data can be located anywhere in page 00H of register RAM but should not overlap Because the source SRCPTR and destination DSTPTR pointers are 16 bits wide this instruction uses nonextended data mov...

Page 315: ...EBMOVI instruction PTSSRC and PTSDST will operate from the page defined by EP_REG EP_REG should be set to 00H to select page 00H see Accessing Data on page 5 23 The 80C196NU forces EP_REG to 00H COUNT...

Page 316: ...LRC 11111000 PSW Flag Settings Z N C V VT ST 0 CLRVT CLEAR OVERFLOW TRAP FLAG Clears the overflow trap flag VT 0 CLRVT 11111100 PSW Flag Settings Z N C V VT ST 0 CMP COMPARE WORDS Subtracts the source...

Page 317: ...operands are specified using the direct addressing mode The flags are altered but the operands remain unaffected If a borrow occurs the carry flag is cleared otherwise it is set DEST SRC DEST SRC CMPL...

Page 318: ...performed concurrently low word DEST DEST SRC high word DEST DEST MOD SRC DEST SRC DIV lreg waop 11111110 100011aa waop lreg PSW Flag Settings Z N C V VT ST DIVB DIVIDE SHORT INTEGERS Divides the con...

Page 319: ...nt into the low order byte i e the byte with the lower address of the destination operand and the remainder into the high order byte The following two statements are performed concurrently low byte DE...

Page 320: ...on and the target label effecting the jump The offset must be in the range of 128 to 127 COUNT COUNT 1 if COUNT 0 then PC PC 8 bit disp end_if DJNZW wreg cadd 11100001 wreg disp NOTE The displacement...

Page 321: ...OP PTRS CNTREG EBMOVI prt2_reg wreg 11100100 wreg prt2_reg NOTES The pointers are autoincre mented during this instruction However CNTREG is decre mented only when the instruc tion is interrupted When...

Page 322: ...es interrupts following the execution of the next statement Interrupt calls cannot occur immediately following this instruction Interrupt Enable PSW 1 1 EI 11111011 PSW Flag Settings Z N C V VT ST EJM...

Page 323: ...T ELDB EXTENDED LOAD BYTE Loads the value of the source byte operand into the destination operand This instruction allows you to move data from anywhere in the 16 Mbyte address space into the lower re...

Page 324: ...e leftmost byte operand into the destination rightmost operand This instruction allows you to move data from the lower register file to anywhere in the 16 Mbyte address space ext indirect DEST SRC ext...

Page 325: ...e to enter idle mode KEY 1 to enter powerdown mode KEY 2 to enter standby mode KEY 3 NU only to execute a reset sequence KEY any value other than 1 or 2 NP or 1 2 or 3 NU The bus controller completes...

Page 326: ...The offset must be in the range of 128 to 127 if specified bit 0 then PC PC 8 bit disp JBC breg bitno cadd 00110bbb breg disp NOTE The displacement disp is sign extended to 24 bits PSW Flag Settings...

Page 327: ...to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 128 to 127 if Z 1 then PC PC 8 bit disp JE cadd 110111...

Page 328: ...set and the zero flag is clear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 t...

Page 329: ...lear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 128 to 127 if C 0 then PC PC...

Page 330: ...l instruction If the sticky bit flag is clear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in...

Page 331: ...ction If the sticky bit flag is set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 1...

Page 332: ...ogram counter the return address onto the stack then adds to the program counter the offset between the end of this instruction and the target label effecting the call The offset must be in the range...

Page 333: ...ds the value of the source byte operand and loads it into the destination word operand low byte DEST SRC high byte DEST 0 DEST SRC LDBZE wreg baop 101011aa baop wreg PSW Flag Settings Z N C V VT ST LJ...

Page 334: ...dress in the range 00H 0FH enables the multiply accumulate function When set bit 3 of the destination address causes the accumulator to be cleared before the results of the multiply are added to the c...

Page 335: ...VT ST MULU 3 operands MULTIPLY WORDS UNSIGNED Multiplies the two source word operands using unsigned arithmetic and stores the 32 bit result into the destination double word operand The sticky bit fla...

Page 336: ...word result into the destination operand The sticky bit flag is undefined after the instruction is executed DEST SRC1 SRC2 DEST SRC1 SRC2 MULUB wreg breg baop 010111aa baop breg wreg PSW Flag Setting...

Page 337: ...ination rightmost operand COUNT 0 do while MSB DEST 0 AND COUNT 31 DEST DEST 2 COUNT COUNT 1 end_while SRC DEST NORML lreg breg 00001111 breg lreg PSW Flag Settings Z N C V VT ST 0 NOT COMPLEMENT WORD...

Page 338: ...B LOGICAL OR BYTES ORs the source byte operand with the destination byte operand and replaces the original destination operand with the result The result has a 1 in each bit position in which either t...

Page 339: ...t occur immediately following this instruction INT_MASK1 WSR SP SP SP 2 PSW INT_MASK SP SP SP 2 POPA 11110101 PSW Flag Settings Z N C V VT ST POPF POP FLAGS Pops the word on top of the stack and place...

Page 340: ...INT_MASK1 WSR INT_MASK1 0 PUSHA 11110100 PSW Flag Settings Z N C V VT ST 0 0 0 0 0 0 PUSHF PUSH FLAGS Pushes the PSW onto the top of the stack then clears it Clearing the PSW disables interrupt servic...

Page 341: ...e offset between the end of this instruction and the target label effecting the call The offset must be in the range of 1024 to 1023 64 Kbyte mode SP SP 2 SP PC PC PC 11 bit disp 1 Mbyte mode SP SP 4...

Page 342: ...unt wreg or SHL wreg breg 00001001 breg wreg PSW Flag Settings Z N C V VT ST SHLB SHIFT BYTE LEFT Shifts the destination byte operand to the left as many times as specified by the count operand The co...

Page 343: ...operand to the right as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 0FH inclusive or as the content of any register 10...

Page 344: ...eration DEST 2 rep resents signed division PSW Flag Settings Z N C V VT ST 0 SHRAB ARITHMETIC RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many times as specified by the count...

Page 345: ...ag In this operation DEST 2 rep resents signed division PSW Flag Settings Z N C V VT ST 0 SHRB LOGICAL RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many times as specified by t...

Page 346: ...g and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents unsigned division PSW Flag Settings Z N C V VT ST 0 0 SJMP SHORT JUMP Adds to the progra...

Page 347: ...BTRACT WORDS Subtracts the source word operand from the destination word operand stores the result in the destination operand and sets the carry flag as the complement of borrow DEST DEST SRC DEST SRC...

Page 348: ...N C V VT ST SUBC SUBTRACT WORDS WITH BORROW Subtracts the source word operand from the destination word operand If the carry flag was clear SUBC subtracts 1 from the result It stores the result in th...

Page 349: ...ump table Like TBASE INDEX can be located in RAM up to FEH without windowing or above FFH with windowing Note that the 16 bit address contained in INDEX is absolute it disregards any windowing that ma...

Page 350: ...tion is intended for use by development tools These tools may not support user application of this instruction PSW Flag Settings Z N C V VT ST XCH EXCHANGE WORD Exchanges the value of the source word...

Page 351: ...a 1 and zeros in all other bit positions DEST DEST XOR SRC DEST SRC XOR wreg waop 100001aa waop wreg PSW Flag Settings Z N C V VT ST 0 0 XORB LOGICAL EXCLUSIVE OR BYTES XORs the source byte operand wi...

Page 352: ...L 0A SHRA 0B XCH Indexed 0C SHRL 0D SHLL 0E SHRAL 0F NORML 10 Reserved 11 CLRB 12 NOTB 13 NEGB 14 XCHB Direct 15 DECB 16 EXTB 17 INCB 18 SHRB 19 SHLB 1A SHRAB 1B XCHB Indexed 1C EST Indirect 1D EST In...

Page 353: ...ops 55 ADDB Immediate 3 ops 56 ADDB Indirect 3 ops 57 ADDB Indexed 3 ops 58 SUBB Direct 3 ops 59 SUBB Immediate 3 ops 5A SUBB Indirect 3 ops 5B SUBB Indexed 3 ops 5C MULUB Direct 3 ops 5D MULUB Immedi...

Page 354: ...ect 2 ops 7B SUBB Indexed 2 ops 7C MULUB Direct 2 ops 7D MULUB Immediate 2 ops 7E MULUB Indirect 2 ops 7F MULUB Indexed 2 ops 80 OR Direct 81 OR Immediate 82 OR Indirect 83 OR Indexed 84 XOR Direct 85...

Page 355: ...t A7 ADDC Indexed A8 SUBC Direct A9 SUBC Immediate AA SUBC Indirect AB SUBC Indexed AC LDBZE Direct AD LDBZE Immediate AE LDBZE Indirect AF LDBZE Indexed B0 LDB Direct B1 LDB Immediate B2 LDB Indirect...

Page 356: ...ndirect CB PUSH Indexed CC POP Direct CD BMOVI CE POP Indirect CF POP Indexed D0 JNST D1 JNH D2 JGT D3 JNC D4 JNVT D5 JNV D4 JNVT D5 JNV D6 JGE D7 JNE D8 JST D9 JH DA JLE DB JC DC JVT DD JV DE JLT DF...

Page 357: ...5 POPA F6 IDLPD F7 TRAP F8 CLRC F9 SETC FA DI FB EI FC CLRVT FD NOP FE DIV DIVB MUL MULB Note 2 FF RST NOTES 1 This opcode is reserved but it does not generate an unimplemented opcode interrupt 2 Sign...

Page 358: ...ops 4 58 4 59 4 5A 5 6 5B SUBC 3 A8 4 A9 3 AA 4 5 AB SUBCB 3 B8 3 B9 3 BA 4 5 BB NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because w...

Page 359: ...0 3 71 3 72 4 5 73 ANDB 3 ops 4 50 4 51 4 52 5 6 53 NEG 2 03 NEGB 2 13 NOT 2 02 NOTB 2 12 OR 3 80 4 81 3 82 4 5 83 ORB 3 90 3 91 3 92 4 5 93 XOR 3 84 4 85 3 86 4 5 87 XORB 3 94 3 95 3 96 4 5 97 Table...

Page 360: ...rs always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte...

Page 361: ...imal Opcodes Continued NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be...

Page 362: ...AP 1 F7 Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word regist...

Page 363: ...s do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indire...

Page 364: ...cimal Opcodes Continued NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can b...

Page 365: ...1 7 10 8 11 ADDC 4 5 6 8 7 9 6 8 7 9 ADDCB 4 4 6 8 7 9 6 8 7 9 CLR 3 CLRB 3 CMP 4 5 6 8 7 9 6 8 7 9 CMPB 4 4 6 8 7 9 6 8 7 9 CMPL 7 DEC 3 DECB 3 EXT 4 EXTB 4 INC 3 INCB 3 SUB 2 ops 4 5 6 8 7 9 6 8 7 9...

Page 366: ...2 16 14 17 MULUB 3 ops 10 10 12 15 13 15 12 16 14 17 Logical Mnemonic Direct Immed Indirect Indexed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem AND 2 ops 4 5 6 8 7 9 6 8 7 9 AND 3 ops 5...

Page 367: ...Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem POP 11 13 15 14 16 14 16 15 17 POPA 18 POPF 10 PUSH 8 9 11 14 12 15 12 15 13 16 PUSHA 18 PUSHF 8 Table A 9 Instruction Execution Times in State Time...

Page 368: ...ndexed Normal Autoinc ELD 6 9 8 11 8 11 ELDB 6 9 8 11 8 11 EST 6 9 8 11 8 11 ESTB 6 9 8 11 8 11 Mnemonic Direct Immed Indirect Indexed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem LD 4 5...

Page 369: ...ode 16 Mnemonic Direct Immed Indirect Indexed Normal Autoinc Short Long LCALL 1 Mbyte mode 64 Kbyte mode 15 11 RET 1 Mbyte mode 64 Kbyte mode 16 11 SCALL 1 Mbyte mode 64 Kbyte mode 15 11 TRAP 1 Mbyte...

Page 370: ...ode 64 Kbyte mode 22 14 SCALL 1 Mbyte mode 64 Kbyte mode 18 13 TRAP 1 Mbyte mode 64 Kbyte mode 25 18 Table A 9 Instruction Execution Times in State Times Continued NOTE The column entitled Reg lists t...

Page 371: ...mp not taken 8 jump taken JST 4 jump not taken 8 jump taken JV 4 jump not taken 8 jump taken JVT 4 jump not taken 8 jump taken Shift Mnemonic Direct NORML 8 1 per shift 9 for 0 shift SHL 6 1 per shift...

Page 372: ...ed Indirect Indexed Normal Autoinc Short Long DPTS 2 EPTS 2 Table A 9 Instruction Execution Times in State Times Continued NOTE The column entitled Reg lists the instruction execution times for access...

Page 373: ......

Page 374: ...B Signal Descriptions...

Page 375: ......

Page 376: ...d they will be added to the datasheets first If your package type is not shown in this appendix refer to the latest datasheet to find the pin locations Table B 1 8XC196NP and 80C196NU Signals Arranged...

Page 377: ...3 2 CS2 P3 3 CS3 VSS P3 4 CS4 P3 5 CS5 P3 6 EXTINT2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S8XC196NP View of component as mounted on PC board 1 2 3 4 5 6 7 8 9 10 1...

Page 378: ...P3 1 CS1 P3 2 CS2 P3 3 CS3 VSS P3 4 CS4 P3 5 CS5 P3 6 EXTINT2 NC P3 7 EXTINT3 P1 0 EPA0 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S8XC196NP View of...

Page 379: ...S1 P3 2 CS2 P3 3 CS3 VSS P3 4 CS4 P3 5 CS5 P3 6 EXTINT2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S8XC196NU View of component as mounted on PC board 1 2 3 4 5 6 7 8 9...

Page 380: ...CS0 P3 1 CS1 P3 2 CS2 P3 3 CS3 VSS P3 4 CS4 P3 5 CS5 P3 6 EXTINT2 NC P3 7 EXTINT3 P1 0 EPA0 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S8XC196NU View...

Page 381: ...16 I O Address Lines 16 19 These address lines provide address bits 16 19 during the entire external memory cycle supporting extended addressing of the 1 Mbyte address space NOTE Internally there are...

Page 382: ...ermines whether this pin functions as BHE or WRH CCR0 2 1 selects BHE CCR0 2 0 selects WRH BREQ O Bus Request This active low output signal is asserted during a hold cycle when the bus controller has...

Page 383: ...I O Extended Addressing Port On the 8XC196NP this is a 4 bit bidirectional memory mapped I O port On the 8XC196NU this is a 4 bit bidirectional standard I O port EPORT 3 0 are multiplexed with A19 16...

Page 384: ...on circuit emulation ONCE mode This mode puts all pins into a high impedance state thereby isolating the device from other components in the system The value of ONCE is latched when the RESET pin goe...

Page 385: ...memory reads READY I Ready Input This active high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated in...

Page 386: ...xed with P2 1 T1CLK I Timer 1 External Clock External clock for timer 1 Timer 1 increments or decrements on both rising and falling edges of T1CLK Also used in conjunction with T1DIR for quadrature co...

Page 387: ...BHE CCR0 2 0 selects WRH WRL O Write Low During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writes During 8 bit bus cycles WRL is asserted for all write op...

Page 388: ...96NP and 80C196NU Pin Status Port Pins Multiplexed With During RESET Active Upon RESET Inactive Note 11 Idle Power down NP NU and Standby NU only Hold Bus Idle P1 3 0 EPA3 0 WK1 WK1 Note 1 Note 1 Note...

Page 389: ...ogrammed If Px_MODE y 1 then as specified by the associ ated peripheral 2 If P2_MODE 7 0 then port is as programmed If P2_MODE 7 1 then 1 3 Used as chip select If HLDA 0 then WK1 If HLDA 1 then LoZ1 U...

Page 390: ...C Registers...

Page 391: ......

Page 392: ...gisters are ar ranged alphabetically by mnemonic Table C 1 Modules and Related Registers Chip Configuration Chip select Units x 0 5 CPU x 0 2 EPA x 0 3 CCR0 ADDRCOMx ACC_0x 80C196NU EPA_MASK CCR1 ADDR...

Page 393: ...K2 Address Mask 2 1F52H XXXX 1111 1111 1111 ADDRMSK3 Address Mask 3 1F5AH XXXX 1111 1111 1111 ADDRMSK4 Address Mask 4 1F62H XXXX 1111 1111 1111 ADDRMSK5 Address Mask 5 1F6AH XXXX 1111 1111 1111 BUSCON...

Page 394: ...tput 1FD4H 1111 1111 P2_DIR Port 2 I O Direction 1FD3H 1111 1111 P2_MODE Port 2 Mode 1FD1H 1000 0000 P2_PIN Port 2 Pin Input 1FD7H XXXX XXXX P2_REG Port 2 Data Output 1FD5H 1111 1111 P3_DIR Port 3 I O...

Page 395: ...us 1FB9H 0000 1011 T1CONTROL Timer 1 Control 1F90H 0000 0000 T2CONTROL Timer 2 Control 1F94H 0000 0000 TIMER1 Timer 1 Value 1F92H 0000 0000 0000 0000 TIMER2 Timer 2 Value 1F96H 0000 0000 0000 0000 WSR...

Page 396: ...Value word 1 high byte 7 0 ACC_02 Accumulator Value word 1 low byte 15 8 Accumulator Value word 0 high byte 7 0 ACC_00 Accumulator Value word 0 low byte Bit Number Function 15 0 Accumulator Value You...

Page 397: ...ltiplication operation is not allowed to overflow or underflow For unsigned multiplication this bit is ignored 5 3 Reserved for compatibility with future devices write zeros to these bits 2 STOVF Stic...

Page 398: ...and sets the STSAT flag Positive saturation changes the accumulator value to 7FFFFFFFH negative saturation changes the accumulator value to 80000000H Accumulation proceeds normally after saturation wh...

Page 399: ...ASE14 BASE13 BASE12 BASE11 BASE10 BASE9 BASE8 Bit Number Bit Mnemonic Function 15 12 Reserved for compatibility with future devices write zeros to these bits 11 0 BASE19 8 Base Address Bits These bits...

Page 400: ...most significant bits of MASK19 8 in the address mask register 15 8 MASK19 MASK18 MASK17 MASK16 7 0 MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8 Bit Number Bit Mnemonic Function 15 12 Reserv...

Page 401: ...to the address range assigned to chip select output x 0 multiplexed 1 demultiplexed 6 BW16 Bus Width This bit specifies the bus width for all external accesses to the address range assigned to chip s...

Page 402: ...or external bus cycles 0 write strobe mode the BHE WRH pin operates as WRH and the WR WRL pin operates as WRL 1 standard write control mode the BHE WRH pin operates as BHE and the WR WRL pin operates...

Page 403: ...t write cycle following a read cycle See Deferred Bus cycle Mode 80C196NU Only on page 13 40 0 deferred bus cycle mode disabled 1 deferred bus cycle mode enabled 4 3 1 To guarantee device operation wr...

Page 404: ...tput period by enabling or disabling the clock prescaler divide by two on the three pulse width modulators PWM0 PWM2 0 disable PWM output period is 512 state times 1 enable PWM output period is 1024 s...

Page 405: ...ut Open drain outputs require external pull ups Any pin that is configured for its extended address function is forced to the complementary output mode except during reset hold idle powerdown and stan...

Page 406: ...pin or as an extended address signal Setting a bit configures a pin as an extended address signal clearing a bit configures a pin as a standard I O port pin 7 0 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mne...

Page 407: ...ded port input EP_PIN register reflects the current state of the corresponding pin regardless of the pin configuration 7 0 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 4 Reserved always writ...

Page 408: ...figured as an extended address signal EP_MODE x set 80C196NU Only For nonextended data accesses the 80C196NU forces the page address to 00H You cannot change pages by modifying EP_REG 7 0 PIN3 PIN2 PI...

Page 409: ...0 7 0 OVR3 OVR2 OVR1 OVR0 Bit Number Bit Mnemonic Function 7 5 3 1 Reserved for compatibility with future devices write zeros to these bits 6 4 2 0 OVR3 OVR2 OVR1 OVR0 Setting this bit enables the co...

Page 410: ...are multiplexed to share one bit OVR0_1 in the INT_PEND1 register Similarly OVR2 and OVR3 are multiplexed to share another bit OVR2_3 in the INT_PEND1 register 7 0 OVR3 OVR2 OVR1 OVR0 Bit Number Func...

Page 411: ...annel 0 shares output pin EPA1 with EPA capture compare channel 1 When the remap feature of EPA3 is enabled EPA capture compare channel 2 shares output pin EPA3 with EPA capture compare channel 3 0 re...

Page 412: ...ister EPAx_TIME matches the reference timer rather than only upon the first time match 0 compare function is disabled after a single event 1 compare function always enabled 2 Reserved always write as...

Page 413: ...me register EPAx_TIME and its buffer are both full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the b...

Page 414: ...C 23 REGISTERS EPAx_CON Table C 8 EPAx_CON Addresses and Reset Values Register Address Reset Value EPA0_CON 1F80H 00H EPA1_CON 1F84H 0000H EPA2_CON 1F88H 00H EPA3_CON 1F8CH 0000H...

Page 415: ...re event when the reference timer matches the value in EPAx_TIME EPAx_TIME is not buffered for compare mode 15 8 EPA Timer Value high byte 7 0 EPA Timer Value low byte Bit Number Function 15 0 EPA Tim...

Page 416: ...ack and POPF or POPA restores it 7 0 EPA0 RI TI EXTINT1 EXTINT0 OVRTM2 OVRTM1 Bit Number Function 7 3 1 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are...

Page 417: ...errupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH EXTINT3 EXTINT3 pin FF203CH EXTINT2 EXTINT2 pin FF203AH OVR2_3 EP...

Page 418: ...TINT0 OVRTM2 OVRTM1 Bit Number Function 7 3 1 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the corresponding interrupt...

Page 419: ...g transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH EXTINT3 EXTINT3 pin FF...

Page 420: ...State 02H FFFFH The two byte ones register ONES_REG is always equal to FFFFH It is useful as a fixed source of all ones for comparison operations 15 8 One high byte 7 0 One low byte Bit Number Functio...

Page 421: ...en drain output configuration requires an external pull up A high impedance input configuration requires that the corresponding bit in Px_REG be set 7 0 x 1 3 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 7...

Page 422: ...C 12 lists the special function signals for each pin Table C 11 Px_MODE Addresses and Reset Values Register Address Reset Value P1_MODE 1FD0H 00H P2_MODE 1FD1H 80H P3_MODE 1FD8H 01H P4_MODE 1FD9H 00H...

Page 423: ...nding pin regardless of the pin configuration 7 0 x 1 3 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 7 0 x 4 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 0 PIN7 0 Port x Pin y Input Value This bi...

Page 424: ...il it is switched back to its standard I O function This feature allows software to configure a pin as standard I O clear Px_MODE y initialize or overwrite the pin value then configure the pin as a sp...

Page 425: ...his ensures that the zero flag will reflect the result of the entire operation not just the last calculation For example if the result of adding together the lower words of two double words is zero th...

Page 426: ...K and INT_MASK1 individually enable or disable the interrupts The EI instruction sets this bit DI clears it 1 enable interrupt servicing 0 disable interrupt servicing 0 ST Sticky Bit Flag This flag is...

Page 427: ...evices write zero to this bit 14 3 1 0 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations are as follows Bit Mnemonic Interrup...

Page 428: ...request an end of PTS interrupt for the corresponding interrupt through its standard interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector EXTI...

Page 429: ...ister causes the PWM to have its maximum duty cycle 99 6 duty cycle 7 0 PWM Duty Cycle Bit Number Function 7 0 PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register...

Page 430: ...held in the receive shift register until the last data bit is received then the data byte is loaded into SBUF_RX If data in the shift register is loaded into SBUF_RX before the previous byte is read t...

Page 431: ...ntains data that is ready for transmission In modes 1 2 and 3 writing to SBUF_TX starts a transmission In mode 0 writing to SBUF_TX starts a transmission only if the receiver is disabled SP_CON 3 0 7...

Page 432: ...emented before a PUSH and incremented after a POP so the stack pointer should be initialized to two bytes in 64 Kbyte mode or four bytes in 1 Mbyte mode above the highest stack location If stack opera...

Page 433: ...nd 0002H for receptions 15 8 CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0 Bit Number Bit Mnemonic Function 15 CLKSRC Serial Port Clock Source This bit determines whether...

Page 434: ...00 8A2BH 8144H 0 0 16 2400 9457H 828AH 0 0 1200 A8AFH 8515H 0 0 300 Note 2 9457H Note 2 0 NOTES 1 Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud r...

Page 435: ...his bit is cleared after each transmission so it must be set before SBUF_TX is written When SP_CON 2 is set this bit takes on the even parity value 3 REN Receive Enable Setting this bit enables the re...

Page 436: ...bit is sampled Reading SP_STATUS clears this bit This bit need not be clear for the serial port to receive data 5 TI Transmit Interrupt This bit is set at the beginning of the stop bit transmission R...

Page 437: ...ine the timer clocking source and direction control source M2 M1 M0 Clock Source Direction Source 0 0 0 f 4 UD bit T1CONTROL 6 X 0 1 T1CLK pin UD bit T1CONTROL 6 0 1 0 f 4 T1DIR pin 0 1 1 T1CLK pin T1...

Page 438: ...tion source M2 M1 M0 Clock Source Direction Source 0 0 0 f 4 UD bit T2CONTROL 6 X 0 1 T2CLK pin UD bit T2CONTROL 6 0 1 0 f 4 T2DIR pin 0 1 1 T2CLK pin T2DIR pin 1 0 0 timer 1 overflow UD bit T2CONTROL...

Page 439: ...ten allowing timer x to be initialized to a value other than zero 15 8 Timer Value high byte 7 0 Timer Value low byte Bit Number Function 15 0 Timer Read the current timer x value from this register o...

Page 440: ...on page 5 15 or Table 5 9 on page 5 15 Table C 18 WSR Settings and Direct Addresses for Windowable SFRs Register Mnemonic Memory Location 32 byte Windows 00E0 00FFH 64 byte Windows 00C0 00FFH 128 byt...

Page 441: ...7CH 00E2H 3EH 00C2H 1FH 0082H EPA1_TIME 1F86H 7CH 00E6H 3EH 00C6H 1FH 0086H EPA2_TIME 1F8AH 7CH 00EAH 3EH 00CAH 1FH 008AH EPA3_TIME 1F8EH 7CH 00EEH 3EH 00CEH 1FH 008EH P1_DIR 1FD2H 7EH 00F2H 3FH 00D2...

Page 442: ...3EH 00FAH 1FH 00BAH SP_BAUD 1FBCH 7DH 00FCH 3EH 00FCH 1FH 00BCH SP_CON 1FBBH 7DH 00FBH 3EH 00FBH 1FH 00BBH SP_STATUS 1FB9H 7DH 00F9H 3EH 00F9H 1FH 00B9H T1CONTROL 1F90H 7CH 00F0H 3EH 00D0H 1FH 0090H T...

Page 443: ...s for Windowable SFRs Register Mnemonic Memory Location 32 byte Windows 0060 007FH 64 byte Windows 0040 007FH WSR1 Direct Address WSR1 Direct Address ADDRCOM0 1F40H 7AH 0060H 3DH 0040H ADDRCOM1 1F48H...

Page 444: ...004EH P1_DIR 1FD2H 7EH 0072H 3FH 0052H P1_MODE 1FD0H 7EH 0070H 3FH 0050H P1_PIN 1FD6H 7EH 0076H 3FH 0056H P1_REG 1FD4H 7EH 0074H 3FH 0054H P2_DIR 1FD3H 7EH 0073H 3FH 0053H P2_MODE 1FD1H 7EH 0071H 3FH...

Page 445: ...3EH 007CH SP_CON 1FBBH 7DH 007BH 3EH 007BH SP_STATUS 1FB9H 7DH 0079H 3EH 0079H T1CONTROL 1F90H 7CH 0070H 3EH 0050H T2CONTROL 1F94H 7CH 0074H 3EH 0054H TIMER1 1F92H 7CH 0072H 3EH 0052H TIMER2 1F96H 7C...

Page 446: ...0000H The two byte zero register ZERO_REG is always equal to zero It is useful as a fixed source of the constant zero for comparisons and calculations 15 8 Zero high byte 7 0 Zero low byte Bit Number...

Page 447: ......

Page 448: ...Glossary...

Page 449: ......

Page 450: ...that processes arithmetic and logical operations assert The act of making a signal active enabled The polarity high or low is defined by the signal name Active low signals are designated by a pound s...

Page 451: ...or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results in an n type material...

Page 452: ...atency The time it takes the microcontroller to assert HLDA after an external device asserts HOLD input leakage Current leakage from an input pin to power or ground integer Any member of the set consi...

Page 453: ...dress and also uses AD15 0 for data See also demultiplexed bus multiply accumulate An operation performed by the 8XC196NU s enhanced multiplication instructions The result of the operation is stored i...

Page 454: ...e to attain its maximum operating frequency with an external clock whose frequency is either equal to one half or one fourth that maximum frequency or with an external oscillator whose frequency is ei...

Page 455: ...terrupt Any maskable interrupt that is assigned to the PTS for interrupt processing PTS mode A microcoded response that enables the PTS to complete a specific task quickly These tasks include transfer...

Page 456: ...ing powerdown mode saturation mode Saturation occurs when the result of two positive numbers generates a negative sign bit or the result of two negative numbers generates a positive sign bit Saturatio...

Page 457: ...te at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time t Lowercase t represents the period of the internal clock For the NP t is the...

Page 458: ...Index...

Page 459: ......

Page 460: ...Address lines extended See A19 16 EPORT Address space 2 6 5 1 16 Mbyte address space 5 1 1 Mbyte address space 5 1 5 25 accessing pages 01H 0FH 7 18 external 5 1 internal 5 2 partitions 5 3 5 12 regi...

Page 461: ...13 33 and interrupts 13 33 and reset See reset disabling 13 32 enabling 13 32 hold latency 13 32 regaining bus control 13 33 signals 13 30 See also port 2 BREQ HLDA HOLD software protection 13 32 tim...

Page 462: ...A 13 A 52 A 54 A 61 DIVU instruction A 3 A 14 A 49 A 54 A 61 DIVUB instruction A 3 A 14 A 50 A 54 A 61 DJNZ instruction A 2 A 5 A 14 A 51 A 58 A 66 DJNZW instruction A 2 A 5 A 15 A 51 A 58 A 66 Docume...

Page 463: ...7 1 pins 7 11 reset 7 14 SFRs 7 12 structure 7 15 EPORT 3 0 B 8 EPTS instruction 6 10 A 3 A 18 A 52 A 59 A 67 ESD protection 7 4 7 14 11 5 EST instruction 4 6 A 3 A 19 A 47 A 56 A 63 ESTB instruction...

Page 464: ...1 Mbyte mode 64 Kbyte mode Instruction set 4 1 additions 4 5 4 6 and PSW flags A 5 code execution 2 4 2 5 conventions 1 3 differences 4 5 execution times A 60 A 61 lengths A 53 A 60 opcode map A 2 A 3...

Page 465: ...ample of 1 Mbyte mode 5 32 Example of 64 Kbyte mode 5 28 5 30 Memory external 13 1 13 45 interface signals 13 2 Memory reserved 5 6 5 7 Microcode engine 2 3 Miller effect 11 7 Mode 0 SIO 8 4 8 5 Mode...

Page 466: ...H 5 3 5 22 page 0FH 5 2 page FFH 5 2 5 25 accessing 5 22 page number and EPORT 5 23 Parameters passing to subroutines 4 13 Parity 8 6 8 7 PC program counter 2 4 5 23 extended 2 6 5 23 5 25 7 13 master...

Page 467: ...7 6 10 6 18 PTSSRV 6 7 6 18 Pulse width modulator See PWM PUSH instruction A 3 A 34 A 51 A 55 A 62 PUSHA instruction A 2 A 35 A 52 A 55 A 62 PUSHF instruction A 2 A 35 A 52 A 55 A 62 PWM 6 26 9 1 and...

Page 468: ...BUF_TX 8 3 SP_BAUD 8 3 8 11 8 12 8 13 SP_CON 8 3 8 9 SP_STATUS 8 4 8 14 T1CONTROL 10 4 T2CONTROL 10 4 TIMER1 10 4 TIMER2 10 4 using 4 12 WSR 6 14 WSR1 5 15 REMAP bit See ROM internal 83C196NP Reserved...

Page 469: ...mode 1 8 5 8 6 mode 2 8 5 8 6 8 7 mode 3 8 5 8 6 8 7 multiprocessor communications 8 7 8 8 overrun error 8 14 programming 8 8 receive interrupt RI flag 8 15 receiver 8 1 selecting baud rate 8 8 8 12 S...

Page 470: ...ait states 13 5 13 26 13 30 for CCB0 fetch 13 17 Window selection register See WSR WSR1 Windows 5 1 5 13 5 21 addressing 5 18 and addressing modes 5 21 base address 5 16 5 18 examples 5 18 5 21 nonwin...

Page 471: ...6NP 80C196NU USER S MANUAL Index 12 and SIO baud rate 8 12 8 13 hardware connections 11 6 11 7 XTAL2 11 2 B 12 hardware connections 11 6 11 7 Y y defined 1 4 Z Zero Z flag A 4 A 5 A 22 A 23 A 24 A 25...

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