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A-9
INSTRUCTION SET REFERENCE
ANDB
(3 operands)
LOGICAL AND BYTES. ANDs the two source
byte operands and stores the result into the
destination operand. The result has ones in
only the bit positions in which both operands
had a “1” and zeros in all other bit positions.
(DEST)
←
(SRC1) AND (SRC2)
DEST, SRC1, SRC2
ANDB
Dbreg, Sbreg, baop
(010100aa) (baop) (Sbreg) (Dbreg)
PSW Flag Settings
Z
N
C
V
VT
ST
✓
✓
0
0
—
—
BMOV
BLOCK MOVE. Moves a block of word data
from one location in memory to another. The
source and destination addresses are
calculated using the indirect with autoin-
crement addressing mode. A long register
(PTRS) addresses the source and destination
pointers, which are stored in adjacent word
registers. The source pointer (SRCPTR) is
the low word and the destination pointer
(DSTPTR) is the high word of PTRS. A word
register (CNTREG) specifies the number of
transfers. The blocks of data can be located
anywhere in page 00H of register RAM, but
should not overlap. Because the source
(SRCPTR) and destination (DSTPTR)
pointers are 16 bits wide, this instruction uses
nonextended data moves. It cannot operate
across page boundaries. For example,
SRCPTR cannot point to a location on page
05 while DSTPTR points to page 00.
SRCPTR and DSTPTR will operate from the
page defined by EP_REG. EP_REG should
be set to 00H to select page 00H (see
“Accessing Data” on page 5-23). (The
80C196NU forces EP_REG to 00H.)
COUNT
←
(CNTREG)
LOOP: SRCPTR
←
(PTRS)
DSTPTR
←
(PTRS + 2)
(DSTPTR)
←
(SRCPTR)
(PTRS)
←
2
(PTRS + 2)
←
2
COUNT
←
COUNT – 1
if COUNT
≠
0 then
go to LOOP
PTRS, CNTREG
BMOV
lreg, wreg
(11000001) (wreg) (lreg)
NOTE:
The pointers are autoincre-
mented during this instruction.
However, CNTREG is not decre-
mented. Therefore, it is easy to
unintentionally create a long,
uninterruptible operation with the
BMOV instruction. Use the
BMOVI instruction for an interrupt-
ible operation.
PSW Flag Settings
Z
N
C
V
VT
ST
—
—
—
—
—
—
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
Summary of Contents for 80C196NU
Page 1: ...8XC196NP 80C196NU Microcontroller User s Manual...
Page 2: ...8XC196NP 80C196NU Microcontroller User s Manual August 1995 Order Number 272479 002...
Page 18: ...1 Guide to This Manual...
Page 19: ......
Page 31: ......
Page 32: ...2 Architectural Overview...
Page 33: ......
Page 48: ...3 Advanced Math Features...
Page 49: ......
Page 56: ...4 Programming Considerations...
Page 57: ......
Page 72: ...5 Memory Partitions...
Page 73: ......
Page 106: ...6 Standard and PTS Interrupts...
Page 107: ......
Page 144: ...7 I O Ports...
Page 145: ......
Page 165: ......
Page 166: ...8 Serial I O SIO Port...
Page 167: ......
Page 183: ......
Page 184: ...9 Pulse width Modulator...
Page 185: ......
Page 196: ...10 Event Processor Array EPA...
Page 197: ......
Page 225: ......
Page 226: ...11 Minimum Hardware Considerations...
Page 227: ......
Page 239: ......
Page 240: ...12 Special Operating Modes...
Page 241: ......
Page 255: ......
Page 256: ...13 Interfacing with External Memory...
Page 257: ......
Page 303: ......
Page 304: ...A Instruction Set Reference...
Page 305: ......
Page 373: ......
Page 374: ...B Signal Descriptions...
Page 375: ......
Page 390: ...C Registers...
Page 391: ......
Page 447: ......
Page 448: ...Glossary...
Page 449: ......
Page 458: ...Index...
Page 459: ......