80960MC
6
Figure 3. Multiple Register Sets Are Stored On-Chip
REGISTER
CACHE
ONE OF FOUR
LOCAL
REGISTER SETS
LOCAL REGISTER SET
R
15
R
0
31
0
1.1.7
Memory Management and Protection
The 80960MC is ideal for multitasking applications
that require software protection and a large address
space. To ensure the highest level of performance
possible, the memory management unit (MMU) and
translation look-aside buffer (TLB) are contained on-
chip.
The 80960MC supports a conventional form of
demand-paged virtual memory in which the address
space is divided into 4-Kbyte pages. Studies indicate
that a 4-Kbyte page is the optimum size for a broad
range of applications.
Each page table entry includes a 2-bit page rights
field that specifies whether the page is a no-access,
read-only, or read-write page. This field is inter-
preted differently depending on whether the current
task (process) is executing in user or supervisor
mode, as shown below:
Rights User
Supervisor
00
No Access
Read-Only
01
No Access
Read-Write
10
Read-Only
Read-Write
11
Read-Write
Read-Write
1.1.8
Floating-Point Arithmetic
In the 80960MC, floating-point arithmetic is an
integral part of the architecture. Having the floating-
point unit integrated on-chip provides two advan-
tages. First, it improves the performance of the chip
for floating-point applications, since no additional
bus overhead is associated with floating-point calcu-
lations, thereby leaving more time for other bus oper-
ations such as I/O. Second, the cost of using
floating-point operations is reduced because a
separate coprocessor chip is not required.
The 80960MC floating-point (real-number) data
types include single-precision (32-bit), double-preci-
sion (64-bit) and extended precision (80-bit) floating-
point numbers. Any registers may be used to
execute floating-point operations.
The processor provides hardware support for both
mandatory and recommended portions of IEEE
Standard 754 for floating-point arithmetic, including
all arithmetic, exponential, logarithmic and other
transcendental functions.
Table 3
shows execution
times for some representative instructions.
