Intel 80960HA Datasheet Download

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Datasheet

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Summary of Contents for 80960HA

Page 1: ...ciative Data Cache 2 Kbyte General Purpose RAM Separate 128 Bit Internal Paths For Instructions Data 3 3 V Supply Voltage 5 V Tolerant Inputs TTL Compatible Outputs Guarded Memory Unit Provides Memory...

Page 2: ...Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of docu...

Page 3: ...Adhesives 34 3 5 PowerQuad4 Plastic Package 34 3 6 Stepping Register Information 34 3 7 Sources for Accessories 36 4 0 Electrical Specifications 37 4 1 Absolute Maximum Ratings 37 4 2 Operating Condit...

Page 4: ...est with Wait States 59 35 Burst Non Pipelined Read Request without Wait States 32 Bit Bus 60 36 Burst Non Pipelined Read Request with Wait States 32 Bit Bus 61 37 Burst Non Pipelined Write Request wi...

Page 5: ...Order 27 11 80960Hx PQ4 Pinout Pin Number Order 29 13 80960Hx 168 Pin PGA Package Thermal Characteristics 32 12 Maximum TA at Various Airflows in C PGA Package Only 32 15 80960Hx 208 Pin PQ4 Package...

Page 6: ...e Internal Bandwidth 80 MHz In Section 3 0 Package Information on page 14 Added paragraph two and Table 5 80960HA HD HT Package Types and Speeds on page 14 In Table 7 80960Hx Processor Family Pin Desc...

Page 7: ...fications for 3 3 V and 5 V Modified TOV2 TOH2 and TTVEL to reflect specific 80960HA 80960HD and 80960HT values In Figure 23 ICC Active Power Supply vs Frequency on page 51 Changed 5 to 0 on the CLKIN...

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Page 9: ...scheduler that allows the processor to sustain a throughput of two instructions every core clock with a peak performance of three instructions per clock The 80960Hx series comprises three processors...

Page 10: ...ously issues these instructions to parallel processing units The various processing units are then able to independently access instruction operands in parallel from a common register set Local Regist...

Page 11: ...set stack frame cache allows the processor to rapidly allocate and deallocate local registers All of the on chip RAM sustains a 4 word 128 bit access every clock cycle 2 2 4 Priority Interrupt Control...

Page 12: ...Error The processor uses only one read bus transaction to signal the fail code message the address of the bus transaction is the fail code itself The fail code is of the form 0xfeffffnn bits 6 to 0 co...

Page 13: ...Span Over Bit Extract Modify Scan Byte for Equal Byte Swap2 Comparison Branch Call Return Fault Compare Conditional Compare Compare and Increment Compare and Decrement Compare Byte2 Compare Short2 Te...

Page 14: ...208 pin PowerQuad2 PQ4 devices are specified for operation at VCC 3 3 V 0 15 V over a case temperature range of 0 C to 85 C Table 5 80960HA HD HT Package Types and Speeds Package Name Device Core Spee...

Page 15: ...hold times relative to CLKIN to ensure proper operation of the processor S L Synchronous level sensitive input This input must meet the setup and hold times relative to CLKIN to ensure proper operati...

Page 16: ...ssor write cycle and is checked for a processor read cycle Parity checking and polarity are programmable Parity generation checking is only performed for the size of the data accessed PCHK O H Q B Q R...

Page 17: ...e internal wait state generator reaches zero BLAST remains active as long as wait states are inserted through the READY pin BLAST becomes inactive after the final data transfer in a bus cycle DT R O H...

Page 18: ...0 BUS STALL indicates that the processor has stalled pending the result of a request in the bus controller When BSTALL is asserted the processor must regain bus ownership to continue processing i e it...

Page 19: ...t in use TCK I TEST CLOCK provides the clocking function for IEEE 1149 1 Boundary Scan testing TDI I TEST DATA INPUT is the serial input pin for IEEE 1149 1 Boundary Scan testing TDI uses an internal...

Page 20: ...D14 VCC D18 D20 D23 D27 D29 NC D0 VCC VSS VSS VSS VSS VSS VSS VCC D22 D31 READY D26 D28 BTERM HOLDA D30 HOLD BE3 VCC ADS BE2 VSS VCC BE1 VSS VCC BLAST VSS BE0 DEN VSS VCC W R VSS VCC DT R A29 LOCK SUP...

Page 21: ...STALL A28 A30 BREQ D C D3 D1 ONCE VSS VCC5 VCC VSS VSS VSS VSS VSS CLKIN VCC VSS BOFF STEST DP1 DP3 TCK TMS VCC PCHK VCC VCCPLL VCC NC NC VCC VSS FAIL DP0 DP2 VOLDET TRST TDI TDO NC NC CT0 CT2 CT3 CT1...

Page 22: ...D22 P3 PCHK B8 A11 K17 BTERM R4 D23 Q2 READY S3 A12 L17 CLKIN C13 D24 R1 RESET A16 A13 L16 CT0 A11 D25 S1 STEST B2 A14 M17 CT1 A12 D26 Q3 SUP Q12 A15 N17 CT2 A13 D27 R2 TCK B5 A16 N16 CT3 A14 D28 Q4 T...

Page 23: ...N3 VSS C8 VSS K15 XINT1 A15 VCC N15 VSS C9 VSS L3 XINT2 A17 VCC Q6 VSS C10 VSS L15 XINT3 B16 VCC R7 VSS C11 VSS M3 XINT4 C15 VCC R8 VSS C12 VSS M15 XINT5 B17 VCC R10 VSS F15 VSS Q7 XINT6 C16 VCC R11 V...

Page 24: ...A12 A10 NC C6 VCC G1 D9 M1 D16 A11 CT0 C7 VSS G2 VCC M2 VCC A12 CT1 C8 VSS G3 VSS M3 VSS A13 CT2 C9 VSS G15 VSS M15 VSS A14 CT3 C10 VSS G16 A7 M16 VCC A15 XINT1 C11 VSS G17 A8 M17 A14 A16 RESET C12 VS...

Page 25: ...10 W R Q9 VSS R4 BTERM R16 A23 S11 DT R Q10 VSS R5 HOLD R17 A22 S12 WAIT Q11 VSS R6 ADS S1 D25 S13 D C Q12 SUP R7 VCC S2 D29 S14 LOCK Q13 A30 R8 VCC S3 READY S15 A31 Q14 A28 R9 BE0 S4 HOLDA S16 A27 Q1...

Page 26: ...BE2 VSS VCC BE1 BE0 BLAST DEN VSS VCC W R DT R WAIT BSTALL VCC VSS VSS VCC D C SUP VSS LOCK BREQ VCC VCC VSS V SS V SS V CC V CC V SS A2 A3 V CC V SS A4 A5 A6 A7 V CC V SS A8 A9 A10 A11 V CC V SS A12...

Page 27: ...54 TMS 192 A11 138 CLKIN 175 D25 55 TRST 193 A12 135 CT0 183 D26 56 VCC 1 A13 134 CT1 182 D27 57 VCC 4 A14 133 CT2 181 D28 61 VCC 9 A15 132 CT3 180 D29 62 VCC 11 A16 127 D C 96 D30 63 VCC 17 A17 126 D...

Page 28: ...VSS 200 VCC 137 VSS 8 VSS 114 VSS 205 VCC 143 VSS 16 VSS 116 W R 88 VCC 149 VSS 18 VSS 122 WAIT 90 VCC 153 VSS 24 VSS 129 XINT0 169 VCC 154 VSS 30 VSS 130 XINT1 168 VCC 158 VSS 32 VSS 136 XINT2 167 V...

Page 29: ...LOCK 10 BOFF 40 D17 70 VSS 100 BREQ 11 VCC 41 D18 71 VCC 101 VCC 12 D0 42 D19 72 HOLDA 102 VCC 13 D1 43 VSS 73 VSS 103 VSS 14 D2 44 VCC 74 VCC 104 A31 15 D3 45 D20 75 VSS 105 A30 16 VSS 46 VCC 76 VCC...

Page 30: ...196 VCC 131 VCC 153 VCC 175 CLKIN 197 VCC5 132 A15 154 VCC 176 VCC 198 VSS 133 A14 155 VSS 177 VCCPLL 199 VCC 134 A13 156 VSS 178 VSS 200 VSS 135 A12 157 VSS 179 VCC 201 VCC 136 VSS 158 VCC 180 CT3 2...

Page 31: ...perature is calculated from CA thermal resistance from case to ambient using Equation 1 Equation 1 Calculation of Ambient Temperature TA Table 12 shows the maximum TA allowable without exceeding TC at...

Page 32: ...X Bus Clock TA with Heatsink 20 25 53 45 63 58 71 67 73 70 76 73 76 73 TA without Heatsink 20 25 43 33 51 42 58 51 63 58 66 61 68 64 0 285 high unidirectional heatsink AI alloy 6061 50 mil fin width 1...

Page 33: ...Core 3X Bus Clock TA with Heatsink 20 25 58 51 68 64 73 70 73 70 76 73 76 73 TA without Heatsink 20 25 56 48 61 55 66 61 66 61 68 64 68 64 0 285 high unidirectional heatsink AI alloy 6061 50 mil fin w...

Page 34: ...of the 80960Hx to operate with the same 0 C to 85 C temperature specifications as the more expensive ceramic PGA package The PQ4 package integrates a copper heat sink within the package to dissipate...

Page 35: ...el See Table 17 Indicates member within a series and specific model information Manufacturer ID 000 0000 1001 Indicates Intel Manufacturer ID assigned by IEEE Table 17 80960Hx Device ID Model Types De...

Page 36: ...oducts 6801 River Place Blvd MS 130 3N 29 Austin TX 78726 9000 800 328 0411 FAX 800 932 9373 Concept Mfg Inc Decoupling Sockets 400 Walnut St Suite 609 Redwood City CA 94063 415 365 1162 FAX 415 365 1...

Page 37: ...aximum Rating Storage Temperature 65 C to 150 C Case Temperature Under Bias 65 C to 110 C Supply Voltage with respect to VSS 0 5 V to 4 6 V Voltage on VCC5 with respect to VSS 0 5 V to 6 5 V Voltage o...

Page 38: ...each pin tied high When READY or HOLD are not used the unused input should be connected to ground N C pins must always remain unconnected 4 4 VCC5 Pin Requirements VDIFF In mixed voltage systems that...

Page 39: ...LL and VCC pins are driven by separate power supplies or voltage regulators Applications that use one power supply for VCCPLL and VCC are not typically at risk Verify that your application does not al...

Page 40: ...H Output High Voltage 2 4 VCC 0 2 V V IOH 3 mA IOH 100 A ILI Input Leakage Current Non Test Inputs TDI TMS TRST and ONCE 1 1 110 A A 0 VIN VCC VIN 0 V ILO Output Leakage Current Non Test Outputs TDO p...

Page 41: ...Figure 8 AC Test Load on page 45 Input signals rise to VCC and fall to VSS 5 ICC Active Power Supply value is provided for selecting your system s power supply It is measured using one of the worst c...

Page 42: ...ynchronous Outputs1 2 3 6 TOV1 TOH1 Output Valid Delay and Output Hold for all outputs except DT R BLAST and BREQ for 3 3 V and 5 V inputs and I Os 1 5 9 5 ns TOV2 TOH2 Output Valid Delay and Output H...

Page 43: ...ing to WAIT Rising 4 N T 4 N T ns 4 10 TNHQX Output Data Hold after WAIT Rising 5 N 1 T 5 N 1 T ns 5 10 TEHTV DT R Hold after DEN High T 2 5 Infinite ns 10 TTVEL DT R Valid to DEN Falling 80960HA 8096...

Page 44: ...ns are synchronized internally by the 80960Hx They have no required setup or hold times for proper operation These pins are sampled by the interrupt controller every clock and must be active for at le...

Page 45: ...oad shown in Figure 8 Figure 25 Output Delay or Hold vs Load Capacitance on page 52 shows how timings vary with load capacitance Input waveforms except for CLKIN are assumed to have a rise and fall ti...

Page 46: ...aveform Figure 11 Output Delay Waveform 2 0 V 1 5 V 0 8 V TCF TCH TCL T TCR CLKIN Outputs 1 5 V 1 5 V TOV1 Min Max TOH1 1 5 V 1 5 V A31 2 D31 0 write only DP3 0 write only PCHK BE3 0 W R D C SUP ADS D...

Page 47: ...y DP3 0 write only PCHK BE3 0 W R D C SUP ADS DEN LOCK HOLDA CT3 0 WAIT BLAST DT R CLKIN 1 5 V 1 5 V CLKIN Inputs 1 5 V 1 5 V 1 5 V Valid TIS TIH READY HOLD BTERM BOFF D31 0 on reads Min Min DP3 0 on...

Page 48: ...OUTPUT DELAY The maximum output delay is referred to as the Output Valid Delay TOV The minimum output delay is referred to as the Output Hold TOH TIS TIH INPUT SETUP AND HOLD The input setup and hold...

Page 49: ...atasheet 49 Figure 17 TCK Waveform Figure 18 Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 2 0 V 1 5 V 0 8 V TBSCF TBSCH TBSCL TBSC TBSCR TCLK Inputs TMS 1 5 V 1 5 V 1 5 V TDI 1 5 V 1 5 V Valid...

Page 50: ...t Delay and Output Float Waveform for TBSOV2 and TBSOF2 Figure 21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 TCK 1 5 V 1 5 V 1 5 V 1 5 V TBSOV1 TDO Valid TBSOF1 TCK 1 5 V 1 5 V 1 5 V 1 5 V TB...

Page 51: ...rating at 85 C and Minimum VCC Figure 23 ICC Active Power Supply vs Frequency 50pF 100pF 150pF Time ns CL pF 5 4 3 2 1 2 0 to 0 8 V 0 8 to 2 0 V 0 I CC Active Power Supply mA CLKIN Frequency MHz 200 1...

Page 52: ...Frequency Figure 25 Output Delay or Hold vs Load Capacitance I CC Active Thermal mA CLKIN Frequency MHz 200 1400 1200 1000 800 600 400 10 20 30 40 HA HT HD 50 100 150 CL pF nom 10 nom 5 nom Output Val...

Page 53: ...VCC nom 0 0 nom 0 4 nom 0 5 Output Valid Delays ns 1 5 V nom 0 3 nom 0 2 nom 0 1 Processor Case Temperature C 85 C 0 C nom 0 5 nom 0 1 nom 0 Output Hold Times ns 1 5 V nom 0 2 nom 0 3 nom 0 4 Processo...

Page 54: ...3 0 Invalid Valid Inputs Tsetup 1CLKIN Thold 1CLKIN A31 2 SUP D C BE3 0 B A B A ONCE NOTE VCC stable As specified in Table 21 VDIFF Specification for Dual Power Supply Requirements 3 3 V 5 V on page 3...

Page 55: ...w to RESET State 16 CLKIN Periods 1 CLKIN CLKIN ADS DT R SUP D31 0 STEST RESET LOCK WAIT DEN BLAST A31 2 D C BE3 0 DP3 0 Valid Thold Tsetup 1 CLKIN W R BREQ FAIL BSTALL Minimum RESET Low Time 16 CLKIN...

Page 56: ...DEN DT R HOLDA CT3 0 BSTALL DP3 0 PCHK BLAST FAIL SUP BREQ VCC VCC5 ONCE mode is entered within 1 CLKIN period after ONCE becomes low while RESET is low CLKIN may neither float nor remain idle It must...

Page 57: ...KIN A D A D A D In Valid Valid Valid Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Disabled 0 OFF 0 0 0000 X xx X x Enabled 1 0 00 0 00000 0 00 Disabled...

Page 58: ...1 D 1 In Valid Valid A DP3 0 PCHK NOTE Bits 31 30 27 25 13 and 5 are reserved Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Disabled 0 OFF 0 1 0001 X xx...

Page 59: ...ut A Valid Valid BE3 0 DP3 0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Disabled 0 OFF 0 1 0001 X xx X x Enabled 1 X xxxxx 3 00011 X xx Disabled...

Page 60: ...T D31 0 CLKIN A D D D D A In3 In2 In1 Valid 00 01 10 11 DP3 0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabled 1 OFF 0 0 0000 32 Bit 10 X x Ena...

Page 61: ...IN A 2 1 D 1 D 1 D 1 D 1 A In1 In2 In3 In0 Valid 00 11 01 10 DP3 0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabled 1 OFF 0 1 0001 32 Bit 10 X...

Page 62: ...0 CLKIN A D D D D A 00 01 10 11 Out0 Out3 Out2 DP3 0 PCHK Out1 Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabled 1 OFF 0 0 0000 32 Bit 10 X x Enable...

Page 63: ...A 2 1 D 1 D 1 D 1 D 1 A Out0 Valid 00 11 01 10 Out1 Out2 Out3 DP3 0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabled 1 OFF 32 bit 0 1 0001 10...

Page 64: ...01 or 11 D15 0 A1 0 D15 0 A1 1 D15 0 A1 0 D15 0 A1 1 D C LOCK A31 4 BE3 BHE BE1 A1 BE0 BLE DP3 0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabl...

Page 65: ...e 0 D7 0 Byte 1 D7 0 Byte 2 D7 0 Byte 3 D C LOCK A31 4 BE1 A1 A1 0 00 A1 0 01 A1 0 10 A1 0 11 BE0 A0 DP3 0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6...

Page 66: ...alid Valid Valid Valid Invalid W R DP3 0 PCHK 1 Non pipelined request concludes pipelined reads begin 2 Pipelined reads conclude non pipelined requests begin 1 2 Burst Bus Width Odd Parity NXDA NWDD N...

Page 67: ...lid DP3 0 1 Non pipelined request concludes pipelined reads begin 2 Pipelined reads conclude non pipelined requests begin PCHK 2 1 Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 1...

Page 68: ...IN D IN D Valid D In Valid DP3 0 PCHK 1 2 Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabled 1 ON 1 X xxxx 32 Bit X x Enabled 1 X xx X xxxxx 0 00 X x...

Page 69: ...lid 00 01 10 11 Valid In valid DP3 0 PCHK 1 Non pipelined request concludes pipelined reads begin 2 Pipelined reads conclude non pipelined requests begin 2 1 NOTE Bits 31 30 27 25 13 and 5 are reserve...

Page 70: ...10 or 11 Valid In valid A1 0 00 A1 0 01 A1 0 10 A1 0 11 Valid Valid In valid DP3 0 1 Non pipelined request concludes pipelined reads begin 2 Pipelined reads conclude non pipelined requests begin PCHK...

Page 71: ...r 10 A3 2 01 or 11 Valid In valid Valid In valid BE3 BHE D31 0 LOCK DP3 0 PCHK 2 1 Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23 22 20 12 8 19 16 15 14 7 6 4 0 Enabled 1 ON 1 X xxxx 16...

Page 72: ...BLAST BTERM A3 2 WAIT D31 0 BE3 0 LOCK D0 D1 D2 D3 D0 D1 D2 D3 00 01 10 11 00 01 10 11 Valid Valid Quad Word Read Request NRAD 0 NRDD 0 NXDA 0 Ready Enabled Quad Word Write Request NWAD 1 NWDD 0 NWDA...

Page 73: ...0 Ready Enabled 00 01 10 11 Note READY adds memory access time to data transfers whether or not the bus access is a burst access BTERM interrupts a bus access whether or not the bus access has more d...

Page 74: ...cases potentially degrading processor performance Do not logically AND BSTALL and BREQ together in arbitration logic Instead the simplest bus arbitration should logically OR BSTALL and BREQ to determ...

Page 75: ...SUP DP3 0 D31 0 BOFF may not be asserted BOFF may not be asserted BOFF may be asserted to suspend request Begin Request End Request Suspend Request Non Burst CT3 0 D C BE3 0 WAIT DEN DT R WRITES Burs...

Page 76: ...6 Datasheet Figure 51 HOLD Functional Timing Word Read Request NRAD 1 NXDA 1 Word Read Request NRAD 0 NXDA 0 Hold State Hold State CLKIN ADS A31 2 SUP CT3 0 D C BE3 0 WAIT DEN DT R BLAST HOLD HOLDA Va...

Page 77: ...ng Figure 53 FAIL Functional Timing CLKIN ADS BLAST HOLD HOLDA LOCK W R RESET FAIL 257 517 Cycles 30 Cycles 113 Cycles Bus Test Pass Internal Self Test Pass Fail Fail 80960HA 80960HD 128 761 Cycles 15...

Page 78: ...ligned Byte Byte Requests Word Request Aligned Trey Byte Requests Short Short Requests Byte Trey Requests Byte Offset Word Offset One Double Word Burst Aligned Trey Byte Trey Byte Requests Short Short...

Page 79: ...ey Byte Trey Byte Requests Short Short Short Requests Short Short Short Short Byte Trey Byte Trey Byte Trey Requests Word Word Word Requests One Four Word Request Aligned Trey Byte Trey Byte Trey Byte...

Page 80: ...Bus Word 16 Bit Bus Short Four Short Burst Byte Short Byte 2 Short 4 Byte Short Byte 2 Four Short Burst Two Short Burst Byte Short Byte 3 Short 6 Byte Short Byte 3 Two Short Burst 3 Two Short Burst 3...

Page 81: ...t Two Byte Burst Byte Byte Four Byte Burst Three Byte Burst Byte Two Byte Burst 2 Four Byte Burst 3 Two Byte Burst 6 Four Byte Burst 3 Four Byte Burst Four Byte Burst 2 Three Byte Burst Byte 2 Four By...

Page 82: ...S A31 4 SUP D C LOCK W R BLAST DT R DEN A3 2 WAIT D31 0 READY BTERM Write Request NWAD 2 NXDA 0 Ready Disabled Idle Bus not in Hold Acknowledge state Read Request NRAD 2 NXDA 0 Ready Disabled In Out V...

Page 83: ...s Because External Ready Control is disabled for Read Pipelining the address cycle occurs during BLAST 2 WaCNT is decremented during Taw 3 WdCNT is decremented during Tdw 4 WxCNT is decremented during...

Page 84: ...D3 Bidirectional D4 Bidirectional D5 Bidirectional D6 Bidirectional D7 Bidirectional Enable for DP 3 0 and D 31 0 Control D8 Bidirectional D9 Bidirectional D10 Bidirectional D11 Bidirectional D12 Bid...

Page 85: ...R Output BLASTBAR Output DENBAR Output WRRDBAR Output Appears as WRBAR in BSDL file DTRBAR Output Enable for DTRBAR Control WAITBAR Output BSTALL Output DATACODBAR Output Appears as DCBAR in BSDL file...

Page 86: ...trol A15 Output A14 Output A13 Output A12 Output A11 Output A10 Output A9 Output A8 Output A7 Output A6 Output A5 Output A4 Output A3 Output A2 Output NMIBAR Input Table 26 80960Hx Boundary Scan Chain...

Page 87: ...ears as CT 3 0 in BSDL file CT2 Output CT1 Output CT0 Output PCHK Output Appears as PCHKBAR in BSDL file PCHK enable Control Table 26 80960Hx Boundary Scan Chain Sheet 4 of 4 Boundary Scan Cell Cell T...

Page 88: ...s and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein Boundary Scan Description Language BSDL Versio...

Page 89: ...port A out bit_vector 2 to 31 ADSBAR out bit BEBAR out bit_vector 0 to 3 BLASTBAR out bit BOFFBAR in bit BREQ out bit BSTALL out bit BTERMBAR in bit CT out bit_vector 0 to 3 CLKIN in bit D inout bit_v...

Page 90: ...linkage bit_vector 0 to 22 NC linkage bit_vector 0 to 4 use STD_1149_1_1990 all use i960ha_a all attribute PIN_MAP of Ha_Processor entity is PHYSICAL_PIN_MAP constant PGA PIN_MAP_STRING A D16 D17 E16...

Page 91: ...03 RESETBAR A16 STEST B02 SUPBAR Q12 TCK B05 TDI A07 TDO A08 TMS B06 TRST A06 WAITBAR S12 WRBAR S10 XINTBAR B15 A15 A17 B16 C15 B17 C16 C17 FIVEVREF C05 VOLTDET A05 VCCPLL B10 VCC1 M02 K02 J02 G02 N03...

Page 92: ...DCODE 0010 RUBIST 0111 CLAMP 0100 HIGHZ 1000 Reserved 1011 1100 attribute Instruction_Capture of Ha_Processor entity is 0001 attribute Instruction_Private of Ha_Processor entity is Reserved attribute...

Page 93: ...r X 17 1 Z 13 CBSC_1 D 4 bidir X 17 1 Z 14 CBSC_1 D 5 bidir X 17 1 Z 15 CBSC_1 D 6 bidir X 17 1 Z 16 CBSC_1 D 7 bidir X 17 1 Z 17 BC_1 control 1 18 CBSC_1 D 8 bidir X 17 1 Z 19 CBSC_1 D 9 bidir X 17 1...

Page 94: ...ASTBAR output3 X 61 1 Z 53 BC_1 DENBAR output3 X 61 1 Z 54 BC_1 WRBAR output3 X 61 1 Z 55 BC_1 DTRBAR output3 X 56 1 Z 56 BC_1 control 1 57 BC_1 WAITBAR output3 X 61 1 Z 58 BC_1 BSTALL output3 X 6 1 Z...

Page 95: ...6 output3 X 80 1 Z 91 BC_1 A 5 output3 X 80 1 Z 92 BC_1 A 4 output3 X 80 1 Z 93 BC_1 A 3 output3 X 80 1 Z 94 BC_1 A 2 output3 X 80 1 Z 95 BC_4 NMIBAR input X 96 BC_4 XINTBAR 7 input X 97 BC_4 XINTBAR...

Page 96: ...ices This language is under consideration by the IEEE for formal inclusion within a supplement to the 1149 1 1990 standard The generation of the supplement entails an extensive IEEE review and a forma...

Page 97: ...tor 0 to 31 DENBAR out bit DP inout bit_vector 0 to 3 DTRBAR out bit DCBAR out bit FAILBAR out bit HOLD in bit HOLDA out bit LOCKBAR out bit NMIBAR in bit ONCEBAR in bit PCHKBAR out bit READYBAR in bi...

Page 98: ...46 145 144 141 140 139 138 135 134 133 132 127 126 125 124 121 120 119 118 113 112 111 110 107 106 105 104 ADSBAR 77 BEBAR 83 82 79 78 BLASTBAR 84 BOFFBAR 10 BREQ 100 BSTALL 91 BTERMBAR 67 CT 183 182...

Page 99: ...7 8 16 18 24 30 32 43 47 48 53 58 65 70 73 75 80 86 93 94 98 103 VSS2 108 114 116 122 129 130 136 142 148 152 155 156 157 164 170 172 178 184 186 190 195 198 200 205 attribute Tap_Scan_In of TDI sign...

Page 100: ...ttribute Register_Access of Ha_Processor entity is Runbist 32 RUBIST Bypass CLAMP HIGHZ The first cell cell 0 is closest to TDO BC_1 Control Output3 CBSC_1 Bidir BC_4 Input Clock attribute Boundary_Ce...

Page 101: ...22 CBSC_1 D 12 bidir X 17 1 Z 23 CBSC_1 D 13 bidir X 17 1 Z 24 CBSC_1 D 14 bidir X 17 1 Z 25 CBSC_1 D 15 bidir X 17 1 Z 26 CBSC_1 D 16 bidir X 17 1 Z 27 CBSC_1 D 17 bidir X 17 1 Z 28 CBSC_1 D 18 bidi...

Page 102: ...56 BC_1 control 1 57 BC_1 WAITBAR output3 X 61 1 Z 58 BC_1 BSTALL output3 X 6 1 Z 59 BC_1 DCBAR output3 X 61 1 Z 60 BC_1 SUPBAR output3 X 61 1 Z 61 BC_1 control 1 62 BC_1 LOCKBAR output3 X 61 1 Z 63 B...

Page 103: ...5 output3 X 80 1 Z 92 BC_1 A 4 output3 X 80 1 Z 93 BC_1 A 3 output3 X 80 1 Z 94 BC_1 A 2 output3 X 80 1 Z 95 BC_4 NMIBAR input X 96 BC_4 XINTBAR 7 input X 97 BC_4 XINTBAR 6 input X 98 BC_4 XINTBAR 5 i...

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