TB-FMCH-HDMI4K Hardware User Manual
24
Rev.2.04
9.4. HDMI DDC
The HDMI DDC (Display Data Channel) interface is implemented for both the Source and Sink HDMI
ports. A bypass loopback is also provided using four 3-pin headers. Figure 9-1 illustrates the connections
for the Source and Sink.
Figure 9-1 HDMI Source and Sink DDC
The TB-FMCH-HDMI4K is shipped with the J4, J5, J6, and J7 jumpers placed in the normal operation
positions. They can be moved for test purposes. The source DDC connections to the TPD5S116 are for
ESD protection and provide pull-up resistors. J3-G24 (LA22_P) should be low to enable the sink DDC.
10. Clocks
10.1. Si5324 Any-Frequency Clock Generator
The Silicon Labs Si5324C Any-Frequency Precision Clock Multiplier/Jitter Attenuator enables the user to
generate the desired video clock frequency for use by the FPGA. An onboard 114.285 MHz crystal can
be used to asynchronously generate the video clocks. The CKIN1 differential input from the FPGA can
J4
J5
J1
J6
J7
15
16
DDC
SCL
DDC
SDA
J2
15
16
HDMI Source
HDMI Sink
1
32
33
2
3
1
2
3
SCL SINK
SDA SINK
SCL SRC
SDA SRC
38
39
SN65DP159
PCA9517
LA29_P
LA29_N
G30
G31
2
3
7
6
SCLA
SDAA
SCLB
SDAB
B3
SCL CON
SDA CON
C3
SCL SYS
SDA SYS
B1
C1
no connection
no connection
TPD5S116
PCA9509
2
3
7
6
A1
A2
B1
B2
PCA9507
7
6
2
3
SCLB
SDAB
SCLA
SDAA
LA16_P
LA16_N
G18
G19
2
2
3
3
1
1
DDC
SCL
DDC
SDA
J3 FMC
Connector for
Main Board
EN
LA22_P
G24
SN74AVCT245
LA15_P (SCL)
LA15_N (SDA)
H19
H20
LA28_P (SCL)
LA28_N (SDA)
H31
H32
LA29_P
LA29_N
G30
G31
LA16_P
LA16_N
G18
G19
J8 FMC
Connector for
Extender
Card
Source DDC
Sink DDC
Ext. Sink DDC
Ext. Source DDC
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
Normal Operation
HDMI DDC Bypass
Loopback
J4
J5
J6
J7
DDC Jumper Settings
Low = enable
