TB-FMCH-HDMI4K Hardware User Manual
26
Rev.2.04
of two source clocks from the FPGA.
Figure 10-2 shows how the clocks are connected and how the extender FMC clocks are connected.
Figure 10-2 HDMI Source Clocks
10.3. HDMI Sink Clock
The HDMI TMDS sink clock is terminated and AC coupled to a DS90LV001 LVDS buffer. The buffer
output is AC coupled to the GBTCLK0_M2C input clock of the J3 FMC main board connector (J3-D4,
J3-D5). The LVDS buffer is permanently enabled.
11. Hot Plug Detect (HPD)
The HDMI sink HPD signal is controlled via a MOSFET. The MOSFET control signal is from J3-G22
(LA20_N) through a voltage translator. The sink HPD signal is low when LA20_N is high. It is also
connected to the HPD connector input of a Texas Instruments TPD5S116 HDMI companion chip for
transient protection.
The HDMI source HPD signal from the J1 HDMI source connector connects to the HPD connector input
of another TPD5S116. The TPD5S116 HPD system output connects to J3-G34 (LA31_N). The source
HPD signal also connects to the HPD Sink input of the SN65DP159. This enables the SN65DP159 to
know when the HPD signal is active.
Two three-pin headers (J11 and J13) provide a bypass loopback for test purposes. Figure 11-1 shows
how the HPD signals are connected and how the extender FMC HPD signals are connected.
Note:
The TB-FMCH-HDMI4k does not support the HDMI Ethernet and Audio Return Channel (HEAC)
on either HDMI interface.
D_P
D_N
9
10
9
10
J1
10
12
HDMI Source
1D_P
1D_N
2D_P
2D_N
8
7
1
2
3
4
OE_N
pulled
low
S
9
IN_CLK_P
IN_CLK_N
SN74AVC4T245
Voltage Translator
OUT_CLK_P
OUT_CLK_N
J3 FMC
Connector for
Main Board
DP3_C2M_P A30
A31
DP3_C2M_N
LA27_P
C27
LA27_N
C26
C22
LA18_CC_P
SN65DP159
TS3USB221
TMDS
CLK
Select
Low = 1D
à
D
High = 2D
à
D
DP7_C2M_P B32
B33
DP7_C2M_N
LA14_P
C19
LA14_N
C18
D17
LA13_P
J8 FMC
Connector for
Extender Card
A30
A31
C27
C26
C22
DP3_C2M_P
DP3_C2M_N
LA27_P
LA27_N
LA18_CC_P
