Inrevium TB-FMCH-HDMI4K, Hardware User Manual

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TB-FMCH-HDMI4K Hardware User Manual
16
Rev.2.04
Table 8-1 HPC FMC Main Board Connector Pin Assignment
J3
Pin
Schematic Signal Name VITA 57.1 Name Direction Type Description
HDMI Source Signals
C2 TX_CH0_MGT_P DP0_C2M_P
C2M CML
SN65DP159
channel 0 input
C3 TX_CH0_MGT_N DP0_C2M_N
A22 TX_CH1_MGT_P DP1_C2M_P
C2M CML
SN65DP159
channel 1 input
A23 TX_CH1_MGT_N DP1_C2M_N
A26 TX_CH2_MGT_P DP2_C2M_P
C2M CML
SN65DP159
channel 2 input A27 TX_CH2_MGT_N DP2_C2M_N
A30 CLK_TX_CH3_MGT_P DP3_C2M_P
C2M CML
SN65DP159 1 of
2 clock mux input A31 CLK_TX_CH3_MGT_N DP3_C2M_N
C26 CLK_TX_LVDS_P LA27_P
C2M LVDS
SN65DP159 2 of
2 clock mux input C27 CLK_TX_LVDS_N LA27_N
C22 TX_CLK_SEL_FPGA LA18_CC_P C2M LVTTL (VADJ)
SN65DP159 input
clock mux select
C10 CLK_I2C_CTL_FPGA_SCL LA06_P C2M LVTTL OD (VADJ) I2C for Si5324,
EDID EEPROM,
and SN65DP159
C11 I2C_CTL_FPGA_SDA_OD LA06_N BI-DIR LVTTL OD (VADJ)
G33 TX_CEC LA31_P BI-DIR LVTTL (VADJ) Source CEC
G34 TX_HPD_HDMI LA31_N M2C LVTTL (VADJ) Source HPD
D26 TX_HDMI_EN_FPGA LA26_P C2M LVTTL (VADJ) SN65DP159 OE
G30 CLK_I2C_TX_FPGA_SCL LA29_P C2M LVTTL OD (VADJ)
Source DDC I2C
G31 I2C_TX_FPGA_SDA_OD LA29_N BI-DIR LVTTL OD (VADJ)
HDMI Sink Signals
C6 RX_TMDS_DAT0_P DP0_M2C_P
M2C TMDS Sink Channel 0
C7 RX_TMDS_DAT0_N DP0_M2C_N
A2 RX_TMDS_DAT1_P DP1_M2C_P
M2C TMDS Sink Channel 1
A3 RX_TMDS_DAT1_N DP1_M2C_N
A6 RX_TMDS_DAT2_P DP2_M2C_P
M2C TMDS Sink Channel 2
A7 RX_TMDS_DAT2_N DP2_M2C_N
D4 CLK_HDMI_RX_P GBTCLK0_M2C_P
M2C LVDS Sink Clock
D5 CLK_HDMI_RX_N GBTCLK0_M2C_N
G18 CLK_I2C_RX_FPGA_SCL LA16_P M2C LVTTL OD (VADJ)
Sink DDC I2C
G19 I2C_RX_FPGA_SDA_OD LA16_N BI-DIR LVTTL OD (VADJ)
G24 RX_I2C_EN_N_FPGA LA22_P C2M LVTTL (VADJ) Sink DDC enable
G21 RX_CEC LA20_P BI-DIR LVTTL (VADJ) Sink CEC
G22 RX_HPD_N LA20_N C2M LVTTL (VADJ) Sink HPD
G9 SOURCE_DET_N LA03_P M2C LVTTL (VADJ) Sink detect
Si5324 Clocks
B20 CLK_MGT_REFCLK_P GBTCLK1_M2C_P
M2C LVDS Si5324 CKOUT1
B21 CLK_MGT_REFCLK_N GBTCLK1_M2C_N
H4 CLK_LVDS_P CLK0_M2C_P M2C LVDS Si5324 CKOUT2