Inrevium TB-FMCH-HDMI2 Hardware User Manual Download Page 28

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TB-FMCH-HDMI2 Hardware User Manual

Rev.1.05

4.12. Image Size

4.12.1. 2D Image Size

TB-FMCH-HDMI2-RX supports HDMI1.4-compliant primary format and part of secondary format

(1080p@60Hz).

Supported image size:



[email protected]/60Hz



[email protected]/60Hz



[email protected]/60Hz



720x480p @ 59.94/60Hz



720(1440)[email protected]/60Hz



1280x720@50Hz



1920x1080i@50Hz



720x576p@50Hz



720(1440)x576i@50Hz



[email protected]/60Hz



1920x1080p@50Hz

4.12.2. 3D Image Size

TB-FMCH-HDMI2-RX supports HDMI1.4-compliant primary format.

Supported image size:



[email protected]/60Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)



1280x720p@50Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)



[email protected]/24Hz (Frame Packing)



[email protected]/30Hz (Frame Packing)



[email protected]/60Hz (Frame Packing, Side-by-Side(Half))



1920x1080i@50Hz (Frame Packing, Side-by-Side(Half))



[email protected]/24Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)



[email protected]/30Hz (Frame Packing, Top-and-Bottom)



[email protected]/60Hz (Top-and-Bottom)



1920x1080p@50Hz (Top-and-Bottom)

Summary of Contents for TB-FMCH-HDMI2

Page 1: ...TB FMCH HDMI2 Hardware User Manual 1 Rev 1 05 TB FMCH HDMI2 Hardware User Manual Rev 1 05 ...

Page 2: ...her Rev 1 00 2011 02 01 Initial release Yoshioka Rev 1 01 2011 03 29 Modified Figure4 2 4 3 5 2 5 3 Yoshioka Rev 1 02 2012 10 18 Add Table5 6 Yanagisawa Rev 1 03 2014 04 15 Add EC Declaration of Conformity Amano Rev 1 04 2014 08 13 Modify Table 5 7 Amano Rev 1 05 2017 05 10 Modify Table 4 7 Goto ...

Page 3: ...utput Data Phase 27 4 12 Image Size 28 4 12 1 2D Image Size 28 4 12 2 3D Image Size 28 5 TB FMCH HDMI2 TX 29 5 1 Block Diagram 29 5 2 External View of the Board 30 5 3 Board Specification 31 5 4 Power Supply to the Board 32 5 5 HDMI Transmitter 33 5 6 FMC Connector 34 5 7 Other Interfaces 37 5 7 1 JTAG Interface 37 5 7 2 General Purpose Clock Interface 37 5 8 LED Status 38 5 9 Relation of ROM and ...

Page 4: ...ttings component side 51 Figure 7 2 TB FMCH HDMI2 TX Default Settings component side 53 Figure 8 1 Usage Example 55 List of Tables Table 2 1 ROM data 8 Table 4 1 HDMI Connector receiving side 14 Table 4 2 SCL SDA Jumper Setting 14 Table 4 3 JP1 Jumper Setting 15 Table 4 4 FMC Connector Pin Assignment 16 Table 4 5 JTAG Connector 18 Table 4 6 LED Status 19 Table 4 7 Switches 19 Table 4 8 FPGA Pin As...

Page 5: ...erious safety instructions that must be observed After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled incorrectly Indicates the possibility of serious injury or...

Page 6: ... speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fir...

Page 7: ...ity acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no respons...

Page 8: ...ere are called TB FMCH HDMI2 This document specifically describes these optional boards in the RX and TX sections respectively Each board has two independent receivers transmitters and is designed for high resolution support It uses Samtec s FMC connector and Molex s HDMI connector for connection with a platform board having High Pin Count connectors This User Manual is refer to Initial ROM files ...

Page 9: ...s ADV7511KSTZ P FMC Connector Samtec s ASP 134488 01 HDMI Connector common Molex s 5002541927 Power Supply common Jumper switch selection The RX board has an EEPROM for Display Data Channel hereafter referred to as DDC and allows setting the AnalogDevices s ADV7612BSWZ P board operation via jumpers Figure 3 1 FMC Connector Pin Layout ...

Page 10: ...A LED 7 0 DSW 7 0 RSW 3 0 JTAG 87832 1420 KC5032C27 000 RX 0_HPD_IO DDC0_GND DDC0 DDC0_HPD DDC0_5V DDC0_SDA RX 0_CEC RX 0_DDCA_SDA_F RX 0_DDCA_SCL_F RX 0_DET1 DDC0_SCL DDC_GND0 DEC 1 500254 1927 HDMI 1 RX ADV7612 RX 1_C RX 1_0 2 RX 1_P 35 0 RX 1_VS HS DE RX 1_LLC RX 1_DDCA_SCL CEC 1 DET1 HPD 1 28 6363MHz RX 1_SPDIF RX 1_I2S 3 0 RX 1_SCLK RX 1_LRCLK RX 1_MCLKOUT RX 1_SCL RX 1_INT1 CSN RX 1_RESETN E...

Page 11: ... the external view of the TB FMCH HDMI2 RX board Caution This board has a plastic cover for protecting HDMI devices Do not remove a plastic cover HDMI Connector HDMI Receiver FPGA Figure 4 2 External View of TB FMCH HDMI2 RX component side FMC HPC Figure 4 3 External View of TB FMCH HDMI2 RX solder side ...

Page 12: ...ows TB FMCH HDMI2 RX board specifications External Dimensions W 160mm x H 69mm Number of Layers 8 layers Board Thickness 1 6 mm Material FR 4 FPGA Xilinx s XC6SLX45 3FGG484C FMC Connector Samtec s ASP 134488 01 HDMI Connector Molex s 5002541927 Figure 4 4 TB FMCH HDMI2 RX Board Dimensions ...

Page 13: ... LTC3026EMSE ADV7612 449 7mA VCC_3 3V FPGA_VCAUX 50mA FPGA_VCCIO 29mA ADV7612 312 5mA x2 625mA 1170mA KC3225A 6mA NC7SZ125 0 02mA x2 0 04mA 24LCS22A 3mA x2 6mA LTC1326 0 04mA 135mA VCC_2 5V 2 926W 750mA 2 475W 0 677W 562mA LT3503EDCB LT3568EDD FPGA_VCCINT 485mA VCC_1 2V FPGA_VCCIO 261mA XCF16 VCCINT 10mA ADV7612 449 7mA XCF16 VCCIO 40mA LT3503EDCB Figure 4 5 TB FMCH HDMI2 RX Power Supply Structure...

Page 14: ... SHLD TMDS receive clock shield 12 TMDS CLK TMDS receive clock 13 CEC CEC signal 14 RESERVED Reserved 15 DDC_SCL DDC serial clock 16 DDC_SDA DDC serial data 17 DDC CEC GND DDC CEC ground 18 DDC_ 5V 5V power supply 19 HOTPLUG_DET Hot plug detection The receiver has an EEPROM 24LCS22A SN Micro Chip This EEPROM is used to store EDID data The SCL signal can be switched by JP6 JP3 and the SDA signal us...

Page 15: ...e TB FMCH HDMI2 RX is supplied from a 12V on the main board An external power source can also be used Table 4 3 shows JP1 jumper setting for power supply Table 4 3 JP1 Jumper Setting No Purpose Silk Setting 1 FMC connector 12VIN_SEL JP1 1 2 short 2 External power supply 12VIN_SEL JP1 2 3 short To connect an external power source use the following test pin TP14 12VIN ...

Page 16: ... DP4_M2C_N GND LA10_N LA09_N HA16_P 16 GND DP6_M2C_P GND GND HA16_N 17 GND DP6_M2C_N GND LA13_P GND 18 DP5_M2C_P GND LA14_P LA13_N HA20_P 19 DP5_M2C_N GND LA14_N GND HA20_N 20 GND GBTCLK1_M2C_P GND LA17_P_CC GND 21 GND GBTCLK1_M2C_N GND LA17_N_CC HB03_P 22 DP1_C2M_P GND LA18_P_CC GND HB03_N 23 DP1_C2M_N GND LA18_N_CC LA23_P GND 24 GND DP2_C9M_P GND LA23_N HB05_P 25 GND DP2_C9M_N GND GND HB05_N 26 ...

Page 17: ...1_P HA14_N HA17_P_CC 17 HA15_P GND LA11_N GND HA17_N_CC 18 HA15_N LA16_P GND HA18_P GND 19 GND LA16_N LA15_P HA18_N HA21_P 20 HA19_P GND LA15_N GND HA21_N 21 HA19_N LA20_P GND HA22_P GND 22 GND LA20_N LA19_P HA22_N HA23_P 23 HB02_P GND LA19_N GND HA23_N 24 HB02_N LA22_P GND HB01_P GND 25 GND LA22_N LA21_P HB01_N HB00_P_CC 26 HB04_P GND LA21_N GND HB00_N_CC 27 HB04_N LA25_P GND HB07_P GND 28 GND LA...

Page 18: ...GA EEPROM device 24LCS22A SN Micro Chip 4 7 2 JTAG Interface JTAG connector for FPGA configuration JTAG connector 87832 1420 Molex Table 4 5 JTAG Connector Pin Signal Pin Signal 1 GND 2 3 3V 3 GND 4 TMS 5 GND 6 TCK 7 GND 8 TDO 9 GND 10 TDI 11 GND 12 NC 13 GND 14 NC 4 7 3 General Purpose Clock Interface General purpose clock for FPGA 27MHz crystal oscillator KC5032C027 0000C30E00 Kyocera ...

Page 19: ...monitor Flashing Clock Off No clock 7 DS7 LED6 General purposeLED6 RX1 Input video image clock monitor Flashing Clock Off No clock 8 DS8 LED7 General purposeLED7 System reset monitor On Reset active Off Reset released 9 DS10 HPD0 RX0 hot plug display On Connected state 10 DS9 HPD1 RX1 hot plug display On Connected state 11 DS11 DONE Config display On Config done 12 DS12 12VLED 12V display On 12V a...

Page 20: ...l FPGA to FMC B8 LA12_P D19 O LVCMOS25 RX 0_P9 signal FPGA to FMC B9 LA13_P D21 O LVCMOS25 RX 0_P10 signal FPGA to FMC G0 LA14_P G19 O LVCMOS25 RX 0_P11 signal FPGA to FMC G1 LA15_P E20 O LVCMOS25 RX 0_P12 signal FPGA to FMC G2 LA16_P F21 O LVCMOS25 RX 0_P13 signal FPGA to FMC G3 LA17_P_CC G20 O LVCMOS25 RX 0_P14 signal FPGA to FMC G4 LA18_P_CC H21 O LVCMOS25 RX 0_P15 signal FPGA to FMC G5 LA19_P ...

Page 21: ...l FPGA to FMC G3 LA17_N_CC G22 O LVCMOS25 RX 1_P14 signal FPGA to FMC G4 LA18_N_CC H22 O LVCMOS25 RX 1_P15 signal FPGA to FMC G5 LA19_N J22 O LVCMOS25 RX 1_P16 signal FPGA to FMC G6 LA20_N L22 O LVCMOS25 RX 1_P17 signal FPGA to FMC G7 LA21_N N22 O LVCMOS25 RX 1_P18 signal FPGA to FMC G8 LA22_N R22 O LVCMOS25 RX 1_P19 signal FPGA to FMC G9 LA23_N U22 O LVCMOS25 RX 1_P20 signal FPGA to FMC R0 LA24_N...

Page 22: ...VCMOS25 Unused HA23_P V21 IO LVCMOS25 Unused CLK2_M2C_N C12 IO LVCMOS25 Unused CLK3_M2C_N A12 IO LVCMOS25 Unused HA00_N_CC A6 IO LVCMOS25 Unused HA01_N_CC A8 IO LVCMOS25 Unused HA02_N A9 IO LVCMOS25 Unused HA03_N C10 IO LVCMOS25 Unused HA04_N C14 IO LVCMOS25 Unused HA05_N A15 IO LVCMOS25 Unused HA06_N A16 IO LVCMOS25 Unused HA07_N A18 IO LVCMOS25 Unused HA08_N B20 IO LVCMOS25 Unused HA09_N F17 IO ...

Page 23: ...X to FPGA RX 0_P18 AA18 I LVCMOS33 RX 0 Video data 18 RX to FPGA RX 0_P17 AB18 I LVCMOS33 RX 0 Video data 17 RX to FPGA RX 0_P16 Y17 I LVCMOS33 RX 0 Video data 16 RX to FPGA RX 0_P15 AB17 I LVCMOS33 RX 0 Video data 15 RX to FPGA RX 0_P14 AA14 I LVCMOS33 RX 0 Video data 14 RX to FPGA RX 0_P13 AB14 I LVCMOS33 RX 0 Video data 13 RX to FPGA RX 0_P12 Y16 I LVCMOS33 RX 0 Video data 12 RX to FPGA RX 0_P1...

Page 24: ...ug Control FPGA to RX RX 0_DET1 V9 I LVCMOS33 RX 0 Detect Signal RX to FPGA FPGA_SRSTN AA2 I LVCMOS33 FPGA Reset RX 1_P35 Y2 I LVCMOS33 RX 1 Video Data 35 RX to FPGA RX 1_P34 Y1 I LVCMOS33 RX 1 Video Data 34 RX to FPGA RX 1_P33 W3 I LVCMOS33 RX 1 Video Data 33 RX to FPGA RX 1_P32 W1 I LVCMOS33 RX 1 Video Data 32 RX to FPGA RX 1_P31 P8 I LVCMOS33 RX 1 Video Data 31 RX to FPGA RX 1_P30 P7 I LVCMOS33...

Page 25: ... FPGA RX 1_HSYNC M1 I LVCMOS33 RX 1 HSYNC RX to FPGA RX 1_VSYNC L3 I LVCMOS33 RX 1 VSYNC RX to FPGA RX 1_SPDIF L1 I LVCMOS33 RX 1 SPDIF Digital Audio RX to FPGA RX 1_I2S0 K2 I LVCMOS33 RX 1 I2S Audio Signal 0 RX to FPGA RX 1_I2S1 K1 I LVCMOS33 RX 1 I2S Audio Signal 1 RX to FPGA RX 1_I2S2 K6 I LVCMOS33 RX 1 I2S Audio Signal 2 RX to FPGA RX 1_I2S3 J6 I LVCMOS33 RX 1 I2S Audio Signal 3 RX to FPGA RX ...

Page 26: ...DIP Switch 3 DSW4 E4 I LVCMOS33 DIP Switch 4 DSW5 J7 I LVCMOS33 DIP Switch 5 DSW6 H8 I LVCMOS33 DIP Switch 6 DSW7 B2 I LVCMOS33 DIP Switch 7 LED0 G7 O LVCMOS33 LED0 LED1 F7 O LVCMOS33 LED1 LED2 D3 O LVCMOS33 LED2 LED3 C4 O LVCMOS33 LED3 LED4 E5 O LVCMOS33 LED4 LED5 E6 O LVCMOS33 LED5 LED6 A2 O LVCMOS33 LED6 LED7 B3 O LVCMOS33 LED7 ...

Page 27: ...data phase of FPGA on TB FMCH HDMI2 RX FPGA to FMC data is output at the falling edge of the video clock The data should be latched at the rising edge on the main board side FPGA FMC HDMIRX_CLK VSYNC HSYNC DE DATA Output data are synchronous with down edge of HDMIRX_CLK Figure 4 6 FPGA Output Data Timing ...

Page 28: ...0x1080p 50Hz 4 12 2 3D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format Supported image size 1280x720p 59 94 60Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 50Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 23 98 24Hz Frame Packing 1280x720p 23 97 30Hz Frame Packing 1920x1080i 59 94 60Hz Frame Packing Side by Side Half 1920x1080i 50Hz Frame Packing Si...

Page 29: ...TDO TX 0_SCL SDA HPD 0 CLK SYSCLK_P LED 7 0 DSW 7 0 RSW 3 0 JTAG KC5032C27 000 KC5032C12 000 CLK TX 0_HPD_IO TX 0_DDCA_SDA DDC0_GND DDC0 DDC0_HPD DDC0_5V DDC0_SDA DDC0_SCL T_SHLD0 VCC_5V ENC 1 500254 1927 HDMI 1 TX ADV7511 TX 1_C TX 0_0 2 TX 1_D 35 0 TX 1_VS HS DE TX 1_CLK TX 1_DDCA_SCL CEC 1 HEAC 1 TX 1_DSD 5 0 TX 1_DSDCLK TX 1_SPDIF TX 1_MCLK TX 1_I2S 3 0 TX 1_SCLK TX 1_LRCLK TX 1_PD TX 1_INT TX...

Page 30: ...Rev 1 05 5 2 External View of the Board Figures 5 2 and 5 3 show the external view of the TB FMCH HDMI2 TX board HDMI Connector HDMI Transmitter FPGA Figure 5 2 TB FMCH HDMI2 TX component side FMC HPC Figure 5 3 TB FMCH HDMI2 TX solder side ...

Page 31: ... the TB FMCH HDMI2 TX board specification External Dimensions W 160mm x H 69mm Number of Layers 8 Layers Board Thickness 1 6 mm Material FR 4 FPGA Xilinx s XC6SLX45 3FGG484C FMC Connector Samtec s ASP 134488 01 HDMI Connector Molex s 5002541927 Figure 5 4 TB FMCH HDMI2 TX Board Dimensions ...

Page 32: ...CC_1 8V1 LTC3026EMSE ADV7511 196mA VCC_3 3V FPGA_VCAUX 68mA FPGA_VCCIO 311mA ADV7511 0 3mA x2 0 6mA 663mA KC3225A 6mA x3 18mA LTC1326 0 04mA 134mA VCC_2 5V 1 6575W 437mA 1 442W 0 671W 349mA LT3503EDCB LT3568EDD FPGA_VCCINT 503mA VCC_1 2V FPGA_VCCIO 261mA XCF16 VCCINT 10mA XCF16 VCCIO 40mA LT3503EDCB ADG702 0 001mA x2 0 002mA ADV7511 196mA Figure 5 5 TB FMCH HDMI2 TX Power Supply Structure ...

Page 33: ...smit Data 2 2 TMDS SHLD2 TMDS Transmit Data 2 Shield 3 TMDS DATA2 TMDS Transmit Data 2 4 TMDS DATA1 TMDS Transmit Data 1 5 TMDS SHLD1 TMDS Transmit Data 1 Shield 6 TMDS DATA1 TMDS Transmit Data 1 7 TMDS DATA0 TMDS Transmit Data 0 8 TMDS SHLD0 TMDS Transmit Data 0 Shield 9 TMDS DATA0 TMDS Transmit Data 0 10 TMDS CLK TMDS Transmit Clock 11 TMDS CLK SHLD TMDS Transmit Clock Shield 12 TMDS CLK TMDS Tr...

Page 34: ...DMI2 TX is supplied from a 12V on the main board An external power source can also be used Table 5 2 shows JP3 jumper setting for power supply Table 5 2 JP3 Jumper Setting No Purpose Silk Jumper Setting 1 FMC Connector 12VIN_SEL JP3 1 2 short 2 External Power Source 12VIN_SEL JP3 2 3 short The following test pin is used to connect an external power source TP14 12VIN ...

Page 35: ... DP4_M2C_N GND LA10_N LA09_N HA16_P 16 GND DP6_M2C_P GND GND HA16_N 17 GND DP6_M2C_N GND LA13_P GND 18 DP5_M2C_P GND LA14_P LA13_N HA20_P 19 DP5_M2C_N GND LA14_N GND HA20_N 20 GND GBTCLK1_M2C_P GND LA17_P_CC GND 21 GND GBTCLK1_M2C_N GND LA17_N_CC HB03_P 22 DP1_C2M_P GND LA18_P_CC GND HB03_N 23 DP1_C2M_N GND LA18_N_CC LA23_P GND 24 GND DP2_C9M_P GND LA23_N HB05_P 25 GND DP2_C9M_N GND GND HB05_N 26 ...

Page 36: ...1_P HA14_N HA17_P_CC 17 HA15_P GND LA11_N GND HA17_N_CC 18 HA15_N LA16_P GND HA18_P GND 19 GND LA16_N LA15_P HA18_N HA21_P 20 HA19_P GND LA15_N GND HA21_N 21 HA19_N LA20_P GND HA22_P GND 22 GND LA20_N LA19_P HA22_N HA23_P 23 HB02_P GND LA19_N GND HA23_N 24 HB02_N LA22_P GND HB01_P GND 25 GND LA22_N LA21_P HB01_N HB00_P_CC 26 HB04_P GND LA21_N GND HB00_N_CC 27 HB04_N LA25_P GND HB07_P GND 28 GND LA...

Page 37: ...as a JTAG connector FPGA configuration JTAG Connector Molex s 87832 1420 Table 5 4 JTAG Connector Pin Signal Pin Signal Name 1 GND 2 3 3V 3 GND 4 TMS 5 GND 6 TCK 7 GND 8 TDO 9 GND 10 TDI 11 GND 12 NC 13 GND 14 NC 5 7 2 General Purpose Clock Interface The board has a general purpose clock on FPGA 27MHz crystal oscillator KC5032C027 0000C30E00 Kyocera ...

Page 38: ...o clock 8 DS10 LED7 General purpose LED7 System Reset Monitor On Reset active Off Reset release 9 DS1 HPD0 TX0 hot plug display On Connected state 10 DS2 HPD1 TX1 hot plug display On Connected state 11 DS11 DONE Config display On Config complete 12 DS12 12VLED 12V display On 12V active 5 9 Relation of ROM and Input Video Format TB FMCH HDMI2 RX and TB FMCH HDMI2 TX have 3 types of FPGA ROM Relatio...

Page 39: ...o Circuit Silk Description 1 S1 1 DSW ADV7511 config ROM selection 8bit Output S1 1 OFF S1 2 ON S1 3 ON S1 4 ON 10bit Output S1 1 ON S1 2 ON S1 3 OFF S1 4 ON 2 S1 2 DSW 3 S1 3 DSW 4 S1 4 DSW 5 S1 5 DSW OFF 6 S1 6 DSW Unused 7 S1 7 DSW Unused 8 S1 8 DSW Unused 9 S2 RSW Unused 10 S3 RST FPGA reconfig long push 3 seconds FPGA reset short push ...

Page 40: ...2_P D19 I LVCMOS25 TX 0_D9 Signal FMC to FPGA B9 LA13_P D21 I LVCMOS25 TX 0_D10 Signal FMC to FPGA G0 LA14_P G19 I LVCMOS25 TX 0_D11 Signal FMC to FPGA G1 LA15_P E20 I LVCMOS25 TX 0_D12 Signal FMC to FPGA G2 LA16_P F21 I LVCMOS25 TX 0_D13 Signal FMC to FPGA G3 LA17_P_CC G20 I LVCMOS25 TX 0_D14 Signal FMC to FPGA G4 LA18_P_CC H21 I LVCMOS25 TX 0_D15 Signal FMC to FPGA G5 LA19_P J20 I LVCMOS25 TX 0_...

Page 41: ...l FMC to FPGA G3 LA17_N_CC G22 I LVCMOS25 TX 1_D14 Signal FMC to FPGA G4 LA18_N_CC H22 I LVCMOS25 TX 1_D15 Signal FMC to FPGA G5 LA19_N J22 I LVCMOS25 TX 1_D16 Signal FMC to FPGA G6 LA20_N L22 I LVCMOS25 TX 1_D17 Signal FMC to FPGA G7 LA21_N N22 I LVCMOS25 TX 1_D18 Signal FMC to FPGA G8 LA22_N R22 I LVCMOS25 TX 1_D19 Signal FMC to FPGA G9 LA23_N U22 I LVCMOS25 TX 1_D20 Signal FMC to FPGA R0 LA24_N...

Page 42: ...VCMOS25 Unused HA23_P V21 IO LVCMOS25 Unused CLK2_M2C_N C12 IO LVCMOS25 Unused CLK3_M2C_N A12 IO LVCMOS25 Unused HA00_N_CC A6 IO LVCMOS25 Unused HA01_N_CC A8 IO LVCMOS25 Unused HA02_N A9 IO LVCMOS25 Unused HA03_N C10 IO LVCMOS25 Unused HA04_N C14 IO LVCMOS25 Unused HA05_N A15 IO LVCMOS25 Unused HA06_N A16 IO LVCMOS25 Unused HA07_N A18 IO LVCMOS25 Unused HA08_N B20 IO LVCMOS25 Unused HA09_N F17 IO ...

Page 43: ...X 0 Video data 19 FPGA to TX TX 0_D18 AB14 O LVCMOS33 TX 0 Video data 18 FPGA to TX TX 0_D17 Y16 O LVCMOS33 TX 0 Video data 17 FPGA to TX TX 0_D16 W15 O LVCMOS33 TX 0 Video data 16 FPGA to TX TX 0_D15 V13 O LVCMOS33 TX 0 Video data 15 FPGA to TX TX 0_D14 W13 O LVCMOS33 TX 0 Video data 14 FPGA to TX TX 0_D13 AA16 O LVCMOS33 TX 0 Video data 13 FPGA to TX TX 0_D12 AB16 O LVCMOS33 TX 0 Video data 12 F...

Page 44: ... TX 0 Power Down FPGA to TX TX 0_INT Y19 I LVCMOS33 TX 0 Interrupt TX to FPGA TX 0_SCL AB19 O LVCMOS33 TX 0 Serial Clock FPGA to TX TX 0_SDA W18 IO LVCMOS33 TX 0 Serial Data FPGA to TX FPGA_SRSTN AA2 O LVCMOS33 FPGA Reset TX 1_D35 W3 O LVCMOS33 TX 1 Video data 35 FPGA to TX TX 1_D34 W1 O LVCMOS33 TX 1 Video data 34 FPGA to TX TX 1_D33 P8 O LVCMOS33 TX 1 Video data 33 FPGA to TX TX 1_D32 P7 O LVCMO...

Page 45: ...to TX TX 1_VSYNC K1 O LVCMOS33 TX 1 VSYNC FPGA to TX TX 1_DSD0 M3 O LVCMOS33 TX 1 DSD Audio data 0 FPGA to TX TX 1_DSD1 L4 O LVCMOS33 TX 1 DSD Audio data 1 FPGA to TX TX 1_DSD2 K5 O LVCMOS33 TX 1 DSD Audio data 2 FPGA to TX TX 1_DSD3 K4 O LVCMOS33 TX 1 DSD Audio data 3 FPGA to TX TX 1_DSD4 K3 O LVCMOS33 TX 1 DSD Audio data 4 FPGA to TX TX 1_DSD5 J4 O LVCMOS33 TX 1 DSD Audio data 5 FPGA to TX TX 1_...

Page 46: ...33 DIP switch 1 DSW2 K8 I LVCMOS33 DIP switch 2 DSW3 D5 I LVCMOS33 DIP switch 3 DSW4 E4 I LVCMOS33 DIP switch 4 DSW5 J7 I LVCMOS33 DIP switch 5 DSW6 H8 I LVCMOS33 DIP switch 6 DSW7 B2 I LVCMOS33 DIP switch 7 LED0 G7 O LVCMOS33 LED0 LED1 F7 O LVCMOS33 LED1 LED2 D3 O LVCMOS33 LED2 LED3 C4 O LVCMOS33 LED3 LED4 E5 O LVCMOS33 LED4 LED5 E6 O LVCMOS33 LED5 LED6 A2 O LVCMOS33 LED6 LED7 B3 O LVCMOS33 LED7 ...

Page 47: ...PGA on the TB FMCH HDMI2 TX FMC connector to FPGA data is captured by the FPGA at the rising edge of a video clock Data from the main board is transferred at the falling edge of a video clock HDMITX_CLK VSYNC HSYNC DE DATA FMC FPGA Output data are synchronous with down edge of HDMITX_CLK Figure 5 6 FPGA Input Data Timing ...

Page 48: ...0x1080p 50Hz 5 13 2 3D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format Supported image size 1280x720p 59 94 60Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 50Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 23 98 24Hz Frame Packing 1280x720p 23 97 30Hz Frame Packing 1920x1080i 59 94 60Hz Frame Packing Side by Side Half 1920x1080i 50Hz Frame Packing Si...

Page 49: ...CL 1 2 short Normal JP5 DDC0_SCL 1 2 short Normal JP12 DDC0_GND 1 2 short Normal JP6 DDC0_GND 1 2 short Normal JP3 SCL1 1 2 short Normal JP4 SDA1 1 2 short Normal JP13 DDC1_5V 1 2 short Normal JP12 DDC1_5V 1 2 short Normal JP14 DDC1_HPD 1 2 short Normal JP13 DDC1_HPD 1 2 short Normal JP15 DDC1_SDA 1 2 short Normal JP9 DDC1_SDA 1 2 short Normal JP16 DDC1_SCL 1 2 short Normal JP10 DDC1_SCL 1 2 short...

Page 50: ...4 SDA1 Open JP13 DDC1_5V 1 2 short Normal JP12 DDC1_5V 1 2 short Normal JP14 DDC1_HPD 1 2 short Normal JP13 DDC1_HPD 1 2 short Normal JP15 DDC1_SDA 2 3 short Through JP9 DDC1_SDA 2 3 short Through JP16 DDC1_SCL 2 3 short Through JP10 DDC1_SCL 2 3 short Through JP17 DDC1_GND 2 3 short Through JP11 DDC1_GND 2 3 short Through SG HDMI DDC_SCL DDC_SDA DDC_5V DDC_GND HOTPLUG_DET DDC_SCL DDC_SCA DDC_5V D...

Page 51: ...DMI 2 3 FPGA 3 JP8 1 2 short DDC0_5V 1 2 Normal 2 3 Through 4 JP9 1 2 short DDC0_HPD 1 2 Normal 2 3 Through 5 JP10 1 2 short DDC0_SDA 1 2 Normal 2 3 Through 6 JP11 1 2 short DDC0_SCL 1 2 Normal 2 3 Through 7 JP12 1 2 short DDC0_GND 1 2 Normal 2 3 Through 8 JP3 1 2 short SCL1 1 2 HDMI 2 3 FPGA 9 JP4 1 2 short SDA1 1 2 HDMI 2 3 FPGA 10 JP13 1 2 short DDC1_5V 1 2 Normal 2 3 Through 11 JP14 1 2 short ...

Page 52: ...v 1 05 Table 7 2 TB FMCH HDMI2 RX Default Setting DSW RSW No Silk No Default Setting 1 S1 1 OFF 2 S1 2 OFF 3 S1 3 OFF 4 S1 4 OFF 5 S1 5 OFF 6 S1 6 OFF 7 S1 7 OFF 8 S1 8 OFF 9 S2 0 For the setting at the time of use refer to Table 4 7 Switches ...

Page 53: ...hort DDC0_5V 1 2 Normal 2 3 Through 2 JP8 1 2 short DDC0_HPD 1 2 Normal 2 3 Through 3 JP4 1 2 short DDC0_SDA 1 2 Normal 2 3 Through 4 JP5 1 2 short DDC0_SCL 1 2 Normal 2 3 Through 5 JP6 1 2 short DDC0_GND 1 2 Normal 2 3 Through 6 JP12 1 2 short DDC1_5V 1 2 Normal 2 3 Through 7 JP13 1 2 short DDC1_HPD 1 2 Normal 2 3 Through 8 JP9 1 2 short DDC1_SDA 1 2 Normal 2 3 Through 9 JP10 1 2 short DDC1_SCL 1...

Page 54: ...able 7 4 TB FMCH HDMI2 TX Default Switch Settings DSW RSW No Silk No Default Setting 1 S1 1 OFF 2 S1 2 OFF 3 S1 3 OFF 4 S1 4 OFF 5 S1 5 OFF 6 S1 6 OFF 7 S1 7 OFF 8 S1 8 OFF 9 S2 0 For the setting at the time of use refer to Table 5 7 Switch Function ...

Page 55: ...tial setting TB FMCH HDMI2 TX connects to CN3 TB FMCH HDMI2 TX are initial setting TB 6S LX150T IMG2 JP6 JP7 5 6 Short JP1 1 2 Short JP4 JP5 5 6 Short JP2 1 2 Short Figure 8 1 Usage Example Table 8 1 Setting Example No Silk No Setting Function 1 JP1 1 2 Bank3 voltage setting 2 5V 3 3V 2 JP6 JP7 5 6 FMC LPC2VADJ voltage setting 2 5V 3 3V none Two jumpers must be always the same 3 JP2 1 2 Bank0 volt...

Page 56: ...TB FMCH HDMI2 Hardware User Manual 56 Rev 1 05 ...

Page 57: ...ev 1 05 PLD Solution Dept PLD Division URL http solutions inrevium com E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 ...

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