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Introduction to Digital Power Conversion

XMC4000/1000 Family

Control Loops

Application Guide

V1.0, 2015-01

7.3

Using FADC Compare Mode; Slope Compensation Add-On

The Low-end XMC devices that do not offer an embedded analog comparator are still able to meet
the functionality of current mode control to a greater or lesser extent, by using the Fast Compare
Mode of a VADC:

The inductor signal (I

*[R

]) is slope compensated by an add-on circuit and compared to a fixed digital

reference value that is stored in

the result register ‘x’ of the VADC channel that is used.

Figure 65

Peak Current Mode Control

– VADC Fast Compare Mode – Slope Compensation

Fast VADC Compare Mode (FADC) Properties

Conversion rate is e.g. 150 ns.

Resolution is 10 bit.

Summary of Contents for XMC Series

Page 1: ...Microcontrollers XMC4000 1000 Microcontroller Series for Industrial Applications Application Guide V1 0 2015 01 Introduction to Digital Power Conversion...

Page 2: ...y terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For inform...

Page 3: ...EXGO of Microsoft Corporation FlexRay is licensed by FlexRay Consortium HYPERTERMINAL of Hilgraeve Incorporated IEC of Commission Electrotechnique Internationale IrDA of Infrared Data Association Corp...

Page 4: ...4 1 Single Channel 24 4 2 Single Channel with Complementary Outputs 24 4 3 Dual Channel with Complementary Outputs with Dead Time using CCU8 25 4 4 Dual Channel with Complementary Outputs with Dead Ti...

Page 5: ...pe Compensation Fixed OFF Time FOFFT PCC 71 6 6 CCM CRM CrCM and DCM 72 6 7 CRM PFC using Fixed On Time FOT 74 6 8 CCM DCM PFC using Fixed Off Time FOFFT 75 6 9 CCM PFC example using Average Current M...

Page 6: ...visiting the basics of electric energy transfer and creating a summarized picture of what can be achieved today with a weighted mix of embedded dedicated peripherals and computing power 1 2 Intendend...

Page 7: ...cy Converter 2 2 Why Power Conversion According to the global environmental context each case of electric energy transfer between an energy source and an energy consuming unit should consume as little...

Page 8: ...e conversion properties in any way i e the steady state input to output transfer function is not adjustable in runtime The consequence of this is Load dependent output voltage Active Linear Conversion...

Page 9: ...property is not covered by any Linear Voltage Converter so most power conversion use cases can be solved by Switch Mode especially in the area of high power where efficiency and form factor are vital...

Page 10: ...true for any DC DC converter topology Interesting similarities with linear conversion can be seen in the output input voltage ratios when replacing R with T This comparison is true as long as the mag...

Page 11: ...ficiency 2 3 2 2 Digital Switch Mode Controllers Digital controllers are flexible with a wide load input range and sophisticated reactions to condition changes during run time through multi control lo...

Page 12: ...run time and reusability is limited because they are a customized solution Positive properties Custom design for known conditions Fixed and optimized settings Lowest possible cost Easy to use Embedded...

Page 13: ...ower converter topology Advanced analog and digital peripherals interact on events in real time via a hardware matrix supported by DMA Software DSP Digital Signal Processing or over a network Figure 4...

Page 14: ...speed and sampling timing 4 independent converters with up to 8 inputs w channel wise selectable reference voltage source 2 4 1 2 Stability and Software An important property of conversion control lo...

Page 15: ...by Symmetric Asymmetric Modulation Edge Aligned or Center Aligned with Active Passive Output Level Control Trap Handling Protocol in hardware with Dithering 4 bits by Status Events by Compare or Perio...

Page 16: ...own Section 3 1 Conventional Interleaved Synchronous Inverted Boost Step Up Section 3 2 Conventional Interleaved Synchronous Inverted Buck Boost PFC Power Factor Correction Section 3 3 Conventional Bo...

Page 17: ...the output currents from a multiphase Buck converter stage For example a 2 phase Buck converter controlled by fixed 180o phase shifted PWM from an XMC CCU4 8 Synchronous Buck Converter When reduced p...

Page 18: ...Boost Interleaved Boost Converter Similar to the Buck converter i e the ripple will be reduced and smaller components can be used by having interleaved output currents from a multiphase Boost convert...

Page 19: ...he current conduction angle becomes fully 180o in both half periods phase correct to the mains AC voltage i e without any parasitic or reactive signal components reflected back into the mains lines Se...

Page 20: ...geless Totem pole PFC Performance High Power Factor PF and low Total Harmonic Distortion THD are directly related so the basic circuits can be listed in performance order as follows Conventional Boost...

Page 21: ...two A transformer which is fed onto its primary coil np with the phase difference voltage PhA PhB This difference voltage will be transformed with a ratio ns np to two secondary coils ns ns Stage thre...

Page 22: ...Principle Using Half Bridge Control Performance A resonant converter enables high voltage and faster switching which allows for smaller components thanks to the reduced switching losses An LLC convert...

Page 23: ...a some rectifier and capacitor C filter configuration Because of this property the essential components and control loops for Switch Mode DC DC power converters can be described by a Generic DC DC Con...

Page 24: ...external events even if stopped timer An output can be set active high or low and with Dead Time in CC8 Figure 12 PWM Single Channel 4 2 Single Channel with Complementary Outputs A single channel Ch1...

Page 25: ...ple is a CCU4 Full Bridge drive with complementary outputs and individual Deadtimes see Figure 15 PWM with Complementary Outputs by Using CCU4 Single Shot Timers A complementary PWM output pair can be...

Page 26: ...mer pair Updates are via period shadow registers by compare ISR and are set on shadow transfers Figure 15 PWM Dual Channel Complementary Outputs w Individual Deadtime PWM Phase Shift Control by Extern...

Page 27: ...configurations variable frequency and or PWM pattern control is easily accomplished Figure 16 PWM On Off Control by External Events 4 6 Fixed ON Time FOT Fixed On Time FOT PWM has two essential prope...

Page 28: ...e fmax min timer add ons in the loop Figure 18 FOT Control with Frequency Limits Supervision The FOT Timer Slice1 Assume that this single shot FOT timer works in a CRM or DCM mode PFC controller In ea...

Page 29: ...ction required to keep track of a ZCD event that might happen before a FOT pulse is allowed to start due to the fmax period restriction Instead of using an ERU a timer slice Slice3 can be used to defi...

Page 30: ...l begin and end with the status bit of all timers 0 i e ST0 0 ST1 0 ST2 0 ST3 0 3 consequently the successive event will follow 4 a parallel synchronous event flow connected to the root event 5 STn ST...

Page 31: ...ter by a load timer request on a peak detection event From this event until period match the rest of the timer cycle is a fixed time period value minus compare value FOFFT mode with On Time Limitation...

Page 32: ...er components EMC quality is also improved Variable Phase Shift This is used for DC DC conversion applications and for energy transfer adaption and isolation by using a transformer in the path The cha...

Page 33: ...d Phase Shift in Edge Aligned Mode for Interleave Start up sequence During the start up phase the duty cycle of CC40 is set to 0 by pre setting a high compare level exceeding the period register value...

Page 34: ...e approach offers reduced current ripple and a continuous current flow into the rectifier and filter output stage of the converter A higher frequency and smaller components can be used This concept is...

Page 35: ...ignal pair should be generated by one master timer that can guarantee a fixed PWM pulse rate and one slave timer in single shot mode for the phase shifted PWM pulses which should be controlled by the...

Page 36: ...re channels can be used as a master for the PSFB control as follows Channel1 The CC80CR1 compare events control the phase shift of the PWM pulse stream S from a slave timer e g CC81 by requesting one...

Page 37: ...guration is used with synchronous rectification with the switch pair Q3 Q4 as an efficient replacement for diodes by offering lower voltage drop The switch pair Q3 Q4 rectifies and interleaves the pos...

Page 38: ...time and to keep the free wheeling current polarity unchanged Free wheeling Current Control by Active Clamp When the upper or the lower switches are conducting simultaneously due to the phase shift t...

Page 39: ...ach one of the High Resolution channels is capable of addressing up to 2 complementary MOSFET switches and Set Clear may be mapped to different sources Flexible Set Clear Switch in Runtime Any combina...

Page 40: ...mode from one switch cycle to another This is useful for adapting to load variations The XMC devices make use of this in order to maintain an optimized efficiency Figure 29 Dead Time Compensation Upd...

Page 41: ...a pair of Inter connected CCU4 Slices in Single Shot Mode Figure 30 Half Bridge LLC Converter Using CCU4 50 duty cycle and center aligned modulation referenced to the sinusoidal voltage zero crossings...

Page 42: ...ntrol by Matrix Interaction Paths in the Timer Cell Pair Setup with CC40 41 and CC42 43 All four timers work in single shot mode The CC40 41 timer pair interacts by alternating start requests on a per...

Page 43: ...l CC80 is master of the synchronous rectifier CC42 43 Note The slices CC42 43 in this example can be replaced by a CCU8 slice configuration Figure 32 Full Bridge LLC Control w Synchronous Rectificatio...

Page 44: ...ncluding a phase adjustable synchronous rectification for alignment to the sinusoidal current phase Figure 33 PWM Full Bridge LLC Control Phase Adjusted High Resolution Rectification Adjusting the Syn...

Page 45: ...e acting as a type of mailbox for every new phase shift Ref CC8yTC TLS register The phase shift procedure after the interconnectivity for the timer load function is setup is as follows Each new phase...

Page 46: ...nerator with embedded 10 bit DAC DSD ADC Delta Sigma De modulator Analog to Digital Converter Uses Sensing is essential for the closed loop control of the converter transfer functions In the closed lo...

Page 47: ...using a VADC channel in Fast Compare mode for analog threshold sensing the input voltage is directly compared with a digital value in the result register resulting in a single bit above below comparis...

Page 48: ...ntrol Using Fast Compare mode This type of sensing is called Peak Detection i e the detection event occurs when the analog signal has ramped up to and crosses a defined level In this example the lower...

Page 49: ...In this example the selected Valley Detection level is Zero To utilize the hysteresis effectively map Hysteresis to the upper boundary 0 Reference to the lower boundary 1 close to 0 Figure 37 Sensing...

Page 50: ...alog input signal has a freely programmable position and size within the entire result range The settings should be mapped in two boundary registers 0 1 Out of Range will set a BFL if the correspondin...

Page 51: ...Inherent feed back Low accuracy higher cost Fast w o CPU Voltage Control Voltage Mode Control implies that the actual output voltage deviation from the desired output voltage i e an error voltage fee...

Page 52: ...y PWM from a CCU driving the switch Q The feed back function of the VC loop modulates D so that the target output voltage is maintained Figure 39 Modulation Voltage Mode Control Buck Converter Steady...

Page 53: ...loop drive process marked by a yellow background in the following figure is repeated with a time constant of n loop cycles while the sensing and averaging of VOUT is processed each cycle In Voltage C...

Page 54: ...ed by the H z transfer compensating software using DSP operations on discrete time variables maintained by the Interrupt Service Request ISR provider stimulated by the VADC result stream due to the co...

Page 55: ...urrent in a very easy and cost effective way The current is monitored over a resistor s R voltage drop VR to ground Steady State Transfer Function The steady state duty cycle to output IOUT is the ind...

Page 56: ...triggered by the CCU8 timer and determines the time constant of the feedback control in the loop i e the loop might be very slow depending on the accuracy requirements 6 2 2 Average Current Control E...

Page 57: ...uccessive PWM cycles by an updated Next CR1 CR2 setup Steady State Frequency Response in ACC Loop The ACC loop is described by the Sense Loop Drive shown in blue in the previouis figure The loop is re...

Page 58: ...e on a Zero Crossing Detection ZCD Such events will frontload the PWM on time start and shorten the PWM cycle period increasing the duty cycle intermediately ahead of the software reaction Figure 43 A...

Page 59: ...atch which occurs at the IL point where IOUT Avrg is due The CPU load is low in this mode but at the cost of resolution Figure 44 Average Current Control ACC Timing Scheme Center Aligned Mode Accuracy...

Page 60: ...analog front end with comparator capability i e VADC in Fast Compare mode ACMP or a CSG with Slope Generator The VOUT D VIN transfer function is maintained by a variable duty cycle D of the PWM cycle...

Page 61: ...CC Modulation Terms PCC modulation is noise sensitive The On Time is unpredictable and has to be overall controlled D 50 causes sub oscillations that must be damped by peak current reference Slope Com...

Page 62: ...Note 3 Because it has been simplified the PCC illustrated here does not include the peak current reference Slope Compensation technique 4 Since there is a fixed frequency PWM i e with a fixed cycle l...

Page 63: ...embedded blanking timer Figure 47 Blanking principle Example Filtering A filter on the analog comparator output rejects unwanted OFF switching due to EMI noise during switch ON signal sensing This fi...

Page 64: ...current mode control loop test by a theoretical inductor current IL Step Response the test will disclose the conditions and the necessity for Slope Compensation i e when instability might occur and c...

Page 65: ...rent Slope Compensation There are 2 examples in the next figure The example at the top demonstrates the necessity of an aligning Peak Current that follows the input voltage variations e g from VIN1 to...

Page 66: ...her No SW is involved Figure 50 Slope Compensation VIN independent Average Current Mode Control PCC Inductor Current and Slope Compensation characteristics for Fixed Average Current PPC 1 Define the a...

Page 67: ...Stability Condition 1 For PCC in CCM the inductor current IL might run into sub harmonic oscillations depending on the system conditions One of those conditions is the duty cycle D If D 0 5 and there...

Page 68: ...stage of the loop This enables adjustable damping of oscillations However the damping factor is duty cycle D dependent and so impacted by VIN variations Maintaining Slope Compensation See Figure 51 T...

Page 69: ...AX will limit the range of the duty cycle to output voltage transfer function operating points The area below the Slope Compensation ramp and below DMAX is satisfying a so called Stable Area The bound...

Page 70: ...est the slope compensation ramp is hit by a different inductor current characteristic starting in Cycle n Stability is disclosed by a perturbing IL step test Figure 53 PCC Stability Considering Outsid...

Page 71: ...etection Mode Control where the current reflections are forced in to stability by the Fixed On Time term Figure 55 Modulation ZCD FOT Stability Recovered w o Slope Compensation 6 5 7 Without Slope Com...

Page 72: ...reaches zero there will be no current until the loading phase appears again This phenomenon defines three different current modulation state modes Continuous Conduction Mode CCM The current is always...

Page 73: ...rent of T if it would occur for example due to decreasing load else d 0 Average Current Depending on the Current Conduction Mode The only difference between CCM and CRM is a load dependent DC componen...

Page 74: ...nductor current hits the ZCD point again after each pulse This kind of control satisfies CRM This type of PFC rectifier does not need a feed forward sensing at the input side to be aligned with the si...

Page 75: ...rent PCC level With this kind of control the inductor current ripples along the average current envelope satisfying CCM except the DCM close to zero The Peak Current has to be aligned with the sinusoi...

Page 76: ...er EMC conditions for high power converters There is a higher loop gain in ACC compared to the loop gain in PCC This is due to the integration of the error signal in the feed back loop algorithm that...

Page 77: ...ential Sense and PWM Drive capability there are advanced modulation add on qualities 7 1 Using CSG HRPWM with an Internal Comparator and Slope Generator This scheme can represent current mode control...

Page 78: ...pt is applicable in any Mid to Low end DC DC converter using current mode control modulation even in combined peak valley detection with two ACMP channels In the following example a PCC is used Extern...

Page 79: ...o ACMP N from a CCU 4 as DAC via RC filter The SC Ramp is PWM aligned Blanking is controlled via ACMP P See Figure 64 ACMP PCC Slope Compensation Circuit Clarification Example By using RC networks the...

Page 80: ...tage and the Current Measurement voltage are added via a respective resistor to the ACMP P input and so invoke Slope Compensation Each time the CCU 4 Slope Compensation MOSFET is ON it discharges the...

Page 81: ...nctionality of current mode control to a greater or lesser extent by using the Fast Compare Mode of a VADC The inductor signal IL Ri is slope compensated by an add on circuit and compared to a fixed d...

Page 82: ...of a slope compensation voltage ramp Figure 66 ACMP PCC Slope Compensation Clarification CCU 4 Blanking Control There is a CCU 4 blanking control to reject noise from power switch commutations propose...

Page 83: ...ns in HCF is via the ADC HADC feedback path compared with the input VREF The difference error is forced towards 0 by the closed open loop gain path HADC can have delay and gain impact but this is assu...

Page 84: ...a function of frequency will fall by 40 dB decade above the cutoff frequency until the slope hits the ESR Equivalent Serial Resistance point frequency after which the slope will be reduced to 20 dB d...

Page 85: ...in is a product of the following transfer functions HADC s HIII s HDC s HHF s HLP s Assume HADC s 1 Bode Plot The vertical co ordinate of the Bode Plot diagram is logarithmic in dB decibel scale The a...

Page 86: ...current IL with a DC gain Ri R and a 1st order frequency function with 1 pole due to the Slope Compensation operating point plus the RC circuit damping factor and 1 zero at 1 RCC due to the time const...

Page 87: ...Plot The vertical co ordinate of the Bode Plot diagram is logarithmic in dB decibel scale The absolute value of the total transfer function will be plotted according to HII s HDC s HHF s HSS s dB This...

Page 88: ...he correct procedure to put it in MPPT Maximum Power Point Tracking MPPT is a technique to get the maximum possible power from energy sources for example Solar cells that produce non linear output eff...

Page 89: ...frames with 11 bit identifiers as well as extended frames with 29 bit identifiers Exchangable data and remote frames via a gateway functions optionally supported by message FIFO buffers USB Universal...

Page 90: ...point for the steady state duty cycle to output transfer function is VOUT D1VIN1 and sC1 is chosen for a desired damping influence by a chosen constant const1 then if the input voltage is changed to V...

Page 91: ...U Central Processing Unit CRM Critical Conduction Mode CrCM CSGy Comparator and Slope Generator unit instance y DAC Digital to Analog Converter DC Direct Current DCM Discontinuous Current Mode DMA Dir...

Page 92: ...ions table continued PCC Peak Current Mode Control PFC Power Factor Correction filter PFM Pulse Frequency Modulation PSFB Phase Shift Full Bridge PWM Pulse Width Modulation SG Slope Generator SR Synch...

Page 93: ...Published by Infineon Technologies AG w w w i n f i n e o n c o m...

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