Introduction to Digital Power Conversion
XMC4000/1000 Family
Modulation
Application Guide
59
V1.0, 2015-01
6.2.4
ACC Center Aligned Scheme
In this diagram the CCU4/8 slice timer works in center aligned mode.
The average current is sensed via the VADC connection to the current sensor each time the timer hits
period-match, which occurs at the "
∆I
L
” point where I
OUT
(Avrg) is due.
The CPU load is low in this mode, but at the cost of resolution.
Figure 44
Average Current Control (ACC)
– Timing Scheme – Center Aligned Mode
Accuracy Considerations
Center aligned mode “costs” an accuracy reduction of factor two.
If for example the compare level is changed by one, then the duty-cycle is changed in steps of two
(due to the impact from both rising and falling sides).
This disadvantage can be overcome by incorporating the High Resolution PWM unit (HRPWM).
