Infineon TRAVEO T2G Technical Reference Manual Download Page 1779

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Technical Reference Manual

002-29852 Rev. *B

Register Name

Address

Permission Description

TCPWM0_GRP0_CNT60_STATUS

0x40381E04 FULL

Counter status register

Note:DT_CNT_H is not available for this register

TCPWM0_GRP0_CNT60_COUNTER

0x40381E08 FULL

Counter count register

TCPWM0_GRP0_CNT60_CC0

0x40381E10 FULL

Counter compare/capture 0 register

TCPWM0_GRP0_CNT60_CC0_BUFF

0x40381E14 FULL

Counter buffered compare/capture 0 register

TCPWM0_GRP0_CNT60_CC1

0x40381E18 FULL

Counter compare/capture 1 register

TCPWM0_GRP0_CNT60_CC1_BUFF

0x40381E1C FULL

Counter buffered compare/capture 1 register

TCPWM0_GRP0_CNT60_PERIOD

0x40381E20 FULL

Counter period register

TCPWM0_GRP0_CNT60_PERIOD_BUFF

0x40381E24 FULL

Counter buffered period register

TCPWM0_GRP0_CNT60_DT

0x40381E30 FULL

Counter PWM dead time register

Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register

TCPWM0_GRP0_CNT60_TR_CMD

0x40381E40 FULL

Counter trigger command register

TCPWM0_GRP0_CNT60_TR_IN_SEL0

0x40381E44 FULL

Counter input trigger selection register 0

TCPWM0_GRP0_CNT60_TR_IN_SEL1

0x40381E48 FULL

Counter input trigger selection register 1

TCPWM0_GRP0_CNT60_TR_IN_EDGE_SEL

0x40381E4C FULL

Counter input trigger edge selection register

TCPWM0_GRP0_CNT60_TR_PWM_CTRL

0x40381E50 FULL

Counter trigger PWM control register

TCPWM0_GRP0_CNT60_TR_OUT_SEL

0x40381E54 FULL

Counter output trigger selection register

TCPWM0_GRP0_CNT60_INTR

0x40381E70 FULL

Interrupt request register

TCPWM0_GRP0_CNT60_INTR_SET

0x40381E74 FULL

Interrupt set request register

TCPWM0_GRP0_CNT60_INTR_MASK

0x40381E78 FULL

Interrupt mask register

TCPWM0_GRP0_CNT60_INTR_MASKED

0x40381E7C FULL

Interrupt masked request register

28.1.62 CNT 61

Register Name

Address

Permission Description

TCPWM0_GRP0_CNT61_CTRL

0x40381E80 FULL

Counter control register

Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register

TCPWM0_GRP0_CNT61_STATUS

0x40381E84 FULL

Counter status register

Note:DT_CNT_H is not available for this register

TCPWM0_GRP0_CNT61_COUNTER

0x40381E88 FULL

Counter count register

TCPWM0_GRP0_CNT61_CC0

0x40381E90 FULL

Counter compare/capture 0 register

TCPWM0_GRP0_CNT61_CC0_BUFF

0x40381E94 FULL

Counter buffered compare/capture 0 register

TCPWM0_GRP0_CNT61_CC1

0x40381E98 FULL

Counter compare/capture 1 register

TCPWM0_GRP0_CNT61_CC1_BUFF

0x40381E9C FULL

Counter buffered compare/capture 1 register

TCPWM0_GRP0_CNT61_PERIOD

0x40381EA0 FULL

Counter period register

TCPWM0_GRP0_CNT61_PERIOD_BUFF

0x40381EA4 FULL

Counter buffered period register

TCPWM0_GRP0_CNT61_DT

0x40381EB0 FULL

Counter PWM dead time register

Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register

TCPWM0_GRP0_CNT61_TR_CMD

0x40381EC0 FULL

Counter trigger command register

TCPWM0_GRP0_CNT61_TR_IN_SEL0

0x40381EC4 FULL

Counter input trigger selection register 0

TCPWM0_GRP0_CNT61_TR_IN_SEL1

0x40381EC8 FULL

Counter input trigger selection register 1

TCPWM0_GRP0_CNT61_TR_IN_EDGE_SEL

0x40381ECC FULL

Counter input trigger edge selection register

TCPWM0_GRP0_CNT61_TR_PWM_CTRL

0x40381ED0 FULL

Counter trigger PWM control register

TCPWM0_GRP0_CNT61_TR_OUT_SEL

0x40381ED4 FULL

Counter output trigger selection register

TCPWM0_GRP0_CNT61_INTR

0x40381EF0 FULL

Interrupt request register

TCPWM0_GRP0_CNT61_INTR_SET

0x40381EF4 FULL

Interrupt set request register

TCPWM0_GRP0_CNT61_INTR_MASK

0x40381EF8 FULL

Interrupt mask register

TCPWM0_GRP0_CNT61_INTR_MASKED

0x40381EFC FULL

Interrupt masked request register

28.1.63 CNT 62

Register Name

Address

Permission Description

TCPWM0_GRP0_CNT62_CTRL

0x40381F00 FULL

Counter control register

Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register

TCPWM0_GRP0_CNT62_STATUS

0x40381F04 FULL

Counter status register

Note:DT_CNT_H is not available for this register

TCPWM0_GRP0_CNT62_COUNTER

0x40381F08 FULL

Counter count register

TCPWM0_GRP0_CNT62_CC0

0x40381F10 FULL

Counter compare/capture 0 register

TCPWM0_GRP0_CNT62_CC0_BUFF

0x40381F14 FULL

Counter buffered compare/capture 0 register

1779

2022-04-18

TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

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Summary of Contents for TRAVEO T2G

Page 1: ...II B E 4M body controller entry registers Technical reference manual About this document Scope and purpose The TRAVEO T2G body controller entry registers TRM provides reference information for registe...

Page 2: ...s privilege mode Read access Non secure yes PRIVILEGE WRITE User mode Read access privilege mode Read and Write access Non secure yes NO ACCESS User mode No access Privilege mode No access Non secure...

Page 3: ...Register contents Every bit is cleared upon writing 1 Software read and write 1 to clear RW0C any Register contents Every bit is cleared upon writing 0 Software read and write 0 to clear RW1SC any NA...

Page 4: ...dware read and set clear any W Write access only any W1S Hardware set any W0S Hardware set any W1C Hardware clear any W0C Hardware clear any W1SC Hardware set clear any W0SC Hardware set clear R A Not...

Page 5: ...egion i e holes may be present in the region Memory structures This includes generic memory structures such as system FLASH system RAM and system ROM but also IP specific memory structures Transfer to...

Page 6: ...512 CYT2BL4CAS 80 LQFP 4160 128 512 CYT2BL4CAE 80 LQFP 4160 128 512 CYT2BL5BAS 100 LQFP 4160 128 512 CYT2BL5BAE 100 LQFP 4160 128 512 CYT2BL5CAS 100 LQFP 4160 128 512 CYT2BL5CAE 100 LQFP 4160 128 512...

Page 7: ...WM 0x40380000 Timer Counter PWM EVTGEN 0x403f0000 Event generator MMIO5 LIN 0x40500000 LIN CXPI 0x40510000 CXPI CANFD 0 0x40520000 CAN Controller CANFD 1 0x40540000 CAN Controller MMIO6 SCB 0 0x406000...

Page 8: ...7001C FULL Alarm 1 Seconds Minute Hours Day of Week BACKUP_ALM1_DATE 0x40270020 FULL Alarm 1 Day of Month Month BACKUP_ALM2_TIME 0x40270024 FULL Alarm 2 Seconds Minute Hours Day of Week BACKUP_ALM2_DA...

Page 9: ...g any component that depends on clk_lf clk_bak like for example RTC or WDTs Follow the procedure in BACKUP_RTC_RW to access this bit 8 9 CLK_SEL RW A 0 Clock select for RTC clock WCO 0 Watch crystal o...

Page 10: ...ystal Connect a 32 768 kHz watch crystal between WCO input and output pins 1 Clock signal either a square wave or sine wave See PRESCALER field for connection information 17 18 VDDBAK_CTL RW A 0 Contr...

Page 11: ...Do not set the Read bit at the same time that the Write bit is cleared 1 WRITE RW A 0 Write bit Only when this bit is set can the RTC registers be written to otherwise writes are ignored This bit can...

Page 12: ...ues 0x01 0x3c 1 60 add pulses negative values remove pulses thus giving a range of 65 1 ppm limited by 60 minutes per hour not the range of this field Calibration is performed hourly starting at 59 mi...

Page 13: ...7 6 5 4 3 2 1 0 Name None 7 3 WCO_OK 2 2 None 1 1 RTC_BUSY 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit...

Page 14: ...e None 15 14 RTC_MIN 13 8 Bits 23 22 21 20 19 18 17 16 Name None 23 23 CTRL _12HR 22 22 None 21 21 RTC_HOUR 20 16 Bits 31 30 29 28 27 26 25 24 Name None 31 27 RTC_DAY 26 24 Bit fields Bits Name SW HW...

Page 15: ...nto these registers Default 0x101 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 RTC_DATE 4 0 Bits 15 14 13 12 11 10 9 8 Name None 15 12 RTC_MON 11 8 Bits 23 22 21 20 19 18 17 16 Name None 23 23 R...

Page 16: ...19 18 17 16 Name ALM _HOUR_EN 23 23 None 22 21 ALM_HOUR 20 16 Bits 31 30 29 28 27 26 25 24 Name ALM_DAY _EN 31 31 None 30 27 ALM_DAY 26 24 Bit fields Bits Name SW HW Default or Enum Description 0 5 A...

Page 17: ...its 31 30 29 28 27 26 25 24 Name ALM_EN 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 ALM_DATE RW A 1 Alarm Day of the Month 1 31 Leap Year corrected 7 ALM_DATE_EN RW A 0...

Page 18: ...19 18 17 16 Name ALM _HOUR_EN 23 23 None 22 21 ALM_HOUR 20 16 Bits 31 30 29 28 27 26 25 24 Name ALM_DAY _EN 31 31 None 30 27 ALM_DAY 26 24 Bit fields Bits Name SW HW Default or Enum Description 0 5 A...

Page 19: ...Bits 31 30 29 28 27 26 25 24 Name ALM_EN 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 ALM_DATE RW A 1 Alarm Day of the Month 1 31 Leap Year corrected 7 ALM_DATE_EN RW A...

Page 20: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 CENTURY 2 2 ALARM2 1 1 ALARM1 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27...

Page 21: ...1 ALARM1 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description...

Page 22: ...2 ALARM2 1 1 ALARM1 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum D...

Page 23: ...Bits 7 6 5 4 3 2 1 0 Name None 7 3 CENTURY 2 2 ALARM2 1 1 ALARM1 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 2...

Page 24: ...4 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name RESET 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 31 RESET R...

Page 25: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name BREG 7 0 Bits 15 14 13 12 11 10 9 8 Name BREG 15 8 Bits 23 22 21 20 19 18 17 16 Name BREG 23 16 Bits 31 30 29 28 27 26 25 24 Name BREG 31 24 Bit fields Bits N...

Page 26: ...ominal Bit Timing Prescaler Register CANFD0_CH0_TSCC 0x40520020 FULL Timestamp Counter Configuration CANFD0_CH0_TSCV 0x40520024 FULL Timestamp Counter Value CANFD0_CH0_TOCC 0x40520028 FULL Timeout Cou...

Page 27: ...FULL TT Capture Time CANFD0_CH0_TTCSM 0x40520140 FULL TT Cycle Sync Mark 2 1 2 CH 1 Register Name Address Permission Description CANFD0_CH1_RXFTOP_CTL 0x40520380 FULL Receive FIFO Top control CANFD0_...

Page 28: ...Limits CANFD0_CH1_TURCF 0x40520310 FULL TUR Configuration CANFD0_CH1_TTOCN 0x40520314 FULL TT Operation Control CANFD0_CH1_TTGTP 0x40520318 FULL TT Global Time Preset CANFD0_CH1_TTTMK 0x4052031C FULL...

Page 29: ...L Tx Buffer Cancellation Finished CANFD0_CH2_TXBTIE 0x405204E0 FULL Tx Buffer Transmission Interrupt Enable CANFD0_CH2_TXBCIE 0x405204E4 FULL Tx Buffer Cancellation Finished Interrupt Enable CANFD0_CH...

Page 30: ...4 FULL Rx FIFO 1 Status CANFD0_CH3_RXF1A 0x405206B8 FULL Rx FIFO 1 Acknowledge CANFD0_CH3_RXESC 0x405206BC FULL Rx Buffer FIFO Element Size Configuration CANFD0_CH3_TXBC 0x405206C0 FULL Tx Buffer Conf...

Page 31: ...028 FULL Timeout Counter Configuration CANFD1_CH0_TOCV 0x4054002C FULL Timeout Counter Value CANFD1_CH0_ECR 0x40540040 FULL Error Counter Register CANFD1_CH0_PSR 0x40540044 FULL Protocol Status Regist...

Page 32: ...mission Description CANFD1_CH1_RXFTOP_CTL 0x40540380 FULL Receive FIFO Top control CANFD1_CH1_RXFTOP0_STAT 0x405403A0 FULL Receive FIFO 0 Top Status CANFD1_CH1_RXFTOP0_DATA 0x405403A8 FULL Receive FIF...

Page 33: ...rol CANFD1_CH1_TTGTP 0x40540318 FULL TT Global Time Preset CANFD1_CH1_TTTMK 0x4054031C FULL TT Time Mark CANFD1_CH1_TTIR 0x40540320 FULL TT Interrupt Register CANFD1_CH1_TTIE 0x40540324 FULL TT Interr...

Page 34: ...Interrupt Enable CANFD1_CH2_TXBCIE 0x405404E4 FULL Tx Buffer Cancellation Finished Interrupt Enable CANFD1_CH2_TXEFC 0x405404F0 FULL Tx Event FIFO Configuration CANFD1_CH2_TXEFS 0x405404F4 FULL Tx Eve...

Page 35: ...FD1_CH3_RXF1A 0x405406B8 FULL Rx FIFO 1 Acknowledge CANFD1_CH3_RXESC 0x405406BC FULL Rx Buffer FIFO Element Size Configuration CANFD1_CH3_TXBC 0x405406C0 FULL Tx Buffer Configuration CANFD1_CH3_TXFQS...

Page 36: ...s directly driven by these bits 31 MRAM_OFF RW R 0 MRAM off 0 Default MRAM on with MRAM retained in DeepSleep 1 Switch MRAM off not retained to save power Before setting this bit all the CAN channels...

Page 37: ...5 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 STOP_ACK R RW 0 Clock Stop Acknowledge for each...

Page 38: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name INT0 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit...

Page 39: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name INT1 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit...

Page 40: ...16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLED 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 PRESCALE RW R 0 Time Stamp counter prescale value When enable...

Page 41: ...0 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 VALUE RW A 0 The counter val...

Page 42: ...0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 17 ECC_EN 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or...

Page 43: ...l is done to this address When the ERR_EN bit is set and the access address matches ERR_ADDR then a non correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown...

Page 44: ...19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 F0TPE RW R 0 FIFO 0 Top Pointer Enable This enables the FIFO top poin...

Page 45: ...15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 F0TA R RW 0 Current FIFO 0 Top Address This i...

Page 46: ...data from MRAM at location FnTA This register can have a read side effect if the following conditions are met M_TTCAN not being reconfigured CCCR CCE 0 FIFO Top Pointer logic is enabled FnTPE 1 FIFO...

Page 47: ...omment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name F1TA 7 0 Bits 15 14 13 12 11 10 9 8 Name F1TA 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 2...

Page 48: ...t if read from debug host Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name F1TD 7 0 Bits 15 14 13 12 11 10 9 8 Name F1TD 15 8 Bits 23 22 21 20 19 18 17 16 Name F1TD 23 16 Bits 31 30 29 28 27 26 2...

Page 49: ...SW HW Default or Enum Description 0 7 DAY R R 0 Time Stamp Day Two digits BCD coded This field is set by generic parameter on M_TTCAN synthesis 8 15 MON R R 0 Time Stamp Month Two digits BCD coded Th...

Page 50: ...Table Bits 7 6 5 4 3 2 1 0 Name ETV 7 0 Bits 15 14 13 12 11 10 9 8 Name ETV 15 8 Bits 23 22 21 20 19 18 17 16 Name ETV 23 16 Bits 31 30 29 28 27 26 25 24 Name ETV 31 24 Bit fields Bits Name SW HW Def...

Page 51: ...sample point 0x0 0xF Valid values are 0 to 15 The actual interpretation by the hardware of this value is such that one more than the programmed value is used 8 12 DTSEG1 RW R 10 Data time segment befo...

Page 52: ...h the signal from the FSE 0 Level at pin m_ttcan_asct controlled by FSE 1 Level at pin m_ttcan_asct 1 2 CAM RW R 0 ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at outpu...

Page 53: ...1 10 9 8 Name WDV 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 WDC RW R 0 Watchdog Configur...

Page 54: ...2 ASM RW R 0 Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to 1 The bit can be reset by the Host at any time For a description of the Restricted Operati...

Page 55: ...l exception handling enabled 1 Protocol exception handling disabled 13 EFBI RW R 0 Edge Filtering during Bus Integration 0 Edge filtering disabled 1 Two consecutive dominant tq required to detect an e...

Page 56: ...this value is such that one more than the programmed value is used 8 15 NTSEG1 RW R 10 Nominal Time segment before sample point 0x01 0xFF Valid values are 1 to 255 The actual interpretation by the ha...

Page 57: ...SW HW Default or Enum Description 0 1 TSS RW R 0 Timestamp Select should always be set to external timestamp counter 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented acc...

Page 58: ...its Name SW HW Default or Enum Description 0 15 TSC RW R 0 Timestamp Counter not used for M_TTCAN The internal external Timestamp Counter value is captured on start of frame both Rx and Tx When TSCC T...

Page 59: ...r disabled 1 Timeout Counter enabled 1 2 TOS RW R 0 Timeout Select When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC TOP and continues down counting...

Page 60: ...7 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 TOC RW R 65535 Timeout Counter The Timeout Counter is decremented in multi...

Page 61: ...state of the Transmit Error Counter values between 0 and 255 8 14 REC R RW 0 Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127 15 RP R RW 0 Receive Error Passive...

Page 62: ...ead from debug host Default 0x707 Bit field Table Bits 7 6 5 4 3 2 1 0 Name BO 7 7 EW 6 6 EP 5 5 ACT 4 3 LEC 2 0 Bits 15 14 13 12 11 10 9 8 Name None 15 15 PXE 14 14 RFDF 13 13 RBRS 12 12 RESI 11 11 D...

Page 63: ...ce of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence indicating the bus is not stuck at dominant or continuously disturbed 6 CRCEr...

Page 64: ...DF independent of acceptance filtering 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set 13 RFDF R RW1C 0 Received a CAN FD Message Reset...

Page 65: ...Description 0 6 TDCF RW R 0 Transmitter Delay Compensation Filter Window Length 0x00 0x7F Defines the minimum value for the SSP position dominant edges on m_ttcan_rx that would result in an earlier S...

Page 66: ...ed 0 Rx FIFO 0 fill level below watermark 1 Rx FIFO 0 fill level reached watermark 2 RF0F RW1C RW 0 Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full 3 RF0L_ RW1C RW 0 Rx FIFO 0 Message Lost 0 No R...

Page 67: ...ng message has been received In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message was not able to write a message to the Messag...

Page 68: ...ssive 0 Error_Passive status unchanged 1 Error_Passive status changed 24 EW_ RW1C RW 0 Warning Status 0 Error_Warning status unchanged 1 Error_Warning status changed 25 BO_ RW1C RW 0 Bus_Off Status 0...

Page 69: ...upt Disabled 1 Interrupt Enabled 1 RF0WE RW R 0 Rx FIFO 0 Watermark Reached Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 2 RF0FE RW R 0 Rx FIFO 0 Full Interrupt Enable 0 Interrupt Disable...

Page 70: ...W R 0 Timeout Occurred Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 19 DRXE RW R 0 Message stored to Dedicated Rx Buffer Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 20 BECE...

Page 71: ...29852 Rev B Bits Name SW HW Default or Enum Description 29 ARAE RW R 0 Access to Reserved Address Enable 0 Interrupt Disabled 1 Interrupt Enabled 71 2022 04 18 TRAVEO T2G Automotive MCU TVII B E 4M b...

Page 72: ...d by ILE EINT0 1 Assign to interrupt enabled by ILE EINT1 1 RF0WL RW R 0 Rx FIFO 0 Watermark Reached Interrupt Select 0 Assign to interrupt enabled by ILE EINT0 1 Assign to interrupt enabled by ILE EI...

Page 73: ...T0 1 Assign to interrupt enabled by ILE EINT1 18 TOOL RW R 0 Timeout Occurred Interrupt Select 0 Assign to interrupt enabled by ILE EINT0 1 Assign to interrupt enabled by ILE EINT1 19 DRXL RW R 0 Mess...

Page 74: ...ata Phase Select 0 Assign to interrupt enabled by ILE EINT0 1 Assign to interrupt enabled by ILE EINT1 29 ARAL RW R 0 Access to Reserved Address Select 0 Assign to interrupt enabled by ILE EINT0 1 Ass...

Page 75: ...9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 EINT0 RW R 0 Enable Interrupt Line...

Page 76: ...h 29 bit extended IDs 1 Reject all remote frames with 29 bit extended IDs 1 RRFS RW R 0 Reject Remote Frames Standard 0 Filter remote frames with 11 bit standard IDs 1 Reject all remote frames with 11...

Page 77: ...1 20 19 18 17 16 Name LSS 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 15 FLSSA RW R 0 Filter List Standard Start Address Start address o...

Page 78: ...19 18 17 16 Name None 23 23 LSE 22 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 15 FLESA RW R 0 Filter List Extended Start Address Start ad...

Page 79: ...3 22 21 20 19 18 17 16 Name EIDM 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 29 EIDM 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 28 EIDM RW R 536870911 Extended ID Mask For acce...

Page 80: ...ts Name SW HW Default or Enum Description 0 5 BIDX R RW 0 Buffer Index Index of Rx FIFO element to which the message was stored Only valid when MSI 1 1 6 7 MSI R RW 0 Message Storage Indicator 00 No F...

Page 81: ...Bit fields Bits Name SW HW Default or Enum Description 0 31 ND RW1C RW 0 New Data The register holds the New Data flags of Rx Buffers 0 to 31 The flags are set when the respective Rx Buffer has been u...

Page 82: ...Bit fields Bits Name SW HW Default or Enum Description 0 31 ND RW1C RW 0 New Data The register holds the New Data flags of Rx Buffers 32 to 63 The flags are set when the respective Rx Buffer has been...

Page 83: ...R 0 Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM 32 bit word address see Figure 2 16 22 F0S RW R 0 Rx FIFO 0 Size 0 No Rx FIFO 0 1 64 Number of Rx FIFO 0 elements 64 Values greate...

Page 84: ...0 Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64 8 13 F0GI R RW 0 Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63 This field is updated by the software writi...

Page 85: ...8 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 5 F0AI RW A 0 Rx FIFO 0 Acknowledge Index After the Host has read a messag...

Page 86: ...0 Bits 15 14 13 12 11 10 9 8 Name RBSA 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 15 RBSA...

Page 87: ...R 0 Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM 32 bit word address see Figure 2 16 22 F1S RW R 0 Rx FIFO 1 Size 0 No Rx FIFO 1 1 64 Number of Rx FIFO 1 elements 64 Values greate...

Page 88: ...t Index Rx FIFO 1 read index pointer range 0 to 63 This field is updated by the software writing to RxF1A FAI 16 21 F1PI R RW 0 Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63 24 F1F R...

Page 89: ...8 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 5 F1AI RW A 0 Rx FIFO 1 Acknowledge Index After the Host has read a messag...

Page 90: ...Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field 4 6 F...

Page 91: ...SW HW Default or Enum Description 2 15 TBSA RW R 0 Tx Buffers Start Address Start address of Tx Buffers section in Message RAM 32 bit word address see Figure 2 16 21 NDTB RW R 0 Number of Dedicated Tr...

Page 92: ...ields Bits Name SW HW Default or Enum Description 0 5 TFFL R RW 0 Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32 Read as zero when Tx Queue operation i...

Page 93: ...14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 TBDS RW R 0 Tx Bu...

Page 94: ...riority Tx Buffer with lowest Message ID A cancellation request resets the corresponding transmission request pending bit of register TXBRP In case a transmission has already been started when a cance...

Page 95: ...num Description 0 31 AR RW RW 0 Add Request Each Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit writing a 0 has no impact This enables the Host to set tra...

Page 96: ...its Name SW HW Default or Enum Description 0 31 CR RW R 0 Cancellation Request Each Tx Buffer has its own Cancellation Request bit Writing a 1 will set the corresponding Cancellation Request bit writi...

Page 97: ...Bits 31 30 29 28 27 26 25 24 Name TO 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 TO R RW 0 Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit The bits are...

Page 98: ...HW Default or Enum Description 0 31 CF R RW 0 Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit The bits are set when the corresponding TXBRP bit is cleared after a cancellati...

Page 99: ...TIE 7 0 Bits 15 14 13 12 11 10 9 8 Name TIE 15 8 Bits 23 22 21 20 19 18 17 16 Name TIE 23 16 Bits 31 30 29 28 27 26 25 24 Name TIE 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 TIE...

Page 100: ...14 13 12 11 10 9 8 Name CFIE 15 8 Bits 23 22 21 20 19 18 17 16 Name CFIE 23 16 Bits 31 30 29 28 27 26 25 24 Name CFIE 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 CFIE RW R 0 Canc...

Page 101: ...t fields Bits Name SW HW Default or Enum Description 2 15 EFSA RW R 0 Event FIFO Start Address Start address of Tx Event FIFO in Message RAM 32 bit word address see Figure 2 16 21 EFS RW R 0 Event FIF...

Page 102: ...5 EFFL R RW 0 Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32 8 12 EFGI R RW 0 Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31 16 20 EFPI R RW 0 Eve...

Page 103: ...6 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 EFAI RW R 0 Event FIFO Acknowledge Index After the Host has read an element or...

Page 104: ...s 23 22 21 20 19 18 17 16 Name None 23 23 TME 22 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 15 TMSA RW R 0 Trigger Memory Start Address St...

Page 105: ...R 0 Reference Identifier Identifier transmitted with reference message and used for reference message filtering Standard or extended reference identifier depending on bit XTD A standard identifier ha...

Page 106: ...e triggered operation 1 External event synchronized time triggered operation 4 TM RW R 0 Time Master 0 Time Master function disabled 1 Potential Time Master 5 7 LDSDL RW R 0 LD of Synchronization Devi...

Page 107: ...incremented once each 256 NTUs 24 EGTF RW R 0 Enable Global Time Filtering 0 Global time filtering in TTCAN Level 0 2 is disabled 1 Global time filtering in TTCAN Level 0 2 is enabled 25 ECC RW R 0 E...

Page 108: ...trix Cycle 0x01 2 Basic Cycles per Matrix Cycle 0x03 4 Basic Cycles per Matrix Cycle 0x07 8 Basic Cycles per Matrix Cycle 0x0F 16 Basic Cycles per Matrix Cycle 0x1F 32 Basic Cycles per Matrix Cycle 0x...

Page 109: ...R 0 Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF ELT 0 or if TTOCF EECS external clock synchronization enabled is se...

Page 110: ...W R 0 External Clock Synchronization Writing a 1 to ECS sets TTOST WECS if the node is the actual Time Master ECS is reset after one Host clock period The external clock synchronization takes effect a...

Page 111: ...eference message 0 No reference message requested 1 Application requested start of reference message 11 TMG RW R 0 Time Mark Gap 0 Reset by each reference message 1 Next reference message started when...

Page 112: ...ields Bits Name SW HW Default or Enum Description 0 15 TP RW R 0 Time Preset TP is write protected while TTOST WGTD is set 0x0000 7FFF Next Master Reference Mark Master Reference Mark TP 0x8000 reserv...

Page 113: ...00000x valid for all cycles 0b000001c valid every second cycle at cycle count mod2 c 0b00001cc valid every fourth cycle at cycle count mod4 cc 0b0001ccc valid every eighth cycle at cycle count mod8 cc...

Page 114: ...started 2 CSM_ RW1C RW 0 Change of Synchronization Mode 0 No change in master to slave relation or schedule synchronization 1 Master to slave relation or schedule synchronization changed also set whe...

Page 115: ...0 Number of Tx Trigger as expected 1 More Tx trigger than expected in one matrix cycle 12 SE1 RW1C RW 0 Scheduling Error 1 0 No scheduling error 1 1 Scheduling error 1 occurred 13 SE2 RW1C RW 0 Schedu...

Page 116: ...pt Disabled 1 Interrupt Enabled 2 CSME RW R 0 Change of Synchronization Mode Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 3 SOGE RW R 0 Start of Gap Interrupt Enable 0 Interrupt Disabled...

Page 117: ...bled 14 ELCE RW R 0 Change Error Level Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 15 IWTE RW R 0 Initialization Watch Trigger Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 1...

Page 118: ...MCL RW R 0 Start of Matrix Cycle Interrupt Select 0 Assign to interrupt enabled by ILE EINT0 1 Assign to interrupt enabled by ILE EINT1 2 CSML RW R 0 Change of Synchronization Mode Interrupt Select 0...

Page 119: ...terrupt enabled by ILE EINT1 14 ELCL RW R 0 Change Error Level Interrupt Select 0 Assign to interrupt enabled by ILE EINT0 1 Assign to interrupt enabled by ILE EINT1 15 IWTL RW R 0 Initialization Watc...

Page 120: ...verity 3 Severe Error 2 3 MS R RW 0 Master State 00 Master_Off no master properties relevant 01 Operating as Time Slave 10 Operating as Backup Time Master 11 Operating as current Time Master 4 5 SYS R...

Page 121: ...RW 0 Time Master Priority 0x0 7 Priority of actual Time Master 27 GSI R RW 0 Gap Started Indicator 0 No Gap in schedule reset by each reference message and for all time slaves 1 Gap time after Basic...

Page 122: ...4 3 2 1 0 Name NAV 7 0 Bits 15 14 13 12 11 10 9 8 Name NAV 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 18 NAV 17 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default...

Page 123: ...GT 23 16 Bits 31 30 29 28 27 26 25 24 Name GT 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 LT R RW 0 Local Time Non fractional part of local time incremented once each local NTU s...

Page 124: ...3 22 21 20 19 18 17 16 Name None 23 22 CC 21 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 CT R RW 0 Cycle Time Non fractional part of the...

Page 125: ...r Enum Description 0 5 CCV R RW 0 Cycle Count Value Cycle count value captured together with SWV 0x00 3F Captured cycle count value 16 31 SWV R RW 0 Stop Watch Value On a rising falling edge as config...

Page 126: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name CSM 7 0 Bits 15 14 13 12 11 10 9 8 Name CSM 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Na...

Page 127: ...t ID 0 CM0P_DWT_DWT_CID1 0xE0001FF4 FULL Watchpoint Unit CoreSight ROM Table Component ID 1 CM0P_DWT_DWT_CID2 0xE0001FF8 FULL Watchpoint Unit CoreSight ROM Table Component ID 2 CM0P_DWT_DWT_CID3 0xE00...

Page 128: ...ate Register CM0P_SCS_DFSR 0xE000ED30 FULL Debug Fault Status Register CM0P_SCS_MPU_TYPE 0xE000ED90 FULL MPU Type Register CM0P_SCS_MPU_CTRL 0xE000ED94 FULL MPU Control Register CM0P_SCS_MPU_RNR 0xE00...

Page 129: ...rmission Description CM0P_CTI_CTICONTROL 0xF0002000 FULL CTI Control Register CM0P_CTI_CTIINTACK 0xF0002010 FULL CTI Interrupt Acknowledge Register CM0P_CTI_CTIAPPSET 0xF0002014 FULL CTI Application T...

Page 130: ...TI_CID1 0xF0002FF4 FULL Component Identification Register 1 CM0P_CTI_CID2 0xF0002FF8 FULL Component Identification Register 2 CM0P_CTI_CID3 0xF0002FFC FULL Component Identification Register 3 3 7 MTB...

Page 131: ...er of comparators implemented Default 0x20000000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29...

Page 132: ...bit 0 is RAZ When RAZ bit 0 does not reflect instruction set state as is the case with similar functionality in other ARM architecture profiles Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name EI...

Page 133: ...ator Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP 15 8 Bits 23 22 21 20 19 18 17 16 Name COMP 23 16 Bits 31 30 29 28 27 26 25 24 Name COMP 31 24...

Page 134: ...11 10 9 8 Name MASK 15 8 Bits 23 22 21 20 19 18 17 16 Name MASK 23 16 Bits 31 30 29 28 27 26 25 24 Name MASK 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 MASK RW R X The size of...

Page 135: ...25 24 Name None 31 25 MATCHED 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 FUNCTION RW R 0 Select action on comparator match DISABLE 0 Disabled IADDR 4 PC watchpoint event DADDR_R...

Page 136: ...ator Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP 15 8 Bits 23 22 21 20 19 18 17 16 Name COMP 23 16 Bits 31 30 29 28 27 26 25 24 Name COMP 31 24...

Page 137: ...10 9 8 Name MASK 15 8 Bits 23 22 21 20 19 18 17 16 Name MASK 23 16 Bits 31 30 29 28 27 26 25 24 Name MASK 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 MASK RW R X The size of the...

Page 138: ...25 24 Name None 31 25 MATCHED 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 FUNCTION RW R 0 Select action on comparator match DISABLE 0 Disabled IADDR 4 PC watchpoint event DADDR_R...

Page 139: ...epSleep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 140: ...epSleep No Comment Default 0xA Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 141: ...pSleep No Comment Default 0xB0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 142: ...epSleep No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 143: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 144: ...epSleep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 145: ...pSleep No Comment Default 0xE0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 146: ...epSleep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 147: ...pSleep No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 148: ...15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLE RW R 0 E...

Page 149: ...H 31 30 None 29 29 COMP_ADDR 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLE RW R 0 Enables the comparator Note BP_CTRL ENABLE must also be set to 1 to enable a comparator 2 28 C...

Page 150: ...H 31 30 None 29 29 COMP_ADDR 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLE RW R 0 Enables the comparator Note BP_CTRL ENABLE must also be set to 1 to enable a comparator 2 28 C...

Page 151: ...H 31 30 None 29 29 COMP_ADDR 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLE RW R 0 Enables the comparator Note BP_CTRL ENABLE must also be set to 1 to enable a comparator 2 28 C...

Page 152: ...H 31 30 None 29 29 COMP_ADDR 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLE RW R 0 Enables the comparator Note BP_CTRL ENABLE must also be set to 1 to enable a comparator 2 28 C...

Page 153: ...pSleep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 154: ...Sleep No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 155: ...leep No Comment Default 0xB0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 156: ...Sleep No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 157: ...pSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 158: ...pSleep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 159: ...Sleep No Comment Default 0xE0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 160: ...pSleep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 161: ...Sleep No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 162: ...the status of the SysTick exception to change to pending 0 count to 0 does not affect the SysTick exception status 1 count to 0 changes the SysTick exception status to pending Changing the value of t...

Page 163: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name RELOAD 7 0 Bits 15 14 13 12 11 10 9 8 Name RELOAD 15 8 Bits 23 22 21 20 19 18 17 16 Name RELOAD 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24...

Page 164: ...gister to 0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CURRENT 7 0 Bits 15 14 13 12 11 10 9 8 Name CURRENT 15 8 Bits 23 22 21 20 19 18 17 16 Name CURRENT 23 16 Bits 31 30 29 28 27 26 25 24...

Page 165: ...r 10ms 100Hz timing subject to system clock skew errors If this field is 0 the calibration value is not known This field is controlled by CPUSS_SYSTICK_CTL TENMS field 30 SKEW R RW X Indicates whether...

Page 166: ...ield Table Bits 7 6 5 4 3 2 1 0 Name SETENA 7 0 Bits 15 14 13 12 11 10 9 8 Name SETENA 15 8 Bits 23 22 21 20 19 18 17 16 Name SETENA 23 16 Bits 31 30 29 28 27 26 25 24 Name SETENA 31 24 Bit fields Bit...

Page 167: ...field Table Bits 7 6 5 4 3 2 1 0 Name CLRENA 7 0 Bits 15 14 13 12 11 10 9 8 Name CLRENA 15 8 Bits 23 22 21 20 19 18 17 16 Name CLRENA 23 16 Bits 31 30 29 28 27 26 25 24 Name CLRENA 31 24 Bit fields Bi...

Page 168: ...interrupts Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SETPEND 7 0 Bits 15 14 13 12 11 10 9 8 Name SETPEND 15 8 Bits 23 22 21 20 19 18 17 16 Name SETPEND 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 169: ...interrupts Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CLRPEND 7 0 Bits 15 14 13 12 11 10 9 8 Name CLRPEND 15 8 Bits 23 22 21 20 19 18 17 16 Name CLRPEND 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 170: ...7 6 None 5 0 Bits 15 14 13 12 11 10 9 8 Name PRI_N1 15 14 None 13 8 Bits 23 22 21 20 19 18 17 16 Name PRI_N2 23 22 None 21 16 Bits 31 30 29 28 27 26 25 24 Name PRI_N3 31 30 None 29 24 Bit fields Bits...

Page 171: ...R 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 REVISION R 1 Indicates revision In ARM implementations this is the minor revision number n in the pn part of the rnpn revision status...

Page 172: ...ions The pending state includes the effect of memory mapped enable and mask registers It does not include the PRIMASK special purpose register qualifier 22 ISRPENDING R RW 0 Indicates if an external c...

Page 173: ...d Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name TBLOFF 15 8 Bits 23 22 21 20 19 18 17 16 Name TBLOFF 23 16 Bits 31 30 29 28 27 26 25 24 Name TBLOFF 31 24 Bit fields Bits Nam...

Page 174: ...ctive state information for fixed and configurable exceptions The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE 2 SYSRESETREQ RW1S R 0 System Reset R...

Page 175: ...whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state 0 do not enter sleep state 1 enter sleep state See Power management on Arm TRM p...

Page 176: ...None 15 10 STKALIGN 9 9 None 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 3 UNALIGN_TRP R 1 1 un...

Page 177: ...tem handler 11 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name P...

Page 178: ...eld Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name PRI_14 23 22 None 21 16 Bits 31 30 29 28 27 26 25 24 Name PRI_15 31 30 None 29...

Page 179: ...CALLPEN DED 15 15 None 14 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 15 SVCALLPENDED RW RW 0 0 S...

Page 180: ...ed by a C_HALT or C_STEP request triggered by a write to the DHCSR 0 no active halt request debug event 1 halt request debug event active See Debug Halting Control and Status Register DHCSR for more i...

Page 181: ...4 13 12 11 10 9 8 Name DREGION 15 8 Bits 23 22 21 20 19 18 17 16 Name IREGION 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 SEPARATE R R 0...

Page 182: ...7 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLE RW R 0 Enables the MPU 0 The MPU is disabled Privileged and unprivileged accesses use the default memory map...

Page 183: ...ield Table Bits 7 6 5 4 3 2 1 0 Name REGION_M 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Na...

Page 184: ...description of the MPU_RASR SIZE field in MPU Region Attribute and Size Register MPU_RASR Software must ensure that the value written to the ADDR field aligns with the size of the selected region Def...

Page 185: ...E RW R X Enables this region 0 when the MPU is enabled this region is disabled 1 When the MPU is enabled this region is enabled Enabling a region has no effect unless the MPU_CTRL ENABLE bit is set to...

Page 186: ...Bits 31 30 29 28 27 26 25 24 Name DBG_KEY_P2 31 26 S_RESET _ST 25 25 S_RETIRE_ ST 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 C_DEBUGEN RW R 0 Halting debug enable bit If a debugge...

Page 187: ...tate 18 S_SLEEP R RW 0 Indicates whether the processor is sleeping The debugger must set the DHCSR C_HALT bit to 1 to gain control or wait for an interrupt or other wakeup event to wakeup the system 1...

Page 188: ...1 0 Name None 7 5 REGSEL 4 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 17 REGWNR 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW H...

Page 189: ...Technical Reference Manual 002 29852 Rev B Bits Name SW HW Default or Enum Description WRITE 1 Write transfer 189 2022 04 18 TRAVEO T2G Automotive MCU TVII B E 4M body controller entry registers...

Page 190: ...r for these accesses Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DBGTMP 7 0 Bits 15 14 13 12 11 10 9 8 Name DBGTMP 15 8 Bits 23 22 21 20 19 18 17 16 Name DBGTMP 23 16 Bits 31 30 29 28 27 26...

Page 191: ...Bits Name SW HW Default or Enum Description 0 VC_CORERESET RW R 0 Enable Reset Vector Catch This causes a Local reset to halt a running system If DHCSR C_DEBUGEN is set to 0 the processor ignores the...

Page 192: ...Sleep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 193: ...Sleep No Comment Default 0x8 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 194: ...eep No Comment Default 0xB0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 195: ...leep No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 196: ...Sleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 197: ...leep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 198: ...eep No Comment Default 0xE0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 199: ...Sleep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 200: ...eep No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 201: ...t Default 0xFFF0F003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALU...

Page 202: ...ault 0xFFF02003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31...

Page 203: ...ault 0xFFF03003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31...

Page 204: ...t Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24...

Page 205: ...p No Comment Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 206: ...p No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 207: ...No Comment Default 0xC0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name V...

Page 208: ...No Comment Default 0xB4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name V...

Page 209: ...No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name V...

Page 210: ...p No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 211: ...p No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 212: ...No Comment Default 0x10 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 213: ...p No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 214: ...No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 215: ...ts 23 22 21 20 19 18 17 16 Name ADDR_OFFSET 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR_OFFSET 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 PRESENT R R 1 Entry present 1 FORMAT_32BI...

Page 216: ...2 21 20 19 18 17 16 Name ADDR_OFFSET 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR_OFFSET 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 PRESENT R R 1 Entry present 1 FORMAT_32BIT R R 1...

Page 217: ...2 21 20 19 18 17 16 Name ADDR_OFFSET 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR_OFFSET 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 PRESENT R R 1 Entry present 1 FORMAT_32BIT R R 1...

Page 218: ...leep No Comment Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 219: ...3 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 JEP_CONTINUATION R R...

Page 220: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 221: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 222: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 223: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name PN_MIN 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits...

Page 224: ...ID_MIN 7 4 PN_MAJ 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 225: ...8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 JEPID_MAJ R R Undefined JEP106 ven...

Page 226: ...me REV_AND 7 4 CM 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 227: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name S...

Page 228: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 229: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name S...

Page 230: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name S...

Page 231: ...3 2 1 0 Name None 7 1 GLBEN 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default o...

Page 232: ...sticky output that is no hardware acknowledge is supplied and a software acknowledge is required Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name INTACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 1...

Page 233: ...Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPSET 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name...

Page 234: ...ten to Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPCLEAR 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 N...

Page 235: ...gister clears itself immediately so it can be repeatedly written to without software having to clear it Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPULSE 3 0 Bits 15 14 13 12 11 1...

Page 236: ...able Bits 7 6 5 4 3 2 1 0 Name None 7 4 TRIGINEN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits...

Page 237: ...one 7 4 TRIGOUTEN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 238: ...S 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 TRI...

Page 239: ...able Bits 7 6 5 4 3 2 1 0 Name TRIGOUTSTATUS 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Nam...

Page 240: ...ATUS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3...

Page 241: ...le Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTICHOUTSTATUS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields...

Page 242: ...register is 0xF and channel propagation is enabled Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTIGATEEN 3 3 3 CTIGATEEN 2 2 2 CTIGATEEN 1 1 1 CTIGATEEN 0 0 0 Bits 15 14 13 12 11 1...

Page 243: ...30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 ASICCTL RW R 0 Implementation defined ASIC control value written to the register is output on ASICCTL 7...

Page 244: ...ter Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHINACK 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 245: ...gister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGINACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name No...

Page 246: ...ster Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHOUT 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 247: ...egister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGOUT 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name Non...

Page 248: ...r Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHOUTACK 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 249: ...ister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGOUTACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name No...

Page 250: ...ter Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHIN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 251: ...egister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGIN 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None...

Page 252: ...pology solving Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 MODE 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25...

Page 253: ...its are implemented a read of this register will return 0x0000000F If no claim tag is implemented then a read of this register will return 0x00000000 Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0 N...

Page 254: ...m Tag value read The width n of this register can be determined from reading the Claim Tag Set Register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TAG 3 0 Bits 15 14 13 12 11 10 9...

Page 255: ...15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 ACCESS_CODE RW R 0 Write Access Code A write o...

Page 256: ...xcept for the Lock Access Register 0xFB0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 IMPLEMENT S_8B 2 2 ACCESS _PE RMITTED 1 1 EXISTS 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 B...

Page 257: ...ame None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 NSIDBG R W 0 Non Secure Invasive Debug 0 Functionality not implemented or controlled elsewhere 1 Functionality disabled 2 Rese...

Page 258: ...configuration Default 0x40800 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 NRMUXING 4 0 Bits 15 14 13 12 11 10 9 8 Name NRTRIG 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 20 NRCHAN 19 16 Bit...

Page 259: ...sub type corresponding to cross trigger 0x1 Default 0x14 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SUB_TYPE 7 4 CLASS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name No...

Page 260: ...eep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 261: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 262: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 263: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 264: ...p No Comment Default 0xA6 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 265: ...p No Comment Default 0xB9 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 266: ...ep No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 267: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name No...

Page 268: ...ep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 269: ...p No Comment Default 0x90 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 270: ...ep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 271: ...p No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 272: ...ace Control Register 3 31 POINTER RW RW X Trace packet location pointer Because a packet consists of two words the POINTER field is the location of the first word of a packet This field contains bits...

Page 273: ...output value is also affected by the Debug authentication interface Configurations Available in all MTB configurations Attributes You can modify all fields by software Automatic hardware mechanisms u...

Page 274: ...ileged AHB Lite read and write accesses to the Special Function Registers are permitted If this bit is 1 then only Privileged write accesses are permitted and User write accesses are ignored The HPROT...

Page 275: ...field and the FLOW AUTOSTOP bit The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signa...

Page 276: ...processor might have to perform additional branch type operations Therefore you must set the WATERMARK field below the final entry in the trace buffer region Default 0x0 Bit field Table Bits 7 6 5 4 3...

Page 277: ...onstraints Configurations Available in all MTB configurations Default 0xF0010000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name BASE 7 0 Bits 15 14 13 12 11 10 9 8 Name BASE 15 8 Bits 23 22 21 20 19 18 17...

Page 278: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31...

Page 279: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31...

Page 280: ...DEN 2 2 AS_1 1 1 DBGEN 0 0 Bits 15 14 13 12 11 10 9 8 Name AS_31TO4 15 8 Bits 23 22 21 20 19 18 17 16 Name AS_31TO4 23 16 Bits 31 30 29 28 27 26 25 24 Name AS_31TO4 31 24 Bit fields Bits Name SW HW De...

Page 281: ...10 9 8 Name ARCH_ID 15 8 Bits 23 22 21 20 19 18 17 16 Name RES_20 20 20 REVISION 19 16 Bits 31 30 29 28 27 26 25 24 Name ARCHITECT 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 AR...

Page 282: ...No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 283: ...field Table Bits 7 6 5 4 3 2 1 0 Name SUB_TYPE 7 4 CLASS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fi...

Page 284: ...eep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 285: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 286: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 287: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 288: ...ep No Comment Default 0x32 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 289: ...p No Comment Default 0xB9 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 290: ...ep No Comment Default 0x1B Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 291: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name No...

Page 292: ...ep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 293: ...p No Comment Default 0x90 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 294: ...ep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 295: ...p No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 296: ...t registers CM4_ITM_STIM23 0xE000005C FULL Stimulus Port registers CM4_ITM_STIM24 0xE0000060 FULL Stimulus Port registers CM4_ITM_STIM25 0xE0000064 FULL Stimulus Port registers CM4_ITM_STIM26 0xE00000...

Page 297: ...0 0xE0001FF0 FULL Component Identification Register 0 CM4_DWT_CID1 0xE0001FF4 FULL Component Identification Register 1 CM4_DWT_CID2 0xE0001FF8 FULL Component Identification Register 2 CM4_DWT_CID3 0xE...

Page 298: ...L Interrupt Clear Pending Registers CM4_SCS_NVIC_ICPR3 0xE000E28C FULL Interrupt Clear Pending Registers CM4_SCS_NVIC_ICPR4 0xE000E290 FULL Interrupt Clear Pending Registers CM4_SCS_NVIC_ICPR5 0xE000E...

Page 299: ...FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR50 0xE000E4C8 FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR51 0xE000E4CC FULL Interrupt Priority Registers CM4_SCS_NVIC_IPR52 0xE000E4D0 FULL In...

Page 300: ..._TRIGGER 0xE0041008 FULL Trigger Event Register CM4_ETM_SR 0xE0041010 FULL ETM Status Register CM4_ETM_SCR 0xE0041014 FULL System Configuration Register CM4_ETM_TEEVR 0xE0041020 FULL TraceEnable Event...

Page 301: ...CTI Channel to Trigger Enable Registers CM4_CM4CTI_CTITRIGINSTATUS 0xE0042130 FULL CTI Trigger In Status Register CM4_CM4CTI_CTITRIGOUTSTATUS 0xE0042134 FULL CTI Trigger Out Status Register CM4_CM4CT...

Page 302: ...to Channel Enable Registers CM4_TRCCTI_CTIINEN4 0xE0080030 FULL CTI Trigger to Channel Enable Registers CM4_TRCCTI_CTIINEN5 0xE0080034 FULL CTI Trigger to Channel Enable Registers CM4_TRCCTI_CTIINEN6...

Page 303: ...FULL Lock Access Register CM4_CSTF_LOCKSTATUS 0xE008CFB4 FULL Lock Status Register CM4_CSTF_AUTHSTATUS 0xE008CFB8 FULL Authentication Status Register CM4_CSTF_DEVID 0xE008CFC8 FULL Device ID CM4_CSTF...

Page 304: ...ister CM4_TPIU_TPIU_FFSR 0xE008E300 FULL Formatter and Flush Status Register CM4_TPIU_TPIU_FFCR 0xE008E304 FULL Formatter and Flush Control Register CM4_TPIU_TPIU_FSCR 0xE008E308 FULL Formatter Synchr...

Page 305: ...E_PID1 0xE00FFFE4 FULL CM4 CoreSight ROM Table Peripheral ID 1 CM4_ROMTABLE_PID2 0xE00FFFE8 FULL CM4 CoreSight ROM Table Peripheral ID 2 CM4_ROMTABLE_PID3 0xE00FFFEC FULL CM4 CoreSight ROM Table Perip...

Page 306: ...tes Configurations Always implemented Attributes See Arm TRM Table C1 11 on page C1 773 and the register field descriptions The address of ITM_STIMn is 0xE0000000 4n Default 0x0 Bit field Table Bits 7...

Page 307: ...ed ITM_STIM registers The processor ignores any unprivileged write to an ITM_TERx bit if the corresponding ITM_TPR PRIVMASK bit is set to 1 see Trace Privilege Register ITM_TPR on Arm TRM page C1 775...

Page 308: ...er is available if the ITM is configured in your implementation Attributes Refer to the ITM register summary table Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 PRIVMASK 3 0 Bits 15 1...

Page 309: ...one 15 12 GTSFREQ 11 10 TSPRESCALE 9 8 Bits 23 22 21 20 19 18 17 16 Name BUSY 23 23 TRACEBUSID 22 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description...

Page 310: ...If implemented a Power on reset clears this field to zero If the processor does not implement the timestamp prescaler then these bits are reserved RAZ WI 10 11 GTSFREQ RW R 0 Global timestamp frequenc...

Page 311: ...num Description 23 BUSY RW R 0 Indicates whether the ITM is currently processing events 0 ITM is not processing any events 1 ITM events present and being drained These bits are read only 311 2022 04 1...

Page 312: ...ts 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 ACCESS_CODE RW R 0 Write Access Code A write of 0xC5A...

Page 313: ...t for the Lock Access Register 0xFB0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 IMPLEMENT S_8B 2 2 ACCESS _PE RMITTED 1 1 EXISTS 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits...

Page 314: ...ep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 315: ...ep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 316: ...ep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 317: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 318: ...eep No Comment Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 319: ...p No Comment Default 0xB0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 320: ...ep No Comment Default 0x3B Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 321: ...ent Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 322: ...ep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 323: ...p No Comment Default 0xE0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 324: ...ep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 325: ...p No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 326: ...NOTRCPKT 27 27 NOEXTTRIG 26 26 NOCYCCNT 25 25 NOPRFCNT 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 CYCCNTENA RW R 0 Enables CYCCNT 0 Disabled 1 Enabled This bit is UNK SBZP if the N...

Page 327: ...d 1 Enabled This bit is UNK SBZP if the NOPRFCNT bit is RAO 18 EXCEVTENA RW R 0 Enables generation of the Exception overhead counter overflow event 0 Disabled 1 Enabled This bit is UNK SBZP if the NOP...

Page 328: ...external match signals CMPMATCH N 0 CMPMATCH N supported 1 CMPMATCH N not supported This bit is read only 27 NOTRCPKT RW R 0 Shows whether the implementation supports trace sampling and exception tra...

Page 329: ...ister CTRL on page C1 797 When CTRL NOCYCCNT is RAO no cycle counter is implemented and this register is UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 Default 0x0 Bit field Table Bits 7 6...

Page 330: ...PICNT 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7...

Page 331: ...TRM page C1 797 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name EXCCNT 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 332: ...utes See Table C1 21 on page C1 797 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SLEEPCNT 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30...

Page 333: ...not include the profiling counters this register is UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name LSUCNT 7 0 Bits 15 14 13 12 11 10...

Page 334: ...he implementation does not include the profiling counters this register is UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name FOLDCNT 7 0...

Page 335: ...s in a PC sample on the ARMv7 A and ARMv7 R architecture profiles Configurations An optional feature Register is RAZ WI if not implemented Attributes See Table C1 21 on Arm TRM page C1 797 Default 0x0...

Page 336: ...plemented only when CTRL NUMCOMP is nonzero see Control register CTRL on Arm TRM page C1 797 CTRL NUMCOMP defines the number of implemented COMPn registers Implemented COMPn registers number from 0 to...

Page 337: ...n page C1 797 CTRL NUMCOMP defines the number of implemented MASKn registers Implemented MASKn registers number from 0 to NUMCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21 on A...

Page 338: ...MCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 See the register field descriptions for information about the values of the RO bits in the register Defau...

Page 339: ...is RAZ WI 9 LNK1ENA RW R 0 Indicates whether the implementation supports use of a second linked comparator 0 Second linked comparator not supported 1 Second linked comparator supported When LNK1ENA is...

Page 340: ...0 Comparator match 0 No match 1 Match A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0 Thi...

Page 341: ...s Implemented only when CTRL NUMCOMP is nonzero see Control register CTRL on Arm TRM page C1 797 CTRL NUMCOMP defines the number of implemented COMPn registers Implemented COMPn registers number from...

Page 342: ...m TRM page C1 797 CTRL NUMCOMP defines the number of implemented MASKn registers Implemented MASKn registers number from 0 to NUMCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21...

Page 343: ...MCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 See the register field descriptions for information about the values of the RO bits in the register Defau...

Page 344: ...is RAZ WI 9 LNK1ENA RW R 0 Indicates whether the implementation supports use of a second linked comparator 0 Second linked comparator not supported 1 Second linked comparator supported When LNK1ENA is...

Page 345: ...0 Comparator match 0 No match 1 Match A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0 Thi...

Page 346: ...s Implemented only when CTRL NUMCOMP is nonzero see Control register CTRL on Arm TRM page C1 797 CTRL NUMCOMP defines the number of implemented COMPn registers Implemented COMPn registers number from...

Page 347: ...m TRM page C1 797 CTRL NUMCOMP defines the number of implemented MASKn registers Implemented MASKn registers number from 0 to NUMCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21...

Page 348: ...MCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 See the register field descriptions for information about the values of the RO bits in the register Defau...

Page 349: ...is RAZ WI 9 LNK1ENA RW R 0 Indicates whether the implementation supports use of a second linked comparator 0 Second linked comparator not supported 1 Second linked comparator supported When LNK1ENA is...

Page 350: ...0 Comparator match 0 No match 1 Match A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0 Thi...

Page 351: ...s Implemented only when CTRL NUMCOMP is nonzero see Control register CTRL on Arm TRM page C1 797 CTRL NUMCOMP defines the number of implemented COMPn registers Implemented COMPn registers number from...

Page 352: ...m TRM page C1 797 CTRL NUMCOMP defines the number of implemented MASKn registers Implemented MASKn registers number from 0 to NUMCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21...

Page 353: ...o NUMCOMP 1 Unimplemented registers are UNK SBZP Attributes See Table C1 21 on Arm TRM page C1 797 See the register field descriptions for information about the values of the RO bits in the register D...

Page 354: ...is RAZ WI 9 LNK1ENA RW R 0 Indicates whether the implementation supports use of a second linked comparator 0 Second linked comparator not supported 1 Second linked comparator supported When LNK1ENA is...

Page 355: ...0 Comparator match 0 No match 1 Match A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register Reading the register clears this bit to 0 Thi...

Page 356: ...eep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 357: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 358: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 359: ...eep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 360: ...eep No Comment Default 0x2 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 361: ...p No Comment Default 0xB0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 362: ...ep No Comment Default 0x3B Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 363: ...ent Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 364: ...ep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 365: ...p No Comment Default 0xE0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 366: ...ep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 367: ...p No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 368: ...point enabled A Power on reset clears this bit to 0 1 KEY RW R 0 On any write to FP_CTRL this bit must be 1 A write to the register with this bit set to zero is ignored The Flash Patch Breakpoint unit...

Page 369: ...28 31 REV RW R 0 Flash Patch Breakpoint architecture revision 0000 Flash Patch Breakpoint version 1 0001 Flash Patch Breakpoint version 2 Supports breakpoints on any location in the 4GB address range...

Page 370: ...3 12 11 10 9 8 Name REMAP 15 8 Bits 23 22 21 20 19 18 17 16 Name REMAP 23 16 Bits 31 30 29 28 27 26 25 24 Name RMPSPT 31 30 None 29 29 REMAP 28 24 Bit fields Bits Name SW HW Default or Enum Descriptio...

Page 371: ...TRL on Arm TRM page C1 816 The FP_REMAP RMPSPT field determines if the FPB unit supports Flash Patch For more information about address remapping see FlashPatch Remap register FP_REMAP on page C1 818...

Page 372: ...ep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 373: ...ep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 374: ...ep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 375: ...ep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 376: ...ep No Comment Default 0x3 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 377: ...p No Comment Default 0xB0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 378: ...ep No Comment Default 0x2B Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 379: ...ent Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 380: ...ep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 381: ...p No Comment Default 0xE0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 382: ...ep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 383: ...p No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 384: ...e VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 VALUE RW R 0 Refer the following AR...

Page 385: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 386: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 387: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 388: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW D...

Page 389: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 390: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 391: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 392: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 393: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 394: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 395: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 396: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 397: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defaul...

Page 398: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW...

Page 399: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 400: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 401: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 402: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 403: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 404: ...le Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW...

Page 405: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 406: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 407: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 408: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 409: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 410: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 411: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 412: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 413: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 414: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defaul...

Page 415: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 416: ...le Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW...

Page 417: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 418: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 419: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 420: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 421: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 422: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 423: ...le Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW...

Page 424: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW D...

Page 425: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 426: ...ble Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW H...

Page 427: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 428: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defaul...

Page 429: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defaul...

Page 430: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defaul...

Page 431: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 432: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 433: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 434: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 435: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 436: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 437: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 438: ...6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW H...

Page 439: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 440: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 441: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 442: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 443: ...me VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enum Descripti...

Page 444: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW...

Page 445: ...ld Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name...

Page 446: ...able Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW...

Page 447: ...ield Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Na...

Page 448: ...eld Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Nam...

Page 449: ...field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits N...

Page 450: ...d Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name...

Page 451: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 452: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 453: ...le Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW...

Page 454: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 455: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit...

Page 456: ...eld Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Nam...

Page 457: ...field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits...

Page 458: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW...

Page 459: ...t field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits...

Page 460: ...0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields...

Page 461: ...t field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits...

Page 462: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields B...

Page 463: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields B...

Page 464: ...it field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bit...

Page 465: ...ield Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Na...

Page 466: ...field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits N...

Page 467: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name S...

Page 468: ...d Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name...

Page 469: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 470: ...it field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bit...

Page 471: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 472: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 473: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 474: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 475: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 476: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 477: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 478: ...eld Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit field...

Page 479: ...it field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bit...

Page 480: ...it field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bit...

Page 481: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bi...

Page 482: ...it field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bit...

Page 483: ...5 4 3 2 1 0 Name None 7 1 GLBEN 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Defau...

Page 484: ...sticky output that is no hardware acknowledge is supplied and a software acknowledge is required Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name INTACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None...

Page 485: ...le Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPSET 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Nam...

Page 486: ...tten to Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPCLEAR 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24...

Page 487: ...register clears itself immediately so it can be repeatedly written to without software having to clear it Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPULSE 3 0 Bits 15 14 13 12 11...

Page 488: ...Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TRIGINEN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bi...

Page 489: ...None 7 4 TRIGOUTEN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum De...

Page 490: ...TUS 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 T...

Page 491: ...Table Bits 7 6 5 4 3 2 1 0 Name TRIGOUTSTATUS 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits N...

Page 492: ...TATUS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3...

Page 493: ...able Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTICHOUTSTATUS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit field...

Page 494: ...is register is 0xF and channel propagation is enabled Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTIGATEEN 3 3 3 CTIGATEEN 2 2 2 CTIGATEEN 1 1 1 CTIGATEEN 0 0 0 Bits 15 14 13 12 11...

Page 495: ...1 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 ASICCTL RW R 0 Implementation defined ASIC control value written to the register is output on ASICCTL...

Page 496: ...ster Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHINACK 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 497: ...register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGINACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 498: ...ister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHOUT 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 499: ...register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGOUT 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 500: ...ter Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHOUTACK 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 501: ...gister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGOUTACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 502: ...ister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHIN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 503: ...register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGIN 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name Non...

Page 504: ...topology solving Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 MODE 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 2...

Page 505: ...bits are implemented a read of this register will return 0x0000000F If no claim tag is implemented then a read of this register will return 0x00000000 Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0...

Page 506: ...aim Tag value read The width n of this register can be determined from reading the Claim Tag Set Register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TAG 3 0 Bits 15 14 13 12 11 10...

Page 507: ...e 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 ACCESS_CODE RW R 0 Write Access Code A write...

Page 508: ...except for the Lock Access Register 0xFB0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 IMPLEMENT S_8B 2 2 ACCESS _PE RMITTED 1 1 EXISTS 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8...

Page 509: ...Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 NSIDBG R W 1 Non Secure Invasive Debug 0 Functionality not implemented or controlled elsewhere 1 Functionality disabled 2 Re...

Page 510: ...d configuration Default 0x40800 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 NRMUXING 4 0 Bits 15 14 13 12 11 10 9 8 Name NRTRIG 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 20 NRCHAN 19 16 Bi...

Page 511: ...sub type corresponding to cross trigger 0x1 Default 0x14 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SUB_TYPE 7 4 CLASS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name N...

Page 512: ...leep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 513: ...leep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 514: ...leep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 515: ...leep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 516: ...leep No Comment Default 0x6 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 517: ...eep No Comment Default 0xB9 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 518: ...eep No Comment Default 0x4B Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 519: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 520: ...eep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 521: ...ep No Comment Default 0x90 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 522: ...leep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 523: ...ep No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 524: ...Default 0xFFF8F003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE...

Page 525: ...lt 0xFFF82003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24...

Page 526: ...lt 0xFFF83003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24...

Page 527: ...lt 0xFFF81003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24...

Page 528: ...ult 0xFFFC3003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 2...

Page 529: ...ult 0xFFFC2003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 2...

Page 530: ...No Comment Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 531: ...No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 532: ...Comment Default 0xC0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VAL...

Page 533: ...o Comment Default 0xB4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 534: ...No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 535: ...No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 536: ...No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 537: ...o Comment Default 0x10 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 538: ...No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 539: ...o Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VA...

Page 540: ...5 4 3 2 1 0 Name None 7 1 GLBEN 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Defau...

Page 541: ...sticky output that is no hardware acknowledge is supplied and a software acknowledge is required Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name INTACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None...

Page 542: ...le Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPSET 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Nam...

Page 543: ...tten to Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPCLEAR 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24...

Page 544: ...register clears itself immediately so it can be repeatedly written to without software having to clear it Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 APPULSE 3 0 Bits 15 14 13 12 11...

Page 545: ...Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TRIGINEN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bi...

Page 546: ...None 7 4 TRIGOUTEN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum De...

Page 547: ...TUS 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 T...

Page 548: ...Table Bits 7 6 5 4 3 2 1 0 Name TRIGOUTSTATUS 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits N...

Page 549: ...TATUS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3...

Page 550: ...able Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTICHOUTSTATUS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit field...

Page 551: ...is register is 0xF and channel propagation is enabled Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTIGATEEN 3 3 3 CTIGATEEN 2 2 2 CTIGATEEN 1 1 1 CTIGATEEN 0 0 0 Bits 15 14 13 12 11...

Page 552: ...1 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 ASICCTL RW R 0 Implementation defined ASIC control value written to the register is output on ASICCTL...

Page 553: ...ster Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHINACK 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 554: ...register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGINACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 555: ...ister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHOUT 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 556: ...register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGOUT 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 557: ...ter Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHOUTACK 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 558: ...gister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGOUTACK 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 559: ...ister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 CTCHIN 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 560: ...register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name CTTRIGIN 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name Non...

Page 561: ...topology solving Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 MODE 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 2...

Page 562: ...bits are implemented a read of this register will return 0x0000000F If no claim tag is implemented then a read of this register will return 0x00000000 Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0...

Page 563: ...aim Tag value read The width n of this register can be determined from reading the Claim Tag Set Register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TAG 3 0 Bits 15 14 13 12 11 10...

Page 564: ...e 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 ACCESS_CODE RW R 0 Write Access Code A write...

Page 565: ...except for the Lock Access Register 0xFB0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 IMPLEMENT S_8B 2 2 ACCESS _PE RMITTED 1 1 EXISTS 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8...

Page 566: ...Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 NSIDBG R W 1 Non Secure Invasive Debug 0 Functionality not implemented or controlled elsewhere 1 Functionality disabled 2 Re...

Page 567: ...d configuration Default 0x40800 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 NRMUXING 4 0 Bits 15 14 13 12 11 10 9 8 Name NRTRIG 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 20 NRCHAN 19 16 Bi...

Page 568: ...sub type corresponding to cross trigger 0x1 Default 0x14 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SUB_TYPE 7 4 CLASS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name N...

Page 569: ...leep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 570: ...leep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 571: ...leep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 572: ...leep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 573: ...leep No Comment Default 0x6 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 574: ...eep No Comment Default 0xB9 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 575: ...eep No Comment Default 0x4B Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 576: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name N...

Page 577: ...eep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 578: ...ep No Comment Default 0x90 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 579: ...leep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 580: ...ep No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Nam...

Page 581: ...2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enum D...

Page 582: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 583: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 584: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 585: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 586: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 587: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 588: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 589: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 590: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 591: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 592: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 593: ...2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enum D...

Page 594: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 595: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 596: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 597: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 598: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 599: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 600: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 601: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 602: ...5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW...

Page 603: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 604: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 605: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 606: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 607: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 608: ...3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enum...

Page 609: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 610: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 611: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 612: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 613: ...3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enu...

Page 614: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 615: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 616: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 617: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 618: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 619: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 620: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 621: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 622: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 623: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 624: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 625: ...its are implemented a read of this register will return 0x0000000F If no claim tag is implemented then a read of this register will return 0x00000000 Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0 N...

Page 626: ...im Tag value read The width n of this register can be determined from reading the Claim Tag Set Register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TAG 3 0 Bits 15 14 13 12 11 10 9...

Page 627: ...15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 ACCESS_CODE RW R 0 Write Access Code A write...

Page 628: ...except for the Lock Access Register 0xFB0 Default 0x3 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 IMPLEMENT S_8B 2 2 ACCESS _PE RMITTED 1 1 EXISTS 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8...

Page 629: ...Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 NSIDBG R W 0 Non Secure Invasive Debug 0 Functionality not implemented or controlled elsewhere 1 Functionality disabled 2 Res...

Page 630: ...dard configuration Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 6 RAMCLK 5 5 EXTMUXNUM 4 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 3...

Page 631: ...t field Table Bits 7 6 5 4 3 2 1 0 Name SUB_TYPE 7 4 CLASS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit f...

Page 632: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 633: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 634: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 635: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 636: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 637: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 638: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 639: ...5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW...

Page 640: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 641: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 642: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 643: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 644: ...5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or...

Page 645: ...its 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Def...

Page 646: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 647: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defaul...

Page 648: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 649: ...Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW De...

Page 650: ...le Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW...

Page 651: ...4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or En...

Page 652: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 653: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 654: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default o...

Page 655: ...6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 656: ...opology solving Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 MODE 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25...

Page 657: ...bits are implemented a read of this register will return 0x0000000F If no claim tag is implemented then a read of this register will return 0x00000000 Default 0xF Bit field Table Bits 7 6 5 4 3 2 1 0...

Page 658: ...im Tag value read The width n of this register can be determined from reading the Claim Tag Set Register Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 TAG 3 0 Bits 15 14 13 12 11 10 9...

Page 659: ...16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 MUXNUM R R 0 Indicates the level of input multiplexing When non zero this val...

Page 660: ...0 Name SUB_TYPE 7 4 CLASS 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or...

Page 661: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 662: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 663: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 664: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 665: ...UE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3...

Page 666: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 667: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 668: ...5 4 3 2 1 0 Name ECOREVNUM 7 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW...

Page 669: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 670: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 671: ...ts 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defa...

Page 672: ...s 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Defau...

Page 673: ...omment Default 0xFFF81003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 674: ...ault 0xFFF8D003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31...

Page 675: ...Default 0xFFF8E003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE...

Page 676: ...Default 0xFFF8F003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE...

Page 677: ...efault 0xFFF80003 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 3...

Page 678: ...ep No Comment Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 679: ...ep No Comment Default 0x4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 680: ...No Comment Default 0xC0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 681: ...No Comment Default 0xB4 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 682: ...ep No Comment Default 0xB Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 683: ...ep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 684: ...ep No Comment Default 0xD Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 685: ...p No Comment Default 0x10 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 686: ...ep No Comment Default 0x5 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 687: ...p No Comment Default 0xB1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 688: ...4 status CPUSS_CM0_INT5_STATUS 0x40201114 FULL CM0 interrupt 5 status CPUSS_CM0_INT6_STATUS 0x40201118 FULL CM0 interrupt 6 status CPUSS_CM0_INT7_STATUS 0x4020111C FULL CM0 interrupt 7 status CPUSS_C...

Page 689: ...CPUSS_CM0_SYSTEM_INT_CTL19 0x4020804C FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL20 0x40208050 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL21 0x40208054 FULL CM0 system in...

Page 690: ...TEM_INT_CTL81 0x40208144 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL82 0x40208148 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL83 0x4020814C FULL CM0 system interrupt contr...

Page 691: ...0_SYSTEM_INT_CTL144 0x40208240 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL145 0x40208244 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL146 0x40208248 FULL CM0 system interru...

Page 692: ...0_SYSTEM_INT_CTL207 0x4020833C FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL208 0x40208340 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL209 0x40208344 FULL CM0 system interru...

Page 693: ...0_SYSTEM_INT_CTL270 0x40208438 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL271 0x4020843C FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL272 0x40208440 FULL CM0 system interru...

Page 694: ...0_SYSTEM_INT_CTL333 0x40208534 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL334 0x40208538 FULL CM0 system interrupt control CPUSS_CM0_SYSTEM_INT_CTL335 0x4020853C FULL CM0 system interru...

Page 695: ...SS_CM4_SYSTEM_INT_CTL13 0x4020A034 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL14 0x4020A038 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL15 0x4020A03C FULL CM4 system inter...

Page 696: ...YSTEM_INT_CTL76 0x4020A130 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL77 0x4020A134 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL78 0x4020A138 FULL CM4 system interrupt con...

Page 697: ...4_SYSTEM_INT_CTL139 0x4020A22C FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL140 0x4020A230 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL141 0x4020A234 FULL CM4 system interru...

Page 698: ...4_SYSTEM_INT_CTL202 0x4020A328 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL203 0x4020A32C FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL204 0x4020A330 FULL CM4 system interru...

Page 699: ...4_SYSTEM_INT_CTL265 0x4020A424 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL266 0x4020A428 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL267 0x4020A42C FULL CM4 system interru...

Page 700: ...4_SYSTEM_INT_CTL328 0x4020A520 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL329 0x4020A524 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL330 0x4020A528 FULL CM4 system interru...

Page 701: ...CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL371 0x4020A5CC FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL372 0x4020A5D0 FULL CM4 system interrupt control CPUSS_CM4_SYSTEM_INT_CTL3...

Page 702: ...e 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 P R W Undefined This field specifies the privileged setting 0 user mode 1 privileged mode...

Page 703: ...its Name SW HW Default or Enum Description 0 SLEEPING R W 1 Specifies if the CPU is in Active Sleep or DeepSleep power mode Active power mode SLEEPING is 0 Sleep power mode SLEEPING is 1 and SLEEPDEEP...

Page 704: ...Bit fields Bits Name SW HW Default or Enum Description 8 15 FAST_INT_DIV RW R 0 Specifies the fast clock divider from the high frequency clock clk_hf to the peripheral clock clk_fast Integer division...

Page 705: ...there is no precise FPU exception handler Instead FPU conditions are captured in the CPU s FPCSR register and the conditions are provided as CPU interface signals The interface signals are masked with...

Page 706: ...te the CPU s floating point interrupt 1 the CPU s exception condition activates the CPU s floating point interrupt Note the inexact condition is set as a result of rounding Rounding may occur frequent...

Page 707: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 708: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 709: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 710: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 711: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 712: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 713: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 714: ...Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 715: ...ame ADDR22 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR22 31 24 Bit fields Bits Name SW HW Default or Enum Description 10 31 ADDR22 RW 0 Address of CM4 vector table This register is used for CM4 warm...

Page 716: ...ate all selected system interrupt sources to identify the source of CPU NMI Default 0x3FF Bit field Table Bits 7 6 5 4 3 2 1 0 Name SYSTEM_INT_IDX 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 SYSTEM...

Page 717: ...s this field to 1 This effectively results in a CM0 reset followed by a CM0 warm boot 1 Enabled Note The intent is that this bit is modified only through an external probe or by the CM4 while the CM0...

Page 718: ...18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 SLEEPING R W 0 Specifies if the CPU is in Active Sleep or DeepSleep power...

Page 719: ...range 0 255 Note that this field is retained However the counter that is used to implement the division is not and will be initialized by HW to 0 when transitioning from DeepSleep to Active power mode...

Page 720: ...n 0 9 SYSTEM_INT_IDX R W Undefined Lowest CM0 activated system interrupt index for CPU interrupt 0 Multiple system interrupts can be mapped on the same CPU interrupt The selected system interrupt is t...

Page 721: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 722: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 723: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 724: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 725: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 726: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 727: ...8 Name None 15 10 SYSTEM_INT_IDX 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name SYSTEM _INT _VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 728: ...15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR24 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR24 31 24 Bit fields Bits Name SW HW Default or Enum Description 8 31 ADDR24 RW 0 Address of CM0 vector table...

Page 729: ...gate all selected system interrupt sources to identify the source of CPU NMI Default 0x3FF Bit field Table Bits 7 6 5 4 3 2 1 0 Name SYSTEM_INT_IDX 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 SYSTE...

Page 730: ...CTKEYSTAT 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 PWR_MODE RW R 1 Power mode OFF 0 Switch CM4 off Power off clock off isolate reset and no retain RESET 1 Reset CM4 Clock off n...

Page 731: ...eld Table Bits 7 6 5 4 3 2 1 0 Name UP 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 UP 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits N...

Page 732: ...Memory wait states for the slow clock domain clk_slow The number of wait states is expressed in clk_hf clock domain cycles 8 9 FAST_WS RW R 0 Memory wait states for the fast clock domain clk_fast The...

Page 733: ...Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 WB_EMPTY R W 1 Write buffer empty This information is...

Page 734: ...27 26 25 24 Name VECTKEYSTAT 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 PWR_MODE RW R 3 SRAM Power mode OFF 0 Turn OFF the SRAM This will trun OFF both array and periphery power...

Page 735: ...s 15 14 13 12 11 10 9 8 Name None 15 10 FAST_WS 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 19 ECC_INJ_E N 18 18 ECC_AUTO _ CORRECT 17 17 ECC_EN 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bi...

Page 736: ...em SRAM controller 1 Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 WB _EMPTY 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 2...

Page 737: ...6 5 4 3 2 1 0 Name None 7 2 PWR_MODE 1 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name VECTKEYSTAT 23 16 Bits 31 30 29 28 27 26 25 24 Name VECTKEYSTAT 31 24 Bit fields Bi...

Page 738: ...lt 0x96 Bit field Table Bits 7 6 5 4 3 2 1 0 Name UP 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 UP 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit...

Page 739: ...emory wait states for the slow clock domain clk_slow The number of wait states is expressed in clk_hf clock domain cycles Timing paths to and from the memory have a fixed minimum duration that always...

Page 740: ...escription 0 24 WORD_ADDR RW R 0 Specifies the word address where an error will be injected On a write transfer to this SRAM address and when the corresponding RAM0 RAM1 RAM2_CTL0 ECC_INJ_EN bit is 1...

Page 741: ...Name MINOR_REV 23 20 MAJOR_REV 19 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 11 FAMILY_ID R W FAMILYID Family ID a k a Partnumber a k a Si...

Page 742: ...24 Bit fields Bits Name SW HW Default or Enum Description 0 SWJ_CONNECTED R W 0 Specifies if the SWJ debug port is connected i e debug host interface is active 0 Not connected not active 1 Connected a...

Page 743: ...16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 CM0_ENABLE RW R 0 Enables the CM0 AP interface 0 Disabled 1 Enabled 1 CM4_ENABLE RW R 0 Ena...

Page 744: ...RW1S R 0 Disables the system AP interface 0 Enabled 1 Disabled Typically this field is set by the Cypress boot code with information from eFUSE The access port is only enabled when SYS_DISABLE is 0 an...

Page 745: ...GROUP_FAULT_15 only for the existing peripheral groups to report decoder or peripheral bus errors in the peripheral groups The CPU can perform a read transfer after a series of write transfers to the...

Page 746: ...d The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator imprecise or a device external crystal oscillator precise 1 The internal main oscillato...

Page 747: ...port Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24...

Page 748: ...Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24 Bit fields Bits Name SW HW Defau...

Page 749: ...7 4 VALID 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Descriptio...

Page 750: ...0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fields Bits Name SW HW Default or Enum Descripti...

Page 751: ...fault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fie...

Page 752: ...fault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fie...

Page 753: ...fault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fie...

Page 754: ...20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 STATE RW R 0 Protection state 0 UNKNOWN 1 VIRGIN 2 NORMAL 3 SECUR...

Page 755: ...AULT 0x0000_0002 ROM_TRIM_WIDTH 3 For Synopsys ROMs the bits are defined as follows 3 0 RM Read Write margin control This is used for setting the Read Write margin It programs the sense amplifier diff...

Page 756: ...to trim ALL RAM memories in the device Different operating Voltages may require different trim settings Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name TRIM 7 0 Bits 15 14 13 12 11 10 9 8 Name T...

Page 757: ...access time and cycle time of the memory RM 1 0 0 is the slowest possible mode of operation for the memory This setting is required for VDDMIN operation RM 3 2 are factory pins reserved for debug mode...

Page 758: ...s mapped E g if CPU_INT_IDX is 6 the system interrupt is mapped to CPU interrupt 6 Note it is possible to map multiple system interrupts to the same CPU interrupt It is advised to assign different pri...

Page 759: ...efault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 CPU_INT_IDX 2 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name C...

Page 760: ...ad CXPI0_CH0_RX_FIFO_RD_SILENT 0x405180AC FULL RX FIFO silent read CXPI0_CH0_INTR 0x405180C0 FULL Interrupt CXPI0_CH0_INTR_SET 0x405180C4 FULL Interrupt set CXPI0_CH0_INTR_MASK 0x405180C8 FULL Interru...

Page 761: ..._MASKED 0x405182CC FULL Interrupt masked 7 4 CH 3 This instance is not available in the following part numbers CYT2BL3BAS CYT2BL3BAE CYT2BL3CAS CYT2BL3CAE CYT2BL4BAS CYT2BL4BAE CYT2BL4CAS CYT2BL4CAE C...

Page 762: ..._IDX RW R 0 Specifies the channel index of the channel to which HW injected channel transmitter errors applies 18 TX_CRC_ERROR RW R 0 The crc field is inverted At the receiver this should result in IN...

Page 763: ...ce Manual 002 29852 Rev B Bits Name SW HW Default or Enum Description 31 ENABLED RW R 0 Error injection enable 0 Disabled 1 Enabled 763 2022 04 18 TRAVEO T2G Automotive MCU TVII B E 4M body controller...

Page 764: ...lds Bits Name SW HW Default or Enum Description 0 4 CH_IDX RW R 0 Specifies the channel index of the channel to which test applies The channel IO signals of channel indices CH_IDX and CH_NR 1 are conn...

Page 765: ...isolation allows for device test without effecting an operational cxpi cluster tx_in CH_IDX cxpi_tx_out CH_IDX tx_in CH_NR 1 cxpi_tx_out CH_IDX rx_in CH_IDX cxpi_tx_out CH_IDX rx_in CH_NR 1 cxpi_tx_ou...

Page 766: ...ORE 27 27 None 26 25 IBS 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 MODE RW R 0 Mode of operation 0 NRZ mode 1 PWM mode NRZ 0 NRZ mode PWM 1 PWM mode 4 AUTO_EN RW R 1 CXPI transcei...

Page 767: ...to get the total idle time For example if TIMEOUT_LENGTH 9 and IFS needed is 20 then CTL0 IFS is set to 10 21 24 IBS RW R 0 Inter Byte Space in bit periods 0 No offset 1 1 IBS is inserted per every b...

Page 768: ...orted CONT_TX_MSG 1 Message transfer is NOT aborted 30 MASTER RW R 0 CXPI master mode 0 Indicates CXPI as slave node 1 Indicates CXPI as master node This bit is only valid if ENABLED 1 SW needs to set...

Page 769: ...Enum Description 0 8 T_LOW1 RW R 0 Low count for logic 1 This is valid only for PWM mode The count value here indicates the number of clocks per clk_cxpi_ch to drive a 0 at CXPI bus before releasing...

Page 770: ...in HW as below 0 means 1 clock after detecting falling edge of rx 1 means 2 clocks after detecting falling edge of rx 7 means 8 clocks after detecting falling edge of rx 15 means 16 clocks after detec...

Page 771: ...fulfilled IFS If SW wants to manage the retransmission then SW can program RETRY 0 In this case HW will not retry after arbitration lost and will set TX_HEADER_ARB_LOST bit SW needs to trigger HW to...

Page 772: ...after receiving any frame bytes within a message frame HW will hold the counter if timeout until the IFS Timeout will cause HW to stop transmission of the current message frame and notify SW with int...

Page 773: ...RX_FRAME _ERROR 29 29 TX _UNDERF LOW _ERROR 28 28 RX _UNDERF LOW _ERROR 27 27 TX _OVERFL OW _ERROR 26 26 RX _OVERFL OW _ERROR 25 25 TX_DATA _LENGTH _ERROR 24 24 Bit fields Bits Name SW HW Default or E...

Page 774: ...ER RX_RESPONSE 18 TIMEOUT R W 0 Copy of INTR TIMEOUT 19 TX_HEADER_ARB_LOST R W 0 Copy of INTR TX_HEADER_ARB_LOST 20 TX_BIT_ERROR R W 0 Copy of INTR TX_BIT_ERROR 21 RX_CRC_ERROR R W 0 Copy of INTR RX_C...

Page 775: ...eive message frames are as below TX_HEADER RX_HEADER RX_RESPONSE WAIT_IFS for master slave in event trigger that is performing transmit PID and follow by receiving response For master in polling that...

Page 776: ...iven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer SW clears this field to 0 when it wants to cancel a pending request Note that if SW clears this...

Page 777: ...n this field is set to 1 When SW clears this field is from 1 to 0 in Standby mode HW will move to Normal mode while HW starts transmitting clock To transmit wake pulse SW need to program TX_WAKE_PULSE...

Page 778: ...bits are received INTR RX_HEADER_PID_DONE and INTR RX_HEADER_DONE Typically a slave node SW sets both RX_HEADER and RX_RESPONSE to 1 anticipating a transfer of a response from the master node to this...

Page 779: ...IN can be used to determine a wakeup source Note that wakeup source detection relies on the external transceiver functionality 17 RX_IN R W Undefined CXPI receiver input rx_in cxpi_rx_in in functional...

Page 780: ...re the bit 7 if SW occupies this bit Transmission To be transmitted PID field HW will ignore bit 7 and compute the parity bit based on bits 6 0 Note that this field can be use by SW to send PType byte...

Page 781: ...PID field to determine how to handle the response for a received frame header TX_RESPONSE or RX_RESPONSE Note that this field can be use by SW to check PType byte as the HW handles both PID and PType...

Page 782: ...or both CRC8 and CRC16 This is valid for both Normal frame and Long frame HW will load this field with first byte of CRC upon receiving it 8 15 RXCRC2 R RW Undefined CRC second byte of CRC16 This is v...

Page 783: ...vel When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated INTR TX_FIFO_TRIGGER FIFO entries TRIGGER_LEVEL 16 CLEAR RW R 0 This is a synchronous clear...

Page 784: ...Bits Name SW HW Default or Enum Description 0 4 USED R W 0 Number of used occupied entries in the TX FIFO The field value is in the range 0 16 When 0 the TX FIFO is empty When 16 the TX FIFO is full...

Page 785: ...or Enum Description 0 7 DATA W R 0 Transmit Data field Transmission To be transmitted data field SW provides data field HW shadows over the write data to TX FIFO after SW performs a write to this fiel...

Page 786: ...tion 0 4 TRIGGER_LEVEL RW R 0 Trigger level When RX FIFO has more entries than the number of this field a receiver trigger event is generated INTR_RX FIFO_TRIGGER FIFO entries TRIGGER_LEVEL 16 CLEAR R...

Page 787: ...e SW HW Default or Enum Description 0 4 USED R W 0 Number of used occupied entries in the RX FIFO The field value is in the range 0 16 When 0 the RX FIFO is empty When 16 the RX FIFO is full 16 20 AVA...

Page 788: ...a field HW shadows the first content of the RX FIFO to this field Software reading this field will remove the content from the RX FIFO and the next content of the RX FIFO will be shadowed over to this...

Page 789: ...field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name...

Page 790: ...action may assert before the full Tbit of the stop bit Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 TX_FIFO_T RIGGER 4 4 TX _WAKEUP _DONE 3 3 None 2 2 TX _RESPON SE_DONE 1 1 TX _HEAD...

Page 791: ...EADER_DONE RW1C RW1S 0 HW sets this field to 1 when a frame header PID field or PType field is received the CMD RX_HEADER is completed Specifically When followed by CMD TX_RESPONSE or CMD RX_RESPONSE...

Page 792: ...sponse Note The ongoing message transfer is aborted INTR RX_RESPONSE_DONE is NOT activated 22 RX_HEADER_PARITY _ERROR RW1C RW1S 0 HW sets this field to 1 when the received PID field or PType field has...

Page 793: ...ferred at CXPI will be bogus and HW will invert the CRC to invalidate the message at the receiving node TX_HEADER and TX_RESPONSE commands are set to 0 29 RX_FRAME_ERROR RW1C RW1S 0 HW sets this field...

Page 794: ...ion 0 TX_HEADER_DONE RW1S A 0 Write INTR_SET field with 1 to set corresponding INTR field a write of 0 has no effect 1 TX_RESPONSE_DONE RW1S A 0 Write INTR_SET field with 1 to set corresponding INTR f...

Page 795: ...NTR field a write of 0 has no effect 24 TX_DATA_LENGTH _ERROR RW1S A 0 Write INTR_SET field with 1 to set corresponding INTR field a write of 0 has no effect 25 RX_OVERFLOW _ERROR RW1S A 0 Write INTR_...

Page 796: ...ask for corresponding field in INTR register 1 TX_RESPONSE_DONE RW R 0 Mask for corresponding field in INTR register 3 TX_WAKEUP_DONE RW R 0 Mask for corresponding field in INTR register 4 TX_FIFO_TRI...

Page 797: ...OVERFLOW_ERROR RW R 0 Mask for corresponding field in INTR register 27 RX_UNDERFLOW _ERROR RW R 0 Mask for corresponding field in INTR register 28 TX_UNDERFLOW _ERROR RW R 0 Mask for corresponding fie...

Page 798: ...23 23 RX _HEADER _PARITY _ERROR 22 22 RX_CRC _ERROR 21 21 TX_BIT_ER ROR 20 20 TX _HEADER _ARB _LOST 19 19 TIMEOUT 18 18 None 17 16 Bits 31 30 29 28 27 26 25 24 Name None 31 31 TX_FRAME _ERROR 30 30 R...

Page 799: ...l AND of corresponding INTR and INTR_MASK fields 23 RX_DATA_LENGTH _ERROR R W 0 Logical AND of corresponding INTR and INTR_MASK fields 24 TX_DATA_LENGTH _ERROR R W 0 Logical AND of corresponding INTR...

Page 800: ...t masked 8 2 CH 1 Register Name Address Permission Description DMAC_CH1_CTL 0x402A1100 FULL Channel control DMAC_CH1_IDX 0x402A1110 FULL Channel current indices DMAC_CH1_SRC 0x402A1114 FULL Channel cu...

Page 801: ...402A1300 FULL Channel control DMAC_CH3_IDX 0x402A1310 FULL Channel current indices DMAC_CH3_SRC 0x402A1314 FULL Channel current source address DMAC_CH3_DST 0x402A1318 FULL Channel current destination...

Page 802: ...20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLED 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 31 ENABLED RW R 0 IP enable 0 Disabled All non retenti...

Page 803: ...7 6 5 4 3 2 1 0 Name ACTIVE 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default...

Page 804: ...ransaction write data All transactions for this channel use the P field for the user privileged access control hprot 1 1 NS RW R 1 Secure on secure access control 0 secure 1 non secure This field is s...

Page 805: ...sts of a contiguous sequence of channel activations within this priority group without any repetition Within a round higher priority is given to the lower channel indices The notion of a round guarant...

Page 806: ...Bits 31 30 29 28 27 26 25 24 Name Y 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 X R W Undefined Specifies the X loop index In the range of 0 X_COUNT with X_COUNT taken from the...

Page 807: ...lt 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fields...

Page 808: ...lt 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fields...

Page 809: ...8 Name PTR 15 8 Bits 23 22 21 20 19 18 17 16 Name PTR 23 16 Bits 31 30 29 28 27 26 25 24 Name PTR 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 31 PTR RW RW Undefined Address of curr...

Page 810: ...ATE 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 ACT...

Page 811: ...2 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name VALID 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 31 VALID R W 0 I...

Page 812: ...the selected system trigger is not active This field is used to synchronize the controller with the agent that generated the trigger This field is ONLY used at the completion of the transfer as specif...

Page 813: ...s 1D or 2D the output trigger is generated after the execution of a 1D transfer If the descriptor type is memory copy the output trigger is generated after the execution of a memory copy transfer If t...

Page 814: ...gher 24 bits are made 0 DATA is 8 bit SRC is 32 bit higher 24 bits are dropped DST is 32 bit higher 24 bits are made 0 DATA is 16 bit SRC is 16 bit DST is 16 bit DATA is 16 bit SRC is 32 bit higher 16...

Page 815: ...IZE and DESCR_X_INCR registers are present the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present A 1D transfer consists out of DESCR_X_SIZE X_COUNT 1 single transfers The DESCR_NEXT_PTR is at offset 0x14...

Page 816: ...ntly active descriptor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 2...

Page 817: ...ently active descriptor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25...

Page 818: ...31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 X_COUNT R W Undefined Number of iterations minus 1 of the X loop X_COUNT 1 is the number of single...

Page 819: ...5 SRC_X R W Undefined Specifies increment of source address for each X loop iteration in multiples of SRC_TRANSFER_SIZE This field is a signed number sign magnitude format in the range 32768 32767 If...

Page 820: ...Bits 15 14 13 12 11 10 9 8 Name Y_COUNT 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 Y_COU...

Page 821: ...18 17 16 Name DST_Y 23 16 Bits 31 30 29 28 27 26 25 24 Name DST_Y 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 SRC_Y R W Undefined Specifies increment of source address for each...

Page 822: ...s at offset 0x1c For a memory copy transfer descriptor type this register is at offset 0x10 For a scatter transfer descriptor type this register is at offset 0x0c Default 0x0 Bit field Table Bits 7 6...

Page 823: ...0 Activated set to 1 on completion of data transfer s as specified by the descriptor s CH_DESCR_CTL INTR_TYPE 1 SRC_BUS_ERROR RW1C RW1S 0 Activated set to 1 on a bus error for a load from the source 2...

Page 824: ...write of 0 has no effect 1 SRC_BUS_ERROR RW1S A 0 Write this field with 1 to set INTR SRC_BUS_ERROR field to 1 a write of 0 has no effect 2 DST_BUS_ERROR RW1S A 0 Write this field with 1 to set INTR D...

Page 825: ...ts 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 COMPLETION RW R 0 Mask for INTR COMPLETION interrupt 1 SRC_BUS_ERROR RW R 0 Mask for INTR SRC_BUS_ER...

Page 826: ...23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 COMPLETION R W 0 Logical and of corresponding INTR COMPLETION and INTR_MASK COMPLETION fiel...

Page 827: ...LL Channel current indices DW0_CH_STRUCT0_CH_CURR_PTR 0x4028800C FULL Channel current descriptor pointer DW0_CH_STRUCT0_INTR 0x40288010 FULL Interrupt DW0_CH_STRUCT0_INTR_SET 0x40288014 FULL Interrupt...

Page 828: ...x40288110 FULL Interrupt DW0_CH_STRUCT4_INTR_SET 0x40288114 FULL Interrupt set DW0_CH_STRUCT4_INTR_MASK 0x40288118 FULL Interrupt mask DW0_CH_STRUCT4_INTR_MASKED 0x4028811C FULL Interrupt masked DW0_C...

Page 829: ...gger 9 1 1 10 CH_STRUCT 9 Register Name Address Permission Description DW0_CH_STRUCT9_CH_CTL 0x40288240 FULL Channel control DW0_CH_STRUCT9_CH_STATUS 0x40288244 FULL Channel status DW0_CH_STRUCT9_CH_I...

Page 830: ...0288350 FULL Interrupt DW0_CH_STRUCT13_INTR_SET 0x40288354 FULL Interrupt set DW0_CH_STRUCT13_INTR_MASK 0x40288358 FULL Interrupt mask DW0_CH_STRUCT13_INTR_MASKED 0x4028835C FULL Interrupt masked DW0_...

Page 831: ...ware trigger 9 1 1 19 CH_STRUCT 18 Register Name Address Permission Description DW0_CH_STRUCT18_CH_CTL 0x40288480 FULL Channel control DW0_CH_STRUCT18_CH_STATUS 0x40288484 FULL Channel status DW0_CH_S...

Page 832: ...0288590 FULL Interrupt DW0_CH_STRUCT22_INTR_SET 0x40288594 FULL Interrupt set DW0_CH_STRUCT22_INTR_MASK 0x40288598 FULL Interrupt mask DW0_CH_STRUCT22_INTR_MASKED 0x4028859C FULL Interrupt masked DW0_...

Page 833: ...ware trigger 9 1 1 28 CH_STRUCT 27 Register Name Address Permission Description DW0_CH_STRUCT27_CH_CTL 0x402886C0 FULL Channel control DW0_CH_STRUCT27_CH_STATUS 0x402886C4 FULL Channel status DW0_CH_S...

Page 834: ...02887D0 FULL Interrupt DW0_CH_STRUCT31_INTR_SET 0x402887D4 FULL Interrupt set DW0_CH_STRUCT31_INTR_MASK 0x402887D8 FULL Interrupt mask DW0_CH_STRUCT31_INTR_MASKED 0x402887DC FULL Interrupt masked DW0_...

Page 835: ...ware trigger 9 1 1 37 CH_STRUCT 36 Register Name Address Permission Description DW0_CH_STRUCT36_CH_CTL 0x40288900 FULL Channel control DW0_CH_STRUCT36_CH_STATUS 0x40288904 FULL Channel status DW0_CH_S...

Page 836: ...0288A10 FULL Interrupt DW0_CH_STRUCT40_INTR_SET 0x40288A14 FULL Interrupt set DW0_CH_STRUCT40_INTR_MASK 0x40288A18 FULL Interrupt mask DW0_CH_STRUCT40_INTR_MASKED 0x40288A1C FULL Interrupt masked DW0_...

Page 837: ...ware trigger 9 1 1 46 CH_STRUCT 45 Register Name Address Permission Description DW0_CH_STRUCT45_CH_CTL 0x40288B40 FULL Channel control DW0_CH_STRUCT45_CH_STATUS 0x40288B44 FULL Channel status DW0_CH_S...

Page 838: ...0288C50 FULL Interrupt DW0_CH_STRUCT49_INTR_SET 0x40288C54 FULL Interrupt set DW0_CH_STRUCT49_INTR_MASK 0x40288C58 FULL Interrupt mask DW0_CH_STRUCT49_INTR_MASKED 0x40288C5C FULL Interrupt masked DW0_...

Page 839: ...ware trigger 9 1 1 55 CH_STRUCT 54 Register Name Address Permission Description DW0_CH_STRUCT54_CH_CTL 0x40288D80 FULL Channel control DW0_CH_STRUCT54_CH_STATUS 0x40288D84 FULL Channel status DW0_CH_S...

Page 840: ...0288E90 FULL Interrupt DW0_CH_STRUCT58_INTR_SET 0x40288E94 FULL Interrupt set DW0_CH_STRUCT58_INTR_MASK 0x40288E98 FULL Interrupt mask DW0_CH_STRUCT58_INTR_MASKED 0x40288E9C FULL Interrupt masked DW0_...

Page 841: ...ware trigger 9 1 1 64 CH_STRUCT 63 Register Name Address Permission Description DW0_CH_STRUCT63_CH_CTL 0x40288FC0 FULL Channel control DW0_CH_STRUCT63_CH_STATUS 0x40288FC4 FULL Channel status DW0_CH_S...

Page 842: ...02890D0 FULL Interrupt DW0_CH_STRUCT67_INTR_SET 0x402890D4 FULL Interrupt set DW0_CH_STRUCT67_INTR_MASK 0x402890D8 FULL Interrupt mask DW0_CH_STRUCT67_INTR_MASKED 0x402890DC FULL Interrupt masked DW0_...

Page 843: ...ware trigger 9 1 1 73 CH_STRUCT 72 Register Name Address Permission Description DW0_CH_STRUCT72_CH_CTL 0x40289200 FULL Channel control DW0_CH_STRUCT72_CH_STATUS 0x40289204 FULL Channel status DW0_CH_S...

Page 844: ...0289310 FULL Interrupt DW0_CH_STRUCT76_INTR_SET 0x40289314 FULL Interrupt set DW0_CH_STRUCT76_INTR_MASK 0x40289318 FULL Interrupt mask DW0_CH_STRUCT76_INTR_MASKED 0x4028931C FULL Interrupt masked DW0_...

Page 845: ...ware trigger 9 1 1 82 CH_STRUCT 81 Register Name Address Permission Description DW0_CH_STRUCT81_CH_CTL 0x40289440 FULL Channel control DW0_CH_STRUCT81_CH_STATUS 0x40289444 FULL Channel status DW0_CH_S...

Page 846: ...0289550 FULL Interrupt DW0_CH_STRUCT85_INTR_SET 0x40289554 FULL Interrupt set DW0_CH_STRUCT85_INTR_MASK 0x40289558 FULL Interrupt mask DW0_CH_STRUCT85_INTR_MASKED 0x4028955C FULL Interrupt masked DW0_...

Page 847: ...A1 0x40289664 FULL SRAM data 1 DW0_CH_STRUCT89_TR_CMD 0x40289668 FULL Channel software trigger 9 1 1 91 CH_STRUCT 90 Register Name Address Permission Description DW0_CH_STRUCT90_CH_CTL 0x40289680 FULL...

Page 848: ...0_INTR_MASKED 0x4029801C FULL Interrupt masked DW1_CH_STRUCT0_SRAM_DATA0 0x40298020 FULL SRAM data 0 DW1_CH_STRUCT0_SRAM_DATA1 0x40298024 FULL SRAM data 1 DW1_CH_STRUCT0_TR_CMD 0x40298028 FULL Channel...

Page 849: ...L Channel control DW1_CH_STRUCT5_CH_STATUS 0x40298144 FULL Channel status DW1_CH_STRUCT5_CH_IDX 0x40298148 FULL Channel current indices DW1_CH_STRUCT5_CH_CURR_PTR 0x4029814C FULL Channel current descr...

Page 850: ...40298258 FULL Interrupt mask DW1_CH_STRUCT9_INTR_MASKED 0x4029825C FULL Interrupt masked DW1_CH_STRUCT9_SRAM_DATA0 0x40298260 FULL SRAM data 0 DW1_CH_STRUCT9_SRAM_DATA1 0x40298264 FULL SRAM data 1 DW1...

Page 851: ...Channel control DW1_CH_STRUCT14_CH_STATUS 0x40298384 FULL Channel status DW1_CH_STRUCT14_CH_IDX 0x40298388 FULL Channel current indices DW1_CH_STRUCT14_CH_CURR_PTR 0x4029838C FULL Channel current des...

Page 852: ...NTR_MASK 0x40298498 FULL Interrupt mask DW1_CH_STRUCT18_INTR_MASKED 0x4029849C FULL Interrupt masked DW1_CH_STRUCT18_SRAM_DATA0 0x402984A0 FULL SRAM data 0 DW1_CH_STRUCT18_SRAM_DATA1 0x402984A4 FULL S...

Page 853: ...Channel control DW1_CH_STRUCT23_CH_STATUS 0x402985C4 FULL Channel status DW1_CH_STRUCT23_CH_IDX 0x402985C8 FULL Channel current indices DW1_CH_STRUCT23_CH_CURR_PTR 0x402985CC FULL Channel current des...

Page 854: ...NTR_MASK 0x402986D8 FULL Interrupt mask DW1_CH_STRUCT27_INTR_MASKED 0x402986DC FULL Interrupt masked DW1_CH_STRUCT27_SRAM_DATA0 0x402986E0 FULL SRAM data 0 DW1_CH_STRUCT27_SRAM_DATA1 0x402986E4 FULL S...

Page 855: ...Channel control DW1_CH_STRUCT32_CH_STATUS 0x40298804 FULL Channel status DW1_CH_STRUCT32_CH_IDX 0x40298808 FULL Channel current indices DW1_CH_STRUCT32_CH_CURR_PTR 0x4029880C FULL Channel current des...

Page 856: ...NTR_MASK 0x40298918 FULL Interrupt mask DW1_CH_STRUCT36_INTR_MASKED 0x4029891C FULL Interrupt masked DW1_CH_STRUCT36_SRAM_DATA0 0x40298920 FULL SRAM data 0 DW1_CH_STRUCT36_SRAM_DATA1 0x40298924 FULL S...

Page 857: ...Channel control DW1_CH_STRUCT41_CH_STATUS 0x40298A44 FULL Channel status DW1_CH_STRUCT41_CH_IDX 0x40298A48 FULL Channel current indices DW1_CH_STRUCT41_CH_CURR_PTR 0x40298A4C FULL Channel current des...

Page 858: ...NTR_MASK 0x40298AD8 FULL Interrupt mask DW1_CH_STRUCT43_INTR_MASKED 0x40298ADC FULL Interrupt masked DW1_CH_STRUCT43_SRAM_DATA0 0x40298AE0 FULL SRAM data 0 DW1_CH_STRUCT43_SRAM_DATA1 0x40298AE4 FULL S...

Page 859: ...31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 0 ECC_EN RW R 1 Enable ECC checking 0 Disabled 1 Enabled 1 ECC_INJ_EN RW R 0 Enable parity injection for SRAM When 1 the parity EC...

Page 860: ...cure access control 0 secure 1 non secure 2 B R RW Undefined Active channel non bufferable bufferable access control 0 non bufferable 1 bufferable 4 7 PC R RW Undefined Active channel protection conte...

Page 861: ...etention Not Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits...

Page 862: ...gle transfer If the descriptor type is 1D or 2D the trigger results in the execution of a 1D transfer 2 A trigger results in the execution of the current descriptor 3 A trigger results in the executio...

Page 863: ...is 32 bit higher 16 bits are dropped DST is 32 bit higher 16 bits are made 0 DATA is 32 bit SRC is 32 bit DST002 is 32 bit 31 30 DESCR_TYPE Specifies the descriptor type not to be confused withthe tri...

Page 864: ...ESCR_NEXT_PTR is at offset 0x14 A 2D transfer consists of DESCR_X_CTL X_COUNT DESCR_Y_CTL Y_COUNT single transfers 3 CRC transfer The DESCR_X_CTL register is present theDESCR_Y_CTL is not present and...

Page 865: ...7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24 Bit fields Bits Name SW HW Default or...

Page 866: ...it fields Bits Name SW HW Default or Enum Description 0 31 DATA R W Undefined Copy of DESCR_DST of the currently active descriptor Base address of destination location Note For a CRC transfer descript...

Page 867: ...tiples of SRC_TRANSFER_SIZE This field is a signed number in the range 2048 2047 If this field is 0 the source address is not incremented This is useful for reading from RX FIFO structures 23 12 DST_X...

Page 868: ...py of DESCR_Y_CTL of the currently active descriptor 11 0 SRC_Y_INCR Specifies increment of source address for each Y loop iteration in multiples of SRC_TRANSFER_SIZE This field is a signed number in...

Page 869: ...12 11 10 9 8 Name ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 31 ADDR R W Undefined Cop...

Page 870: ...le Bits 7 6 5 4 3 2 1 0 Name SRC_ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name SRC_ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name SRC_ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name SRC_ADDR 31 24 Bit fields Bit...

Page 871: ...le Bits 7 6 5 4 3 2 1 0 Name DST_ADDR 7 0 Bits 15 14 13 12 11 10 9 8 Name DST_ADDR 15 8 Bits 23 22 21 20 19 18 17 16 Name DST_ADDR 23 16 Bits 31 30 29 28 27 26 25 24 Name DST_ADDR 31 24 Bit fields Bit...

Page 872: ...19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name PARITY 31 25 None 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 9 WORD_ADDR RW R 0 Specifies the word address where an e...

Page 873: ...19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 DATA_REVERSE RW R 0 Specifies the bit order in which a data Byte is p...

Page 874: ...1 0 Name DATA_XOR 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum De...

Page 875: ...IAL RW R 0 CRC polynomial The polynomial is represented WITHOUT the high order bit this bit is always assumed 1 The polynomial should be aligned shifted such that the more significant bits bit 31 and...

Page 876: ...efault or Enum Description 0 31 LFSR32 RW RW 0 State of a 32 bit Linear Feedback Shift Registers LFSR that is used to implement CRC This register needs to be initialized by SW to provide the CRC seed...

Page 877: ...its 15 14 13 12 11 10 9 8 Name REM_XOR 15 8 Bits 23 22 21 20 19 18 17 16 Name REM_XOR 23 16 Bits 31 30 29 28 27 26 25 24 Name REM_XOR 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31...

Page 878: ...6 Bits 31 30 29 28 27 26 25 24 Name REM 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 REM R W 0 Remainder value The alignment of the remainder depends on CRC_REM_CTL0 REM_REVERSE 0...

Page 879: ...r privileged access control of the transaction that writes this register i e the write data is ignored and instead the access control is inherited from the write transaction note the field attributes...

Page 880: ...robin arbitration is applied Round robin arbitration within a priority group gives the highest priority to the lower channel indices within the priority group 11 PREEMPTABLE RW R Undefined Specifies...

Page 881: ...rupt generated 1 Interrupt based on transfer complettion configuration based on INTR_TYPE 2 Source transfer bus error 3 Destination transfer bus error 4 Source address misalignment 5 Destination addre...

Page 882: ...ndefined Specifies the X loop index In the range of 0 X_COUNT with X_COUNT taken from the current descriptor Note HW sets this field to 0 when it updates the current descriptor pointer CH_CURR_PTR wit...

Page 883: ...23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 31 ADDR RW RW Undefined Address of current descriptor When this field is 0 there is no valid...

Page 884: ...0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 CH 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit f...

Page 885: ...x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 CH 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fie...

Page 886: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 CH 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields...

Page 887: ...ation rather than two load operations one for INTR and one for INTR_MASK This simplifies Firmware development The associated interrupt is active 1 when INTR_MASKED 0 Default 0x0 Bit field Table Bits 7...

Page 888: ...es only update a subset of a 32 bit SRAM data word For ECC fault injection it is required to update a complete 32 bit SRAM data word with a user provided ECC parity specified by ECC_CTL PARITY at a sp...

Page 889: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24...

Page 890: ...CTIVATE 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0...

Page 891: ...via CMx EFUSE_DATA_CUSTOMER_DATA2 0x402C0870 NO ACCESS Available EFUSE bits for customer usage They can be programmed in NORMAL protection state via CMx DAP and in SECURE protection state via CMx EFU...

Page 892: ...tion is in progress CMD START is 1 results in an AHB Lite bus error The number of eFUSE memory Bytes is determined by the EFUSE_NR configuration parameter This parameter specifies the number of instan...

Page 893: ...unctionality 12 2 COMP_STRUCT 1 Register Name Address Permission Description EVTGEN0_COMP_STRUCT1_COMP_CTL 0x403F0820 FULL Comparator control EVTGEN0_COMP_STRUCT1_COMP0 0x403F0824 FULL Comparator 0 Ac...

Page 894: ...GEN0_COMP_STRUCT8_COMP_CTL 0x403F0900 FULL Comparator control EVTGEN0_COMP_STRUCT8_COMP0 0x403F0904 FULL Comparator 0 Active functionality EVTGEN0_COMP_STRUCT8_COMP1 0x403F0908 FULL Comparator 1 DeepS...

Page 895: ...21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLED 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 31 ENABLED RW R 0 IP enable 0 Disabled All non rete...

Page 896: ...Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP0_OUT 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP0_OUT 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 3...

Page 897: ...ble Bits 7 6 5 4 3 2 1 0 Name COMP1_OUT 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP1_OUT 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Nam...

Page 898: ...None 30 24 Bit fields Bits Name SW HW Default or Enum Description 31 VALID R W 0 Active counter validity 0 Invalid 1 Valid The COUNTER register field INT32 is only valid when VALID is 1 The COUNTER_S...

Page 899: ...ble Bits 7 6 5 4 3 2 1 0 Name INT32 7 0 Bits 15 14 13 12 11 10 9 8 Name INT32 15 8 Bits 23 22 21 20 19 18 17 16 Name INT32 23 16 Bits 31 30 29 28 27 26 25 24 Name INT32 31 24 Bit fields Bits Name SW H...

Page 900: ...ATIO value 15 RATIO measurement 8 16 4 new RATIO value 31 RATIO measurement 16 32 5 new RATIO value 63 RATIO measurement 32 64 6 new RATIO value 127 RATIO measurement 64 128 7 new RATIO value 255 RATI...

Page 901: ...me SW HW Default or Enum Description 31 VALID RW RW1S 0 Ratio value valid 0 Invalid 1 Valid The RATIO register fields INT16 and FRAC8 are only valid when VALID is 1 901 2022 04 18 TRAVEO T2G Automotiv...

Page 902: ...ns the average number of clk_ref_div cycles per clk_lf cycle Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name FRAC8 15 8 Bits 23 22 21 20 19 18 17 16 Name...

Page 903: ...5 4 3 2 1 0 Name INT_DIV 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or...

Page 904: ...9 8 Name COMP0 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 COMP0 RW1C RW1S 0 This interru...

Page 905: ...n HW to activate the interrupt cause The interrupt causes are deactivated when the IP is disabled CTL ENABLED is 0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP0 7 0 Bits 15 14 13 12 11 1...

Page 906: ...ld Table Bits 7 6 5 4 3 2 1 0 Name COMP0 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP0 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name S...

Page 907: ...INTR and INTR_MASK registers Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP0 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP0 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27...

Page 908: ...2 1 0 Name COMP1 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP1 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 909: ...ows for debug of the SW ISR without relying on HW to activate the interrupt cause Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP1 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP1 15 8 Bits 23 22...

Page 910: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP1 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP1 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bit...

Page 911: ...n the INTR and INTR_MASK registers Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name COMP1 7 0 Bits 15 14 13 12 11 10 9 8 Name COMP1 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29...

Page 912: ...Description 0 COMP0_EN RW R 0 Active comparator COMP0 enable 0 Disabled The comparator output comp0_out is 0 1 Enabled 1 COMP1_EN RW R 0 DeepSleep comparator COMP1 enable 0 Disabled The comparator ou...

Page 913: ...s 23 22 21 20 19 18 17 16 Name INT32 23 16 Bits 31 30 29 28 27 26 25 24 Name INT32 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 INT32 RW R Undefined This value is a 32 bit unsigne...

Page 914: ...3 22 21 20 19 18 17 16 Name INT32 23 16 Bits 31 30 29 28 27 26 25 24 Name INT32 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 INT32 RW R Undefined This value is a 32 bit unsigned i...

Page 915: ...AULT_STRUCT1_DATA2 0x40210118 FULL Fault data FAULT_STRUCT1_DATA3 0x4021011C FULL Fault data FAULT_STRUCT1_PENDING0 0x40210140 FULL Fault pending 0 FAULT_STRUCT1_PENDING1 0x40210144 FULL Fault pending...

Page 916: ...10318 FULL Fault data FAULT_STRUCT3_DATA3 0x4021031C FULL Fault data FAULT_STRUCT3_PENDING0 0x40210340 FULL Fault pending 0 FAULT_STRUCT3_PENDING1 0x40210344 FULL Fault pending 1 FAULT_STRUCT3_PENDING...

Page 917: ...bled The trigger output tr_fault reflects STATUS VALID The trigger can be used to initiate a Datawire transfer of the FAULT data FAULT_DATA0 through FAULT_DATA3 1 OUT_EN RW R 0 IO output signal enable...

Page 918: ...DATA3 should only be considered valid when VALID is 1 MPU_0 0 Bus master 0 MPU SMPU DATA0 31 0 Violating address DATA1 0 User read DATA1 1 User write DATA1 2 User execute DATA1 3 Privileged read DATA1...

Page 919: ...Privileged write DATA1 5 Privileged execute DATA1 6 Non secure DATA1 11 8 Master identifier DATA1 15 12 Protection context identifier DATA1 31 28 0 master interface PPU violation 1 timeout detected 2...

Page 920: ...A0 26 0 Violating address Append 5 b00010 as most significant bits to derive 32 bit system address FAULT_DATA1 11 8 Master identifier FLASHC_MAIN_C_ECC 49 Flash controller main interface correctable E...

Page 921: ...61 System SRAM 1 non correctable ECC error See RAMC0_C_ECC description RAMC2_C_ECC 62 System SRAM 2 correctable ECC error See RAMC0_C_ECC description RAMC2_NC_ECC 63 System SRAM 2 non correctable ECC...

Page 922: ...CAN0_NC_ECC description SRSS_CSV 90 SRSS Clock SuperVisor CSV violation detected Multiple CSV can detect a violation at the same time DATA0 15 0 CSV violation occurred on corresponding clk_hf root cl...

Page 923: ...a fault source index different to one of the defined HW fault sources SW update is not restricted by the MASK registers In both use case scenarios the following holds STATUS IDX DATA0 DATA3 can only...

Page 924: ...Sleep reset Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA...

Page 925: ...same for ALL fault structures i e these registers are NOT qualified by the fault structure specific MASK0 MASK1 and MASK2 registers Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SOURCE 7 0 Bi...

Page 926: ...30 29 28 27 26 25 24 Name SOURCE 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 SOURCE R W Undefined This field specifies the following sources Bit 0 Peripheral group 0 PPU Bit 1 P...

Page 927: ...s 7 6 5 4 3 2 1 0 Name SOURCE 7 0 Bits 15 14 13 12 11 10 9 8 Name SOURCE 15 8 Bits 23 22 21 20 19 18 17 16 Name SOURCE 23 16 Bits 31 30 29 28 27 26 25 24 Name SOURCE 31 24 Bit fields Bits Name SW HW D...

Page 928: ...d the mask fields of the fault structures overlap the same source is enabled for multiple fault structures an overlapping enabled pending fault source is captured by a single fault structure that has...

Page 929: ...able Bits 7 6 5 4 3 2 1 0 Name SOURCE 7 0 Bits 15 14 13 12 11 10 9 8 Name SOURCE 15 8 Bits 23 22 21 20 19 18 17 16 Name SOURCE 23 16 Bits 31 30 29 28 27 26 25 24 Name SOURCE 31 24 Bit fields Bits Name...

Page 930: ...able Bits 7 6 5 4 3 2 1 0 Name SOURCE 7 0 Bits 15 14 13 12 11 10 9 8 Name SOURCE 15 8 Bits 23 22 21 20 19 18 17 16 Name SOURCE 23 16 Bits 31 30 29 28 27 26 25 24 Name SOURCE 31 24 Bit fields Bits Name...

Page 931: ...FAULT RW1C RW1S 0 This interrupt cause field is activated HW sets the field to 1 when an enabled MASK0 MASK1 MASK2 pending fault source is captured STATUS VALID is set to 1 STATUS IDX specifies the fa...

Page 932: ...r debug of the SW ISR without relying on HW to activate the interrupt cause Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 FAULT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 2...

Page 933: ...ld Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 FAULT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bit...

Page 934: ...INTR and INTR_MASK registers Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 FAULT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30...

Page 935: ...us 0 FLASHC_CM4_CA_STATUS1 0x402404C4 FULL CM4 cache status 1 FLASHC_CM4_CA_STATUS2 0x402404C8 FULL CM4 cache status 2 FLASHC_CM4_STATUS 0x402404E0 FULL CM4 interface status FLASHC_CRYPTO_BUFF_CTL 0x4...

Page 936: ..._WS RW R 0 FLASH macro main interface wait states 0 0 wait states 15 15 wait states 8 MAIN_MAP RW R 0 Specifies mapping of FLASH macro main array 0 Mapping A 1 Mapping B This field is only used when M...

Page 937: ...ers Non CPU bus transfers always have a bus transfer with a bus error in case of a non recoverable error Note All CPU bus masters have dedicated status registers CM0_STATUS and CM4_STATUS to register...

Page 938: ...e s cache and or buffer This field is ONLY used by CPU and debug i e SYS_AP CM0_AP CM4_AP bus transfers Non CPU bus transfers always have a bus transfer with a bus error in case of a non recoverable e...

Page 939: ...ory is 10us Twake1 So SW has to wait for 10us to read from Flash after turning the Flash memory ON though this register Default 0x3 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 2 ENABLE _HV 1 1 EN...

Page 940: ...sets this field to 0 when the operation is completed The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks The caches LRU structures are also reset to...

Page 941: ...ding CM0 4_CA_CTL RAM_ECC_INJ_EN bit is 1 the parity PARITY 6 0 is injected and stored in the cache For FLASH main interface ECC the word address WORD_ADDR 23 0 is device address A 26 3 On a FLASH mai...

Page 942: ...6 5 4 3 2 1 0 Name ECC_INJ_DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name ECC_INJ_DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name ECC_INJ_DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name ECC_INJ_DATA 31 24 Bit fie...

Page 943: ...Bits 7 6 5 4 3 2 1 0 Name None 7 7 ECC_INJ_PARITY 6 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bit...

Page 944: ...s 7 6 5 4 3 2 1 0 Name CORRECTED_DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name CORRECTED_DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name CORRECTED_DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name CORRECTED_DATA 31...

Page 945: ...INJ_EN RW RW1C 0 eCT Flash SRAM ECC error injection test enable Follow the steps below for ECC logic test 1 Write corrupted or uncorrupted 39 bit data to FM_SRAM_ECC_CTL0 1 registers 2 Set the ECC_INJ...

Page 946: ...nabled 1 RAM_ECC_INJ_EN RW R 0 Enable error injection for cache When 1 the parity ECC_CTL PARITY 6 0 is used when a refill is done from the FLASH macro to the ECC_CTL WORD_ADDR 23 0 word address 16 17...

Page 947: ...quence a Write CM0_CA_CTL0 to disable cache b Write CM0_CA_CTL1 to turn OFF cache SRAM Turn ON sequence a Write CM0_CA_CTL1 to turn ON cache SRAM b Delay to allow power up of cache SRAM Delay should b...

Page 948: ...6 5 4 3 2 1 0 Name PWRUP_DELAY 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 PWRUP_DELAY 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits...

Page 949: ...4 3 2 1 0 Name VALID32 7 0 Bits 15 14 13 12 11 10 9 8 Name VALID32 15 8 Bits 23 22 21 20 19 18 17 16 Name VALID32 23 16 Bits 31 30 29 28 27 26 25 24 Name VALID32 31 24 Bit fields Bits Name SW HW Defa...

Page 950: ...7 6 5 4 3 2 1 0 Name TAG 7 0 Bits 15 14 13 12 11 10 9 8 Name TAG 15 8 Bits 23 22 21 20 19 18 17 16 Name TAG 23 16 Bits 31 30 29 28 27 26 25 24 Name TAG 31 24 Bit fields Bits Name SW HW Default or Enu...

Page 951: ...ame None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 5 LRU R W Undefined Six bit LRU representation of the cache set specified by CM0_CA...

Page 952: ...escription 0 MAIN_INTERNAL_ERR RW1C W1S 0 Specifies registers the occurrence of a FLASH macro main interface internal error typically the result of a read access while a program erase operation is ong...

Page 953: ...ult or Enum Description 0 RAM_ECC_EN RW R 1 See CM0_CA_CTL 1 RAM_ECC_INJ_EN RW R 0 See CM0_CA_CTL 16 17 WAY RW R 0 Specifies the cache way for which cache information is provided in CM4_CA_STATUS0 1 2...

Page 954: ...equence a Write CM4_CA_CTL0 to disable cache b Write CM4_CA_CTL1 to turn OFF cache SRAM Turn ON sequence a Write CM4_CA_CTL1 to turn ON cache SRAM b Delay to allow power up of cache SRAM Delay should...

Page 955: ...6 5 4 3 2 1 0 Name PWRUP_DELAY 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 PWRUP_DELAY 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits...

Page 956: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALID32 7 0 Bits 15 14 13 12 11 10 9 8 Name VALID32 15 8 Bits 23 22 21 20 19 18 17 16 Name VALID32 23 16 Bits 31 30 29 28 27 26 25 24 Name VALID32 31...

Page 957: ...nt Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name TAG 7 0 Bits 15 14 13 12 11 10 9 8 Name TAG 15 8 Bits 23 22 21 20 19 18 17 16 Name TAG 23 16 Bits 31 30 29 28 27 26 25 24 Name TAG 31 24 Bit fi...

Page 958: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 6 LRU 5 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24...

Page 959: ...escription 0 MAIN_INTERNAL_ERR RW1C W1S 0 Specifies registers the occurrence of a FLASH macro main interface internal error typically the result of a read access while a program erase operation is ong...

Page 960: ...3 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 31 PREF_EN 30 30 None 29 24 Bit fields Bits Name SW HW Default or Enum Description...

Page 961: ...0000000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 31 PREF_EN 3...

Page 962: ...0000000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 31 PREF_EN 3...

Page 963: ...0x40000000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 31 PREF_E...

Page 964: ...omment The register fields are related to C interface functionality Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 FM_MODE 4 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 2...

Page 965: ...program d8 Program 64b CODE Used as program confirm command for 64 Code bits program d9 Program 256b CODE Used as program confirm command for 256 Code bits program d10 Program Page CODE Used as progra...

Page 966: ...16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name MARGIN _MODE _EN 31 31 MARGIN _MODE _RDREG_C HNG_EN 30 30 MARGIN _PGM_ERS _B 29 29 None 28 24 Bit fields Bits Name SW HW Default or Enum Descriptio...

Page 967: ...the address definition for R bus code_r_addr and work_r_addr This FM_ADDR should be used whenever a user mode embedded operation is done on the Flash i e PGM ERS Default 0x0 Bit field Table Bits 7 6 5...

Page 968: ...None 7 1 INTR 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Descri...

Page 969: ...3 2 1 0 Name None 7 1 INTR_SET 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Defaul...

Page 970: ...Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 INTR _MASK 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields B...

Page 971: ...able Bits 7 6 5 4 3 2 1 0 Name None 7 1 INTR _MASKED 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields...

Page 972: ...12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ECC _OVERR IDE_CODE 31 31 ECC _OVERR IDE_WORK 30 30 None 29 24 Bit fields Bits Name SW HW Def...

Page 973: ...at can be done per pgm command 64 256 page for Code or 32 to work flash and therefore the sequence must be correct These register are related to C interface functionality Default 0x0 Bit field Table B...

Page 974: ...0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name BOOKMARK 7 0 Bits 15 14 13 12 11 10 9 8 Name BOOKMARK 15 8 Bits 23 22 21 20 19 18 17 16 Name BOOKMARK 23 16 Bits 31 30 29 28 27 26 25 24 Name BOOKMARK 31...

Page 975: ...3 2 1 0 Name None 7 1 MAINFLASH WRITEENABL E 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Nam...

Page 976: ...efault or Enum Description 0 PGM_CODE R W 0 Indicates if active PGM operation to the Code flash is taking place 0 not running 1 running 1 PGM_WORK R W 0 Indicates if active PGM operation to the Work f...

Page 977: ...Set it is not cleaned till additional POR rst_hf_ac_t 0 No error 1 ECC 2b Error in POR 29 NATIVE_POR R W 0 Indicates a Native Flash state UV or sorted one Valid only after 2nd phase of POR FUR DOWNLO...

Page 978: ...2 1 0 Name None 7 1 WORKFLASH WRITEENABL E 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name...

Page 979: ...masked status register Note EDGE4 EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT0_INTR_SET 0x40310020 FULL Port interrupt set register Note EDGE4 EDGE5 EDGE6 EDGE7 are not available fo...

Page 980: ...sion Description GPIO_PRT2_OUT 0x40310100 FULL Port output data register Note OUT6 OUT7 are not available for this register GPIO_PRT2_OUT_CLR 0x40310104 FULL Port output data clear register GPIO_PRT2_...

Page 981: ...buffer AUTOLVL configuration register Note VTRIP_SEL6_1 VTRIP_SEL7_1 are not available for this register 15 5 PRT 4 Register Name Address Permission Description GPIO_PRT4_OUT 0x40310200 FULL Port out...

Page 982: ...PIO_PRT5_CFG_OUT 0x403102CC FULL Port output buffer configuration register Note SLOW0 SLOW1 SLOW2 SLOW3 SLOW4 SLOW5 SLOW6 SLOW7 DRIVE_SEL6 DRIVE_SEL7 are not available for this register GPIO_PRT5_CFG_...

Page 983: ...er GPIO_PRT8_INTR_MASKED 0x4031041C FULL Port interrupt masked status register Note EDGE5 EDGE6 EDGE7 are not available for this register GPIO_PRT8_INTR_SET 0x40310420 FULL Port interrupt set register...

Page 984: ...8 FULL Port output data set register GPIO_PRT10_OUT_INV 0x4031050C FULL Port output data invert register GPIO_PRT10_IN 0x40310510 FULL Port input state register GPIO_PRT10_INTR 0x40310514 FULL Port in...

Page 985: ...NTR 0x40310614 FULL Port interrupt status register GPIO_PRT12_INTR_MASK 0x40310618 FULL Port interrupt mask register GPIO_PRT12_INTR_MASKED 0x4031061C FULL Port interrupt masked status register GPIO_P...

Page 986: ...ister Note IN4 IN5 IN6 IN7 are not available for this register GPIO_PRT15_INTR 0x40310794 FULL Port interrupt status register Note EDGE4 EDGE5 EDGE6 EDGE7 IN_IN4 IN_IN5 IN_IN6 IN_IN7 are not available...

Page 987: ...Port input buffer AUTOLVL configuration register Note VTRIP_SEL4_1 VTRIP_SEL5_1 VTRIP_SEL6_1 VTRIP_SEL7_1 are not available for this register 15 18 PRT 17 Register Name Address Permission Description...

Page 988: ...L EDGE7_SEL are not available for this register GPIO_PRT19_CFG 0x403109C4 FULL Port configuration register Note DRIVE_MODE5 IN_EN5 DRIVE_MODE6 IN_EN6 DRIVE_MODE7 IN_EN7 are not available for this regi...

Page 989: ...t interrupt mask register GPIO_PRT22_INTR_MASKED 0x40310B1C FULL Port interrupt masked status register GPIO_PRT22_INTR_SET 0x40310B20 FULL Port interrupt set register GPIO_PRT22_INTR_CFG 0x40310B40 FU...

Page 990: ...Name SW HW Default or Enum Description 0 31 PORT_INT R W 0 Each IO port has an associated bit field in this register The bit field reflects the IO port s interrupt line bit field i reflects gpio_inter...

Page 991: ...or off chip analog resources need to provide it For these bits to work reliable the supply must be within valid spec range per datasheet or held at ground Any in between voltage has an undefined resu...

Page 992: ...a supply ramp up or ramp down is detected Some bits may be set after system power up depending on power supply sequencing Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VDDIO_ACTIVE 7 0 Bits 15...

Page 993: ...Table Bits 7 6 5 4 3 2 1 0 Name VDDIO_ACTIVE 7 0 Bits 15 14 13 12 11 10 9 8 Name VDDIO_ACTIVE 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name VDDD _ACTIVE 31 31 VD...

Page 994: ...8 Name VDDIO_ACTIVE 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name VDDD _ACTIVE 31 31 VDDA _ACTIVE 30 30 None 29 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 995: ...Bits 7 6 5 4 3 2 1 0 Name VDDIO_ACTIVE 7 0 Bits 15 14 13 12 11 10 9 8 Name VDDIO_ACTIVE 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name VDDD _ACTIVE 31 31 VDDA _AC...

Page 996: ...field Table Bits 7 6 5 4 3 2 1 0 Name OUT7 7 7 OUT6 6 6 OUT5 5 5 OUT4 4 4 OUT3 3 3 OUT2 2 2 OUT1 1 1 OUT0 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bi...

Page 997: ...4 OUT3 3 3 OUT2 2 2 OUT1 1 1 OUT0 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Def...

Page 998: ...UT4 4 4 OUT3 3 3 OUT2 2 2 OUT1 1 1 OUT0 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW...

Page 999: ...OUT2 2 2 OUT1 1 1 OUT0 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or En...

Page 1000: ...HW Default or Enum Description 0 IN0 R W 0 IO pin state for pin 0 0 Low logic level present on pin 1 High logic level present on pin On reset assertion IN register will get reset The Pad value takes...

Page 1001: ...5 21 21 IN_IN4 20 20 IN_IN3 19 19 IN_IN2 18 18 IN_IN1 17 17 IN_IN0 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 25 FLT_IN_IN 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 EDGE0 RW1...

Page 1002: ...None 15 9 FLT_EDGE 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 EDGE0 RW R 0 Masks edge inter...

Page 1003: ...0 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 EDGE0 R W 0 Edge detected AND masked on IO pin 0 0 Interrupt was not forwarded to CPU 1 Interrupt occurred...

Page 1004: ...16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 EDGE0 RW1S A 0 Sets edge detect interrupt for IO pin 0 0 Interrupt state not affected 1 Interr...

Page 1005: ...Falling edge BOTH 3 Both rising and falling edges 2 3 EDGE1_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 1 4 5 EDGE2_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 2 6 7 EDGE3_...

Page 1006: ...26 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 DRIVE_MODE0 RW R 0 The GPIO drive mode for IO pin 0 Resistive pull up and pull down is selected in the drive mode Note when initializi...

Page 1007: ...0 Weak resistive pull down D_OUT 1 Strong pull up When D_OUT_EN 0 D_OUT 0 High impedance D_OUT 1 High impedance For peripherals other than GPIO UDB DSI When D_OUT_EN 1 D_OUT 0 Strong pull down D_OUT 1...

Page 1008: ...pull down For GPIO UDB DSI peripherals When D_OUT_EN 0 GPIO_DSI_OUT 0 Weak resistive pull down GPIO_DSI_OUT 1 Weak resistive pull up where GPIO_DSI_OUT is a function of PORT_SEL OUT DSI_DATA_OUT For...

Page 1009: ...r for IO pin 4 20 22 DRIVE_MODE5 RW R 0 The GPIO drive mode for IO pin 5 23 IN_EN5 RW R 0 Enables the input buffer for IO pin 5 24 26 DRIVE_MODE6 RW R 0 The GPIO drive mode for IO pin 6 27 IN_EN6 RW R...

Page 1010: ...trip points and hysteresis CMOS 0 PSoC 6 Input buffer compatible with CMOS and I2C interfaces Traveo II Full encoding is shown in CFG_IN_AUTOLVL VTRIP_SEL0_1 TTL 1 PSoC 6 Input buffer compatible with...

Page 1011: ...W R 0 Enables slow slew rate for IO pin 1 2 SLOW2 RW R 0 Enables slow slew rate for IO pin 2 3 SLOW3 RW R 0 Enables slow slew rate for IO pin 3 4 SLOW4 RW R 0 Enables slow slew rate for IO pin 4 5 SLO...

Page 1012: ...MC GPIO 1 4 drive strength Traveo II _HSIO_STD GPIO 1 4 drive strength PSoC 6 GPIO cells and HSIO_STD cells 1 8 drive strength GPIO drives current at 1 8 of its max rated spec 18 19 DRIVE_SEL1 RW R 0...

Page 1013: ...L0_0 field as below CFG_IN_AUTOLVL VTRIP_SEL0_1 CFG_IN VTRIP_SEL0_0 0 0 CMOS 0 1 TTL 1 0 input buffer is compatible with automotive 1 1 input buffer is compatible with automotvie CMOS_OR_TTL 0 Input b...

Page 1014: ...are not available for this register 16 4 PRT 3 Register Name Address Permission Description HSIOM_PRT3_PORT_SEL0 0x40300030 FULL Port selection 0 HSIOM_PRT3_PORT_SEL1 0x40300034 FULL Port selection 1...

Page 1015: ..._SEL0 0x403000D0 FULL Port selection 0 HSIOM_PRT13_PORT_SEL1 0x403000D4 FULL Port selection 1 16 15 PRT 14 Register Name Address Permission Description HSIOM_PRT14_PORT_SEL0 0x403000E0 FULL Port selec...

Page 1016: ...0 FULL Port selection 0 HSIOM_PRT21_PORT_SEL1 0x40300154 FULL Port selection 1 16 23 PRT 22 Register Name Address Permission Description HSIOM_PRT22_PORT_SEL0 0x40300160 FULL Port selection 0 HSIOM_PR...

Page 1017: ...SWITCH _AA_SR 1 1 SWITCH _AA_SL 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Defau...

Page 1018: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name MONITOR_EN 7 0 Bits 15 14 13 12 11 10 9 8 Name MONITOR_EN 15 8 Bits 23 22 21 20 19 18 17 16 Name MONITOR_EN 23 16 Bits 31 30 29 28 27 26 25 24 Name MONITOR_E...

Page 1019: ...Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLE 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enu...

Page 1020: ...7 5 IO0_SEL 4 0 Bits 15 14 13 12 11 10 9 8 Name None 15 13 IO1_SEL 12 8 Bits 23 22 21 20 19 18 17 16 Name None 23 21 IO2_SEL 20 16 Bits 31 30 29 28 27 26 25 24 Name None 31 29 IO3_SEL 28 24 Bit fields...

Page 1021: ...ipheral 12 ACT_13 25 Active peripheral 13 ACT_14 26 Active peripheral 14 ACT_15 27 Active peripheral 15 DS_4 28 Deep Sleep peripheral 4 DS_5 29 Deep Sleep peripheral 5 DS_6 30 Deep Sleep peripheral 6...

Page 1022: ...20 19 18 17 16 Name None 23 21 IO6_SEL 20 16 Bits 31 30 29 28 27 26 25 24 Name None 31 29 IO7_SEL 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 IO4_SEL RW RW 0 Selects the peripher...

Page 1023: ...IPC_STRUCT2_DATA0 0x4022004C FULL IPC data 0 IPC_STRUCT2_DATA1 0x40220050 FULL IPC data 1 IPC_STRUCT2_LOCK_STATUS 0x4022005C FULL IPC lock status 17 4 STRUCT 3 Register Name Address Permission Descrip...

Page 1024: ...dress Permission Description IPC_INTR_STRUCT1_INTR 0x40221020 FULL Interrupt IPC_INTR_STRUCT1_INTR_SET 0x40221024 FULL Interrupt set IPC_INTR_STRUCT1_INTR_MASK 0x40221028 FULL Interrupt mask IPC_INTR_...

Page 1025: ...6_INTR_SET 0x402210C4 FULL Interrupt set IPC_INTR_STRUCT6_INTR_MASK 0x402210C8 FULL Interrupt mask IPC_INTR_STRUCT6_INTR_MASKED 0x402210CC FULL Interrupt masked 17 16 INTR_STRUCT 7 Register Name Addre...

Page 1026: ...attempt Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name PC 7 4 None 3 2 NS 1 1 P 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 12 MS 11 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 2...

Page 1027: ...nsaction and not released The P NS PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock the fields are NOT affected by the current access 1 S...

Page 1028: ...W HW Default or Enum Description 0 15 INTR_RELEASE W 0 Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acqu...

Page 1029: ...Bit fields Bits Name SW HW Default or Enum Description 0 15 INTR_NOTIFY W 0 This field allows for the generation of notification events to the IPC interrupt structures The IPC notification cause field...

Page 1030: ...5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24 Bit fields Bits Name SW HW Default or Enum...

Page 1031: ...5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24 Bit fields Bits Name SW HW Default or Enum...

Page 1032: ...ield specifies the user privileged access control 0 user mode 1 privileged mode 1 NS R W Undefined This field specifies the secure non secure access control 0 secure 1 non secure 4 7 PC R W Undefined...

Page 1033: ...IFY 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 RELEASE RW1C RW1S 0 These interrupt cause fields are activated HW sets the field to 1 when a IPC release event is detected One bit...

Page 1034: ...te the interrupt cause Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name RELEASE 7 0 Bits 15 14 13 12 11 10 9 8 Name RELEASE 15 8 Bits 23 22 21 20 19 18 17 16 Name NOTIFY 23 16 Bits 31 30 29 28 27...

Page 1035: ...ASE 7 0 Bits 15 14 13 12 11 10 9 8 Name RELEASE 15 8 Bits 23 22 21 20 19 18 17 16 Name NOTIFY 23 16 Bits 31 30 29 28 27 26 25 24 Name NOTIFY 31 24 Bit fields Bits Name SW HW Default or Enum Descriptio...

Page 1036: ...0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name RELEASE 7 0 Bits 15 14 13 12 11 10 9 8 Name RELEASE 15 8 Bits 23 22 21 20 19 18 17 16 Name NOTIFY 23 16 Bits 31 30 29 28 27 26 25 24 Name NOTIFY 31 24 Bit...

Page 1037: ...ommand LIN0_CH1_TX_RX_STATUS 0x40508160 FULL TX RX status LIN0_CH1_PID_CHECKSUM 0x40508180 FULL PID and checksum LIN0_CH1_DATA0 0x40508184 FULL Response data 0 LIN0_CH1_DATA1 0x40508188 FULL Response...

Page 1038: ...2BL4CAS CYT2BL4CAE CYT2BL5BAS CYT2BL5BAE CYT2BL5CAS CYT2BL5CAE Register Name Address Permission Description LIN0_CH5_CTL0 0x40508500 FULL Control 0 LIN0_CH5_CTL1 0x40508504 FULL Control 1 LIN0_CH5_STA...

Page 1039: ...FULL Interrupt masked 18 10 CH 9 Register Name Address Permission Description LIN0_CH9_CTL0 0x40508900 FULL Control 0 LIN0_CH9_CTL1 0x40508904 FULL Control 1 LIN0_CH9_STATUS 0x40508908 FULL Status LIN...

Page 1040: ...rol 1 LIN0_CH11_STATUS 0x40508B08 FULL Status LIN0_CH11_CMD 0x40508B10 FULL Command LIN0_CH11_TX_RX_STATUS 0x40508B60 FULL TX RX status LIN0_CH11_PID_CHECKSUM 0x40508B80 FULL PID and checksum LIN0_CH1...

Page 1041: ...4 Bit fields Bits Name SW HW Default or Enum Description 0 4 CH_IDX RW R 0 Specifies the channel index of the channel to which HW injected channel transmitter errors applies 16 TX_SYNC_ERROR RW R 0 Th...

Page 1042: ...T mode 22 TX_CHECKSUM_ERROR RW R 0 The checksum field is inverted At the receiver this should result in INTR RX_RESPONSE_CHECKSUM_ERROR activation 23 TX_CHECKSUM_STOP _ERROR RW R 0 The checksum field...

Page 1043: ...lds Bits Name SW HW Default or Enum Description 0 4 CH_IDX RW R 0 Specifies the channel index of the channel to which test applies The channel IO signals of channel indices CH_IDX and CH_NR 1 are conn...

Page 1044: ...OSS HSIOM should disconnect tx_out from the tx IO cell This mode s isolation allows for device test without effecting an operational LIN cluster tx_in CH_IDX lin_tx_out CH_IDX tx_in CH_NR 1 lin_tx_out...

Page 1045: ...30 30 PARITY _EN 29 29 PARITY 28 28 BIT _ERROR _IGNORE 27 27 None 26 25 MODE 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 STOP_BITS RW R 1 STOP bit periods 0 1 2 bit period 1 1 bi...

Page 1046: ...functions are mutually exclusive When CMD TX_HEADER is 1 the field specifies the transmitted break field When CMD TX_WAKEUP is 1 the field specifies the transmitted wakeup field When CMD RX_HEADER is...

Page 1047: ...PARITY_EN RW R 0 Parity generation enable 0 Disabled No parity bit is transferred 1 Enabled The parity bit is transferred after the last most significant data field bit Note Used in UART mode only 30...

Page 1048: ...of at least 1 data field and the CHECKSUM_ENHANCED and DATA_NR fields need to be set BEFORE the receipt of the STOP bit s of the first data field i e SW effectively has a data field transfer duration...

Page 1049: ...nom The nominal header length Theader_nom is 34 bit periods and the nominal response length Tresponse_nom is 10 data_nr 1 bit periods data_nr is the number of data fields Note the LIN specification sp...

Page 1050: ...24 Name None 31 29 RX _RESPON SE _CHECKSU M_ERROR 28 28 RX _RESPON SE_FRAME _ERROR 27 27 RX _HEADER _PARITY _ERROR 26 26 RX _HEADER _SYNC _ERROR 25 25 RX _HEADER _FRAME _ERROR 24 24 Bit fields Bits N...

Page 1051: ...et at Break filed rising edge in RX_RESPONSE case set at the start bit falling edge in the first response data byte Set to 0 on successful completion of previous commands or when an error is detected...

Page 1052: ...l 002 29852 Rev B Bits Name SW HW Default or Enum Description 28 RX_RESPONSE _CHECKSUM_ERROR R W 0 Copy of INTR RX_RESPONSE_CHECKSUM_ERROR 1052 2022 04 18 TRAVEO T2G Automotive MCU TVII B E 4M body co...

Page 1053: ...ive but are evaluated in the following order of decreasing priority TX_RESPONSE RX_RESPONSE The CMD TX_HEADER register field description provides all legal command sequences The break or wakeup detect...

Page 1054: ...the jitter that is typically associated with SW driven transfer In UART mode a single data field DATA0 DATA1 is transmitted 1 TX_RESPONSE RW1S RW1C 0 SW sets this field to 1 to transmit a response HW...

Page 1055: ...performed regardless of CMD RX_HEADER INTR RX_BREAK_WAKEUP_DONE will trigger at LIN_RX rising edge when the low pulse meet CTL0 BREAK_WAKEUP_LENGTH when Break is detected HW check CMD RX_HEADER before...

Page 1056: ...ERI PCLK divider value should be decreased If SYNC_COUNTER is greater than 128 the LIN channel clock is too fast and the PERI PCLK divider value should be increased The biggest master slave clock disc...

Page 1057: ...s field to enable the external transceiver Before a legal command sequence HW sets this field to 1 if it is 0 The start of the command sequence is effectively postponed by a 4 bit period preamble Afte...

Page 1058: ...r ID 5 0 Frame identifier 0x3c is for a master request frame 0x3d is for a slave response frame 0x3e and 0x3f are for future LIN enhancements Frame identifier ID 5 4 is optionally used for length cont...

Page 1059: ...the received data fields provided by HW Data field DATA1 is the first response data field first to be transmitted received The number of transmitted received data fields is specified by CTL DATA_NR De...

Page 1060: ...fault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA5 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA6 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA7 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA8 31 24 Bit...

Page 1061: ...RX_HEADER_FRAME_ERROR and RX_HEADER_PARITY_ERROR interrupt causes only Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 TX _WAKEUP _DONE 2 2 TX _RESPON SE_DONE 1 1 TX _HEADER _DONE 0 0 B...

Page 1062: ...reak field synchronization field and PID field is received the CMD RX_HEADER is completed Specifically When followed by CMD TX_RESPONSE or CMD RX_RESPONSE this field is set to 1 after completion of th...

Page 1063: ...k SYNC and the PID fields for the START bit data Byte and STOP bit Note When CTL BIT_ERROR_IGNORE is 0 the ongoing message transfer is aborted INTR TX_HEADER_DONE is NOT activated and the TX_HEADER TX...

Page 1064: ...ata field has a parity error when CTL0 PARITY_EN is 1 27 RX_RESPONSE_FRAME _ERROR RW1C RW1S 0 HW sets this field to 1 when the received START or STOP bits have an unexpected value during response rece...

Page 1065: ...TX_HEADER_DONE RW1S A 0 Write INTR_SET field with 1 to set corresponding INTR field a write of 0 has no effect 1 TX_RESPONSE_DONE RW1S A 0 Write INTR_SET field with 1 to set corresponding INTR field a...

Page 1066: ...R field a write of 0 has no effect 25 RX_HEADER_SYNC _ERROR RW1S A 0 Write INTR_SET field with 1 to set corresponding INTR field a write of 0 has no effect 26 RX_HEADER_PARITY _ERROR RW1S A 0 Write IN...

Page 1067: ...ds Bits Name SW HW Default or Enum Description 0 TX_HEADER_DONE RW R 0 Mask for corresponding field in INTR register 1 TX_RESPONSE_DONE RW R 0 Mask for corresponding field in INTR register 2 TX_WAKEUP...

Page 1068: ...in INTR register 26 RX_HEADER_PARITY _ERROR RW R 0 Mask for corresponding field in INTR register 27 RX_RESPONSE_FRAME _ERROR RW R 0 Mask for corresponding field in INTR register 28 RX_RESPONSE _CHECKS...

Page 1069: ..._HEADER _DONE 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 18 TX _RESPON SE_BIT _ERROR 17 17 TX _HEADER _BIT _ERROR 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 29 RX _RESPON SE _CHECKSU M_ERROR...

Page 1070: ...f corresponding INTR and INTR_MASK fields 24 RX_HEADER_FRAME _ERROR R W 0 Logical AND of corresponding INTR and INTR_MASK fields 25 RX_HEADER_SYNC _ERROR R W 0 Logical AND of corresponding INTR and IN...

Page 1071: ...ntrol PASS0_SAR0_CH0_SAMPLE_CTL 0x40900804 FULL Sample control PASS0_SAR0_CH0_POST_CTL 0x40900808 FULL Post processing control PASS0_SAR0_CH0_RANGE_CTL 0x4090080C FULL Range thresholds PASS0_SAR0_CH0_...

Page 1072: ...e register PASS0_SAR0_CH3_TR_CMD 0x409008FC FULL Software triggers 19 1 5 CH 4 Register Name Address Permission Description PASS0_SAR0_CH4_TR_CTL 0x40900900 FULL Trigger control PASS0_SAR0_CH4_SAMPLE_...

Page 1073: ...register PASS0_SAR0_CH7_TR_CMD 0x409009FC FULL Software triggers 19 1 9 CH 8 Register Name Address Permission Description PASS0_SAR0_CH8_TR_CTL 0x40900A00 FULL Trigger control PASS0_SAR0_CH8_SAMPLE_CT...

Page 1074: ...egister PASS0_SAR0_CH11_TR_CMD 0x40900AFC FULL Software triggers 19 1 13 CH 12 Register Name Address Permission Description PASS0_SAR0_CH12_TR_CTL 0x40900B00 FULL Trigger control PASS0_SAR0_CH12_SAMPL...

Page 1075: ...egister PASS0_SAR0_CH15_TR_CMD 0x40900BFC FULL Software triggers 19 1 17 CH 16 Register Name Address Permission Description PASS0_SAR0_CH16_TR_CTL 0x40900C00 FULL Trigger control PASS0_SAR0_CH16_SAMPL...

Page 1076: ...egister PASS0_SAR0_CH19_TR_CMD 0x40900CFC FULL Software triggers 19 1 21 CH 20 Register Name Address Permission Description PASS0_SAR0_CH20_TR_CTL 0x40900D00 FULL Trigger control PASS0_SAR0_CH20_SAMPL...

Page 1077: ...triggers 19 2 SAR 1 Register Name Address Permission Description PASS0_SAR1_CTL 0x40901000 FULL Analog control register PASS0_SAR1_DIAG_CTL 0x40901004 FULL Diagnostic Reference control register PASS0...

Page 1078: ..._SAR1_CH2_INTR_MASKED 0x4090189C FULL Interrupt masked request register PASS0_SAR1_CH2_WORK 0x409018A0 FULL Working data register PASS0_SAR1_CH2_RESULT 0x409018A4 FULL Result data register PASS0_SAR1_...

Page 1079: ...SS0_SAR1_CH6_INTR_MASK 0x40901998 FULL Interrupt mask register PASS0_SAR1_CH6_INTR_MASKED 0x4090199C FULL Interrupt masked request register PASS0_SAR1_CH6_WORK 0x409019A0 FULL Working data register PA...

Page 1080: ...0_INTR_SET 0x40901A94 FULL Interrupt set request register PASS0_SAR1_CH10_INTR_MASK 0x40901A98 FULL Interrupt mask register PASS0_SAR1_CH10_INTR_MASKED 0x40901A9C FULL Interrupt masked request registe...

Page 1081: ...PASS0_SAR1_CH14_INTR 0x40901B90 FULL Interrupt request register PASS0_SAR1_CH14_INTR_SET 0x40901B94 FULL Interrupt set request register PASS0_SAR1_CH14_INTR_MASK 0x40901B98 FULL Interrupt mask regist...

Page 1082: ...g control PASS0_SAR1_CH18_RANGE_CTL 0x40901C8C FULL Range thresholds PASS0_SAR1_CH18_INTR 0x40901C90 FULL Interrupt request register PASS0_SAR1_CH18_INTR_SET 0x40901C94 FULL Interrupt set request regi...

Page 1083: ...ontrol PASS0_SAR1_CH22_POST_CTL 0x40901D88 FULL Post processing control PASS0_SAR1_CH22_RANGE_CTL 0x40901D8C FULL Range thresholds PASS0_SAR1_CH22_INTR 0x40901D90 FULL Interrupt request register PASS0...

Page 1084: ...er control PASS0_SAR1_CH26_SAMPLE_CTL 0x40901E84 FULL Sample control PASS0_SAR1_CH26_POST_CTL 0x40901E88 FULL Post processing control PASS0_SAR1_CH26_RANGE_CTL 0x40901E8C FULL Range thresholds PASS0_S...

Page 1085: ...triggers 19 2 31 CH 30 Register Name Address Permission Description PASS0_SAR1_CH30_TR_CTL 0x40901F80 FULL Trigger control PASS0_SAR1_CH30_SAMPLE_CTL 0x40901F84 FULL Sample control PASS0_SAR1_CH30_PO...

Page 1086: ...INTR_MASKED 0x4090281C FULL Interrupt masked request register PASS0_SAR2_CH0_WORK 0x40902820 FULL Working data register PASS0_SAR2_CH0_RESULT 0x40902824 FULL Result data register PASS0_SAR2_CH0_GRP_ST...

Page 1087: ...uest register PASS0_SAR2_CH4_WORK 0x40902920 FULL Working data register PASS0_SAR2_CH4_RESULT 0x40902924 FULL Result data register PASS0_SAR2_CH4_GRP_STAT 0x40902928 FULL Group status register PASS0_S...

Page 1088: ...x409029DC FULL Interrupt masked request register PASS0_SAR2_CH7_WORK 0x409029E0 FULL Working data register PASS0_SAR2_CH7_RESULT 0x409029E4 FULL Result data register PASS0_SAR2_CH7_GRP_STAT 0x409029E8...

Page 1089: ...ay is 1 us 8 IDLE_PWRDWN RW R 0 When idle automatically power down the analog After an automatic power down a new trigger will power up the analog however it will take PWRUP_TIME cycles before the fir...

Page 1090: ...SARADC analog in power down and stop clocks also clears all pending triggers 1 SAR ADC and SARSEQ are enabled To enable ADC0 to borrow SARMUX1 3 the corresponding ADC_EN must be set to 0 31 ENABLED R...

Page 1091: ...VREFH_2DIV8 2 DiagOut VrefH 2 8 VREFH_3DIV8 3 DiagOut VrefH 3 8 VREFH_4DIV8 4 DiagOut VrefH 4 8 VREFH_5DIV8 5 DiagOut VrefH 5 8 VREFH_6DIV8 6 DiagOut VrefH 6 8 VREFH_7DIV8 7 DiagOut VrefH 7 8 VREFH 8...

Page 1092: ...0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 PRECOND...

Page 1093: ..._CMD UPDATE Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name AOFFSET 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 21 AGAIN 20 16 Bits 31 30 29 28 27 26...

Page 1094: ...s 15 14 13 12 11 10 9 8 Name None 15 12 DOFFSET 11 8 Bits 23 22 21 20 19 18 17 16 Name None 23 22 DGAIN 21 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum De...

Page 1095: ...ibration Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name AOFFSET 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 21 AGAIN 20 16 Bits 31 30 29 28 27 26 25...

Page 1096: ...ration to map codes on full 12 bit range Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DOFFSET 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 12 DOFFSET 11 8 Bits 23 22 21 20 19 18 17 16 Name Non...

Page 1097: ...s Hardware will do the calibration update as soon as the ADC is idle or a continuous triggered group completes This ensures that all acquisitions within a group scan even if preempted are done with th...

Page 1098: ...Bits 7 6 5 4 3 2 1 0 Name TR_PEND 7 0 Bits 15 14 13 12 11 10 9 8 Name TR_PEND 15 8 Bits 23 22 21 20 19 18 17 16 Name TR_PEND 23 16 Bits 31 30 29 28 27 26 25 24 Name TR_PEND 31 24 Bit fields Bits Name...

Page 1099: ...4 13 12 11 10 9 8 Name WORK_VALID 15 8 Bits 23 22 21 20 19 18 17 16 Name WORK_VALID 23 16 Bits 31 30 29 28 27 26 25 24 Name WORK_VALID 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31...

Page 1100: ...bled channels will be reset Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name RANGE 7 0 Bits 15 14 13 12 11 10 9 8 Name RANGE 15 8 Bits 23 22 21 20 19 18 17 16 Name RANGE 23 16 Bits 31 30 29 28 27...

Page 1101: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ABOVE_HI 7 0 Bits 15 14 13 12 11 10 9 8 Name ABOVE_HI 15 8 Bits 23 22 21 20 19 18 17 16 Name ABOVE_HI 23 16 Bits 31 30 29 28 27 26 25 24 Name ABOVE_H...

Page 1102: ...bled channels will be reset Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name PULSE 7 0 Bits 15 14 13 12 11 10 9 8 Name PULSE 15 8 Bits 23 22 21 20 19 18 17 16 Name PULSE 23 16 Bits 31 30 29 28 27...

Page 1103: ...SULT_VALID 15 8 Bits 23 22 21 20 19 18 17 16 Name RESULT_VALID 23 16 Bits 31 30 29 28 27 26 25 24 Name RESULT_VALID 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 RESULT_VALID R RW...

Page 1104: ...Table Bits 7 6 5 4 3 2 1 0 Name ABOVE_HI 7 0 Bits 15 14 13 12 11 10 9 8 Name ABOVE_HI 15 8 Bits 23 22 21 20 19 18 17 16 Name ABOVE_HI 23 16 Bits 31 30 29 28 27 26 25 24 Name ABOVE_HI 31 24 Bit fields...

Page 1105: ...1 PWRUP _BUSY 30 30 DBG _FREEZE 29 29 None 28 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 CUR_CHAN R W 0 current channel being acquired only valid if BUSY 8 10 CUR_PRIO R W 0 priorit...

Page 1106: ...15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 20 CUR_AVG_ACCU 19 16 Bits 31 30 29 28 27 26 25 24 Name CUR_AVG_CNT 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 19 CUR_AVG_ACCU R W 0...

Page 1107: ...nel TCPWM 1 Trigger from corresponding TCPWM channel GENERIC0 2 Generic trigger input 0 GENERIC1 3 N A GENERIC2 4 N A GENERIC3 5 N A GENERIC4 6 N A CONTINUOUS 7 Always triggered also called idle can o...

Page 1108: ...pt ABORT_RESTART 1 Abort ongoing acquisition up on return Restart group from first channel ABORT_RESUME 2 Abort ongoing acquisition up on return Resume group from aborted channel If averaging discard...

Page 1109: ...t 34 Vout AmuxbusA 35 Vout AmuxbusB 36 Vout Vccd 37 Vout Vdda 38 Vout Vbg Bandgap voltage from SRSS 39 Vout Vtemp select temperature sensor Make sure that only 1 ADC is allowed to use this 40 61 Vout...

Page 1110: ...No preconditioning VREFL 1 Discharge to VREFL VREFH 2 Charge to VREFH DIAG 3 Connect the Diagnostic reference output during preconditioning The Diagnostic reference should be configured to output a r...

Page 1111: ...20MHz 31 ALT_CAL RW R Undefined Use alternate calibration values instead of the current calibration values This allows the firmware to allocate one or more channels to quietly re calibrate the ADC in...

Page 1112: ...ROC RW R Undefined Post processing NONE 0 No postprocessing AVG 1 Averaging AVG_RANGE 2 Averaging followed by Range detect RANGE 3 Range detect RANGE_PULSE 4 Range detect followed by pulse detect RESE...

Page 1113: ...fied here Software has to make sure that the result fits in less than 16 bits Any value 12 will be treated as 12 bit 4 is always ignored This can also be used to fit the 12 bit result in 8 bits Pulse...

Page 1114: ...0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name RANGE_LO 7 0 Bits 15 14 13 12 11 10 9 8 Name RANGE_LO 15 8 Bits 23 22 21 20 19 18 17 16 Name RANGE_HI 23 16 Bits 31 30 29 28 27 26 25 24 Name RANGE_HI 31 24...

Page 1115: ...w triggers were detected while the group was already busy i e triggers are too fast Write with 1 to clear bit 2 GRP_OVERFLOW RW1C RW1S 0 Overflow Interrupt hardware sets this interrupt for the last ch...

Page 1116: ...7 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 GRP_DONE_SET RW1S A 0 Write with 1 to set corresponding bit in interrupt requ...

Page 1117: ...27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 GRP_DONE_MASK RW R 0 Mask bit for corresponding bit in interrupt request register 1 GRP_CANCELLED _MASK RW R 0 Mas...

Page 1118: ...ERFL OW _MASKED 10 10 CH_PULSE _MASKED 9 9 CH _RANGE_ MASKED 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum De...

Page 1119: ...NGE _MIR 29 29 ABOVE_HI _MIR 28 28 None 27 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 WORK R RW Undefined SAR conversion working data of the channel The data is written here right...

Page 1120: ..._INTR_MIR 29 29 ABOVE_HI _MIR 28 28 None 27 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 RESULT R W Undefined SAR conversion result of the channel The data is copied here from the W...

Page 1121: ...ts 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 GRP_COMPLETE R W 0 Group acquisition complete This is a copy of the INTR GRP_DONE bit 1 GRP_CANCELLE...

Page 1122: ...Bits Name SW HW Default or Enum Description 0 CHAN_EN RW R 0 Channel enable 0 the corresponding channel is disabled Corresponding trigger will be reset immediately 1 the corresponding channel is enabl...

Page 1123: ...15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 START RW1S A 0...

Page 1124: ...MUXBUS_A VRL 0 amuxbus_a_mon VRL VRH 1 amuxbus_a_mon VRH 4 SUPPLY_MON_EN_B RW R 0 Supply monitor enable for AMUXBUS_B amuxbus_b_mon 5 SUPPLY_MON_LVL_B RW R 0 Supply monitor level select for AMUXBUS_B...

Page 1125: ...N2_SEL 11 8 Bits 23 22 21 20 19 18 17 16 Name None 23 20 IN4_SEL 19 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 IN0_SEL RW R 0 Select gen...

Page 1126: ...Name None 7 6 OUT0_SEL 5 0 Bits 15 14 13 12 11 10 9 8 Name None 15 14 OUT1_SEL 13 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW H...

Page 1127: ...r Calibration 2 TS_CAL_VB_OUT RW R 0 Voltage Base switch control for Temperature Sensor Calibration 3 TS_CAL_VE_OUT RW R 0 Voltage Emitter switch control for Temperature Sensor Calibration 4 TS_CAL_DI...

Page 1128: ...0000C54 FULL Clock control PERI_CLOCK_CTL22 0x40000C58 FULL Clock control PERI_CLOCK_CTL23 0x40000C5C FULL Clock control PERI_CLOCK_CTL24 0x40000C60 FULL Clock control PERI_CLOCK_CTL25 0x40000C64 FULL...

Page 1129: ...D44 FULL Clock control PERI_CLOCK_CTL82 0x40000D48 FULL Clock control PERI_CLOCK_CTL83 0x40000D4C FULL Clock control PERI_CLOCK_CTL84 0x40000D50 FULL Clock control PERI_CLOCK_CTL85 0x40000D54 FULL Clo...

Page 1130: ...Divider control for 8 0 divider PERI_DIV_8_CTL23 0x4000105C FULL Divider control for 8 0 divider PERI_DIV_8_CTL24 0x40001060 FULL Divider control for 8 0 divider PERI_DIV_8_CTL25 0x40001064 FULL Divid...

Page 1131: ...SABLED_12 DISABLED_13 DISABLED_14 DISABLED_15 are not available for this register 20 3 GR 2 Register Name Address Permission Description PERI_GR2_SL_CTL 0x40004050 FULL Slave control Note ENABLED_12 E...

Page 1132: ...r PERI_TR_GR0_TR_CTL6 0x40008018 FULL Trigger control register PERI_TR_GR0_TR_CTL7 0x4000801C FULL Trigger control register 20 9 TR_GR 1 Register Name Address Permission Description PERI_TR_GR1_TR_CTL...

Page 1133: ...0x40009414 FULL Trigger control register PERI_TR_GR5_TR_CTL6 0x40009418 FULL Trigger control register PERI_TR_GR5_TR_CTL7 0x4000941C FULL Trigger control register PERI_TR_GR5_TR_CTL8 0x40009420 FULL...

Page 1134: ...cription PERI_TR_1TO1_GR0_TR_CTL0 0x4000C000 FULL Trigger control register PERI_TR_1TO1_GR0_TR_CTL1 0x4000C004 FULL Trigger control register PERI_TR_1TO1_GR0_TR_CTL2 0x4000C008 FULL Trigger control re...

Page 1135: ...gister PERI_TR_1TO1_GR1_TR_CTL42 0x4000C4A8 FULL Trigger control register PERI_TR_1TO1_GR1_TR_CTL43 0x4000C4AC FULL Trigger control register PERI_TR_1TO1_GR1_TR_CTL44 0x4000C4B0 FULL Trigger control r...

Page 1136: ...ter PERI_TR_1TO1_GR2_TR_CTL38 0x4000C898 FULL Trigger control register PERI_TR_1TO1_GR2_TR_CTL39 0x4000C89C FULL Trigger control register PERI_TR_1TO1_GR2_TR_CTL40 0x4000C8A0 FULL Trigger control regi...

Page 1137: ...PERI_TR_1TO1_GR3_TR_CTL34 0x4000CC88 FULL Trigger control register PERI_TR_1TO1_GR3_TR_CTL35 0x4000CC8C FULL Trigger control register PERI_TR_1TO1_GR3_TR_CTL36 0x4000CC90 FULL Trigger control registe...

Page 1138: ...TR_1TO1_GR 6 Register Name Address Permission Description PERI_TR_1TO1_GR6_TR_CTL0 0x4000D800 FULL Trigger control register PERI_TR_1TO1_GR6_TR_CTL1 0x4000D804 FULL Trigger control register PERI_TR_1T...

Page 1139: ...RI_TR_1TO1_GR10_TR_CTL0 0x4000E800 FULL Trigger control register PERI_TR_1TO1_GR10_TR_CTL1 0x4000E804 FULL Trigger control register PERI_TR_1TO1_GR10_TR_CTL2 0x4000E808 FULL Trigger control register P...

Page 1140: ...16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 TIMEOUT RW R 65535 This field specifies a number of clock cycles clk_slow If...

Page 1141: ...ct 8 12 GROUP_SEL RW R 0 Specifies the trigger group 0 15 trigger multiplexer groups 16 31 trigger 1 to 1 groups 29 TR_EDGE RW R 0 Specifies if the activated trigger is treated as a level sensitive or...

Page 1142: ...ensitive triggers AFTER the selected trigger is activated for two clk_peri cycles Note when ACTIVATE is 1 SW should not modify the other register fields SW MUST NOT set ACTIVATE bit to 1 while updatin...

Page 1143: ...e Bits 7 6 5 4 3 2 1 0 Name DIV_SEL 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 TYPE_SEL 9 8 Bits 23 22 21 20 19 18 17 16 Name PA_DIV_SEL 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLE 31 31 DISABL...

Page 1144: ...rs are initialized to 0 If a divider is to be re enabled using different integer and fractional divider values the SW should follow these steps 0 Disable the divider using the DIV_CMD DISABLE field 1...

Page 1145: ...no divider is specified and no clock control signal s are generated When transitioning a clock between two out of phase dividers spurious clock control signals may be generated for one clk_peri cycle...

Page 1146: ...the divider does NOT have to be re enabled after transitioning from DeepSleep to Active power mode 8 15 INT8_DIV RW R 0 Integer division by 1 INT8_DIV Allows for integer divisions in the range 1 256...

Page 1147: ...NOT have to be re enabled after transitioning from DeepSleep to Active power mode 8 23 INT16_DIV RW R 0 Integer division by 1 INT16_DIV Allows for integer divisions in the range 1 65 536 Note this ty...

Page 1148: ...ions in the range 0 31 32 Note that fractional division results in clock jitter as some clock periods may be 1 clk_peri cycle longer than other clock periods Note that this field is retained However t...

Page 1149: ...17 ECC_EN 16 16 Bits 31 30 29 28 27 26 25 24 Name PARITY 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 10 WORD_ADDR RW R 0 Specifies the word address where the parity is injected On a...

Page 1150: ...7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 10 9 8 Name INT8_DIV 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default...

Page 1151: ...5 DISABLED _8 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLED_0 RW R 1 Peripheral group slave 0 enable If the slave is disabled its clock is gated off constant 0 and its resets...

Page 1152: ...ISABLED_1 RW1S R 0 N A 18 DISABLED_2 RW1S R 0 N A 19 DISABLED_3 RW1S R 0 N A 20 DISABLED_4 RW1S R 0 N A 21 DISABLED_5 RW1S R 0 N A 22 DISABLED_6 RW1S R 0 N A 23 DISABLED_7 RW1S R 0 N A 24 DISABLED_8 R...

Page 1153: ...s 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 TR_SEL RW R 0 Specifies input trigger This field is ty...

Page 1154: ...R 0 Specifies input trigger 0 constant signal level 0 1 input trigger 8 TR_INV RW R 0 Specifies if the output trigger is inverted 9 TR_EDGE RW R 0 Specifies if the inverted output trigger is treated a...

Page 1155: ...r region base address PERI_MS_PPU_PR1_MS_SIZE 0x40010064 FULL Master region size PERI_MS_PPU_PR1_MS_ATT0 0x40010070 FULL Master attributes 0 PERI_MS_PPU_PR1_MS_ATT1 0x40010074 FULL Master attributes 1...

Page 1156: ...ibutes 2 PERI_MS_PPU_PR5_SL_ATT3 0x4001015C FULL Slave attributes 3 PERI_MS_PPU_PR5_MS_ADDR 0x40010160 FULL Master region base address PERI_MS_PPU_PR5_MS_SIZE 0x40010164 FULL Master region size PERI_M...

Page 1157: ..._PPU_PR9_MS_ADDR 0x40010260 FULL Master region base address PERI_MS_PPU_PR9_MS_SIZE 0x40010264 FULL Master region size PERI_MS_PPU_PR9_MS_ATT0 0x40010270 FULL Master attributes 0 PERI_MS_PPU_PR9_MS_AT...

Page 1158: ...se address PERI_MS_PPU_PR13_MS_SIZE 0x40010364 FULL Master region size PERI_MS_PPU_PR13_MS_ATT0 0x40010370 FULL Master attributes 0 PERI_MS_PPU_PR13_MS_ATT1 0x40010374 FULL Master attributes 1 PERI_MS...

Page 1159: ...region size PERI_MS_PPU_FX1_MS_ATT0 0x40010870 FULL Master attributes 0 PERI_MS_PPU_FX1_MS_ATT1 0x40010874 FULL Master attributes 1 PERI_MS_PPU_FX1_MS_ATT2 0x40010878 FULL Master attributes 2 PERI_MS...

Page 1160: ...tributes 0 PERI_MS_PPU_FX5_MS_ATT1 0x40010974 FULL Master attributes 1 PERI_MS_PPU_FX5_MS_ATT2 0x40010978 FULL Master attributes 2 PERI_MS_PPU_FX5_MS_ATT3 0x4001097C FULL Master attributes 3 21 23 PPU...

Page 1161: ...Slave attributes 2 PERI_MS_PPU_FX9_SL_ATT3 0x40010A5C FULL Slave attributes 3 PERI_MS_PPU_FX9_MS_ADDR 0x40010A60 FULL Master region base address PERI_MS_PPU_FX9_MS_SIZE 0x40010A64 FULL Master region s...

Page 1162: ..._ADDR 0x40010B20 READ Master region base address PERI_MS_PPU_FX12_MS_SIZE 0x40010B24 READ Master region size PERI_MS_PPU_FX12_MS_ATT0 0x40010B30 READ Master attributes 0 PERI_MS_PPU_FX12_MS_ATT1 0x400...

Page 1163: ...40010BFC PRIVILEGE WRITE Master attributes 3 21 33 PPU_FX 16 Register Name Address Permission Description PERI_MS_PPU_FX16_SL_ADDR 0x40010C00 FULL Slave region base address PERI_MS_PPU_FX16_SL_SIZE 0x...

Page 1164: ...ributes 0 PERI_MS_PPU_FX19_MS_ATT1 0x40010CF4 FULL Master attributes 1 PERI_MS_PPU_FX19_MS_ATT2 0x40010CF8 FULL Master attributes 2 PERI_MS_PPU_FX19_MS_ATT3 0x40010CFC FULL Master attributes 3 21 37 P...

Page 1165: ..._SIZE 0x40010DE4 FULL Master region size PERI_MS_PPU_FX23_MS_ATT0 0x40010DF0 FULL Master attributes 0 PERI_MS_PPU_FX23_MS_ATT1 0x40010DF4 FULL Master attributes 1 PERI_MS_PPU_FX23_MS_ATT2 0x40010DF8 F...

Page 1166: ...WRITE Master region base address PERI_MS_PPU_FX26_MS_SIZE 0x40010EA4 PRIVILEGE WRITE Master region size PERI_MS_PPU_FX26_MS_ATT0 0x40010EB0 PRIVILEGE WRITE Master attributes 0 PERI_MS_PPU_FX26_MS_ATT1...

Page 1167: ...L Master region size PERI_MS_PPU_FX29_MS_ATT0 0x40010F70 FULL Master attributes 0 PERI_MS_PPU_FX29_MS_ATT1 0x40010F74 FULL Master attributes 1 PERI_MS_PPU_FX29_MS_ATT2 0x40010F78 FULL Master attribute...

Page 1168: ...gion size PERI_MS_PPU_FX33_MS_ATT0 0x40011070 FULL Master attributes 0 PERI_MS_PPU_FX33_MS_ATT1 0x40011074 FULL Master attributes 1 PERI_MS_PPU_FX33_MS_ATT2 0x40011078 FULL Master attributes 2 PERI_MS...

Page 1169: ...ributes 0 PERI_MS_PPU_FX37_MS_ATT1 0x40011174 FULL Master attributes 1 PERI_MS_PPU_FX37_MS_ATT2 0x40011178 FULL Master attributes 2 PERI_MS_PPU_FX37_MS_ATT3 0x4001117C FULL Master attributes 3 21 55 P...

Page 1170: ...ributes 1 PERI_MS_PPU_FX41_MS_ATT2 0x40011278 FULL Master attributes 2 PERI_MS_PPU_FX41_MS_ATT3 0x4001127C FULL Master attributes 3 21 59 PPU_FX 42 Register Name Address Permission Description PERI_MS...

Page 1171: ...ributes 2 PERI_MS_PPU_FX45_MS_ATT3 0x4001137C FULL Master attributes 3 21 63 PPU_FX 46 Register Name Address Permission Description PERI_MS_PPU_FX46_SL_ADDR 0x40011380 FULL Slave region base address P...

Page 1172: ...utes 3 21 67 PPU_FX 50 Register Name Address Permission Description PERI_MS_PPU_FX50_SL_ADDR 0x40011480 FULL Slave region base address PERI_MS_PPU_FX50_SL_SIZE 0x40011484 FULL Slave region size PERI_M...

Page 1173: ...tion PERI_MS_PPU_FX54_SL_ADDR 0x40011580 READ Slave region base address PERI_MS_PPU_FX54_SL_SIZE 0x40011584 READ Slave region size PERI_MS_PPU_FX54_SL_ATT0 0x40011590 READ Slave attributes 0 PERI_MS_P...

Page 1174: ...ase address PERI_MS_PPU_FX58_SL_SIZE 0x40011684 FULL Slave region size PERI_MS_PPU_FX58_SL_ATT0 0x40011690 FULL Slave attributes 0 PERI_MS_PPU_FX58_SL_ATT1 0x40011694 FULL Slave attributes 1 PERI_MS_P...

Page 1175: ...egion size PERI_MS_PPU_FX62_SL_ATT0 0x40011790 FULL Slave attributes 0 PERI_MS_PPU_FX62_SL_ATT1 0x40011794 FULL Slave attributes 1 PERI_MS_PPU_FX62_SL_ATT2 0x40011798 FULL Slave attributes 2 PERI_MS_P...

Page 1176: ...tributes 0 PERI_MS_PPU_FX66_SL_ATT1 0x40011894 FULL Slave attributes 1 PERI_MS_PPU_FX66_SL_ATT2 0x40011898 FULL Slave attributes 2 PERI_MS_PPU_FX66_SL_ATT3 0x4001189C FULL Slave attributes 3 PERI_MS_P...

Page 1177: ...tributes 1 PERI_MS_PPU_FX70_SL_ATT2 0x40011998 FULL Slave attributes 2 PERI_MS_PPU_FX70_SL_ATT3 0x4001199C FULL Slave attributes 3 PERI_MS_PPU_FX70_MS_ADDR 0x400119A0 FULL Master region base address P...

Page 1178: ...utes 2 PERI_MS_PPU_FX74_SL_ATT3 0x40011A9C FULL Slave attributes 3 PERI_MS_PPU_FX74_MS_ADDR 0x40011AA0 FULL Master region base address PERI_MS_PPU_FX74_MS_SIZE 0x40011AA4 FULL Master region size PERI_...

Page 1179: ...3 PERI_MS_PPU_FX78_MS_ADDR 0x40011BA0 FULL Master region base address PERI_MS_PPU_FX78_MS_SIZE 0x40011BA4 FULL Master region size PERI_MS_PPU_FX78_MS_ATT0 0x40011BB0 FULL Master attributes 0 PERI_MS_...

Page 1180: ...e address PERI_MS_PPU_FX82_MS_SIZE 0x40011CA4 FULL Master region size PERI_MS_PPU_FX82_MS_ATT0 0x40011CB0 FULL Master attributes 0 PERI_MS_PPU_FX82_MS_ATT1 0x40011CB4 FULL Master attributes 1 PERI_MS_...

Page 1181: ...gion size PERI_MS_PPU_FX86_MS_ATT0 0x40011DB0 FULL Master attributes 0 PERI_MS_PPU_FX86_MS_ATT1 0x40011DB4 FULL Master attributes 1 PERI_MS_PPU_FX86_MS_ATT2 0x40011DB8 FULL Master attributes 2 PERI_MS...

Page 1182: ...ributes 0 PERI_MS_PPU_FX90_MS_ATT1 0x40011EB4 FULL Master attributes 1 PERI_MS_PPU_FX90_MS_ATT2 0x40011EB8 FULL Master attributes 2 PERI_MS_PPU_FX90_MS_ATT3 0x40011EBC FULL Master attributes 3 21 108...

Page 1183: ...ributes 1 PERI_MS_PPU_FX94_MS_ATT2 0x40011FB8 FULL Master attributes 2 PERI_MS_PPU_FX94_MS_ATT3 0x40011FBC FULL Master attributes 3 21 112 PPU_FX 95 Register Name Address Permission Description PERI_M...

Page 1184: ...2 PERI_MS_PPU_FX98_MS_ATT3 0x400120BC FULL Master attributes 3 21 116 PPU_FX 99 Register Name Address Permission Description PERI_MS_PPU_FX99_SL_ADDR 0x400120C0 FULL Slave region base address PERI_MS_...

Page 1185: ...s 3 21 120 PPU_FX 103 Register Name Address Permission Description PERI_MS_PPU_FX103_SL_ADDR 0x400121C0 FULL Slave region base address PERI_MS_PPU_FX103_SL_SIZE 0x400121C4 FULL Slave region size PERI_...

Page 1186: ...on PERI_MS_PPU_FX107_SL_ADDR 0x400122C0 FULL Slave region base address PERI_MS_PPU_FX107_SL_SIZE 0x400122C4 FULL Slave region size PERI_MS_PPU_FX107_SL_ATT0 0x400122D0 FULL Slave attributes 0 PERI_MS_...

Page 1187: ...se address PERI_MS_PPU_FX111_SL_SIZE 0x400123C4 FULL Slave region size PERI_MS_PPU_FX111_SL_ATT0 0x400123D0 FULL Slave attributes 0 PERI_MS_PPU_FX111_SL_ATT1 0x400123D4 FULL Slave attributes 1 PERI_MS...

Page 1188: ...gion size PERI_MS_PPU_FX115_SL_ATT0 0x400124D0 FULL Slave attributes 0 PERI_MS_PPU_FX115_SL_ATT1 0x400124D4 FULL Slave attributes 1 PERI_MS_PPU_FX115_SL_ATT2 0x400124D8 FULL Slave attributes 2 PERI_MS...

Page 1189: ...ributes 0 PERI_MS_PPU_FX119_SL_ATT1 0x400125D4 FULL Slave attributes 1 PERI_MS_PPU_FX119_SL_ATT2 0x400125D8 FULL Slave attributes 2 PERI_MS_PPU_FX119_SL_ATT3 0x400125DC FULL Slave attributes 3 PERI_MS...

Page 1190: ...ributes 1 PERI_MS_PPU_FX123_SL_ATT2 0x400126D8 FULL Slave attributes 2 PERI_MS_PPU_FX123_SL_ATT3 0x400126DC FULL Slave attributes 3 PERI_MS_PPU_FX123_MS_ADDR 0x400126E0 FULL Master region base address...

Page 1191: ...tes 2 PERI_MS_PPU_FX127_SL_ATT3 0x400127DC FULL Slave attributes 3 PERI_MS_PPU_FX127_MS_ADDR 0x400127E0 FULL Master region base address PERI_MS_PPU_FX127_MS_SIZE 0x400127E4 FULL Master region size PER...

Page 1192: ...3 PERI_MS_PPU_FX131_MS_ADDR 0x400128E0 FULL Master region base address PERI_MS_PPU_FX131_MS_SIZE 0x400128E4 FULL Master region size PERI_MS_PPU_FX131_MS_ATT0 0x400128F0 FULL Master attributes 0 PERI_M...

Page 1193: ...address PERI_MS_PPU_FX135_MS_SIZE 0x400129E4 FULL Master region size PERI_MS_PPU_FX135_MS_ATT0 0x400129F0 FULL Master attributes 0 PERI_MS_PPU_FX135_MS_ATT1 0x400129F4 FULL Master attributes 1 PERI_M...

Page 1194: ...on size PERI_MS_PPU_FX139_MS_ATT0 0x40012AF0 FULL Master attributes 0 PERI_MS_PPU_FX139_MS_ATT1 0x40012AF4 FULL Master attributes 1 PERI_MS_PPU_FX139_MS_ATT2 0x40012AF8 FULL Master attributes 2 PERI_M...

Page 1195: ...butes 0 PERI_MS_PPU_FX143_MS_ATT1 0x40012BF4 FULL Master attributes 1 PERI_MS_PPU_FX143_MS_ATT2 0x40012BF8 FULL Master attributes 2 PERI_MS_PPU_FX143_MS_ATT3 0x40012BFC FULL Master attributes 3 21 161...

Page 1196: ...butes 1 PERI_MS_PPU_FX147_MS_ATT2 0x40012CF8 FULL Master attributes 2 PERI_MS_PPU_FX147_MS_ATT3 0x40012CFC FULL Master attributes 3 21 165 PPU_FX 148 Register Name Address Permission Description PERI_...

Page 1197: ...butes 2 PERI_MS_PPU_FX151_MS_ATT3 0x40012DFC FULL Master attributes 3 21 169 PPU_FX 152 Register Name Address Permission Description PERI_MS_PPU_FX152_SL_ADDR 0x40012E00 FULL Slave region base address...

Page 1198: ...s 3 21 173 PPU_FX 156 Register Name Address Permission Description PERI_MS_PPU_FX156_SL_ADDR 0x40012F00 FULL Slave region base address PERI_MS_PPU_FX156_SL_SIZE 0x40012F04 FULL Slave region size PERI_...

Page 1199: ...on PERI_MS_PPU_FX160_SL_ADDR 0x40013000 FULL Slave region base address PERI_MS_PPU_FX160_SL_SIZE 0x40013004 FULL Slave region size PERI_MS_PPU_FX160_SL_ATT0 0x40013010 FULL Slave attributes 0 PERI_MS_...

Page 1200: ...se address PERI_MS_PPU_FX164_SL_SIZE 0x40013104 FULL Slave region size PERI_MS_PPU_FX164_SL_ATT0 0x40013110 FULL Slave attributes 0 PERI_MS_PPU_FX164_SL_ATT1 0x40013114 FULL Slave attributes 1 PERI_MS...

Page 1201: ...gion size PERI_MS_PPU_FX168_SL_ATT0 0x40013210 FULL Slave attributes 0 PERI_MS_PPU_FX168_SL_ATT1 0x40013214 FULL Slave attributes 1 PERI_MS_PPU_FX168_SL_ATT2 0x40013218 FULL Slave attributes 2 PERI_MS...

Page 1202: ...ributes 0 PERI_MS_PPU_FX172_SL_ATT1 0x40013314 FULL Slave attributes 1 PERI_MS_PPU_FX172_SL_ATT2 0x40013318 FULL Slave attributes 2 PERI_MS_PPU_FX172_SL_ATT3 0x4001331C FULL Slave attributes 3 PERI_MS...

Page 1203: ...ributes 1 PERI_MS_PPU_FX176_SL_ATT2 0x40013418 FULL Slave attributes 2 PERI_MS_PPU_FX176_SL_ATT3 0x4001341C FULL Slave attributes 3 PERI_MS_PPU_FX176_MS_ADDR 0x40013420 FULL Master region base address...

Page 1204: ...tes 2 PERI_MS_PPU_FX180_SL_ATT3 0x4001351C FULL Slave attributes 3 PERI_MS_PPU_FX180_MS_ADDR 0x40013520 FULL Master region base address PERI_MS_PPU_FX180_MS_SIZE 0x40013524 FULL Master region size PER...

Page 1205: ...3 PERI_MS_PPU_FX184_MS_ADDR 0x40013620 FULL Master region base address PERI_MS_PPU_FX184_MS_SIZE 0x40013624 FULL Master region size PERI_MS_PPU_FX184_MS_ATT0 0x40013630 FULL Master attributes 0 PERI_M...

Page 1206: ...address PERI_MS_PPU_FX188_MS_SIZE 0x40013724 FULL Master region size PERI_MS_PPU_FX188_MS_ATT0 0x40013730 FULL Master attributes 0 PERI_MS_PPU_FX188_MS_ATT1 0x40013734 FULL Master attributes 1 PERI_M...

Page 1207: ...on size PERI_MS_PPU_FX192_MS_ATT0 0x40013830 FULL Master attributes 0 PERI_MS_PPU_FX192_MS_ATT1 0x40013834 FULL Master attributes 1 PERI_MS_PPU_FX192_MS_ATT2 0x40013838 FULL Master attributes 2 PERI_M...

Page 1208: ...butes 0 PERI_MS_PPU_FX196_MS_ATT1 0x40013934 FULL Master attributes 1 PERI_MS_PPU_FX196_MS_ATT2 0x40013938 FULL Master attributes 2 PERI_MS_PPU_FX196_MS_ATT3 0x4001393C FULL Master attributes 3 21 214...

Page 1209: ...butes 1 PERI_MS_PPU_FX200_MS_ATT2 0x40013A38 FULL Master attributes 2 PERI_MS_PPU_FX200_MS_ATT3 0x40013A3C FULL Master attributes 3 21 218 PPU_FX 201 Register Name Address Permission Description PERI_...

Page 1210: ...butes 2 PERI_MS_PPU_FX204_MS_ATT3 0x40013B3C FULL Master attributes 3 21 222 PPU_FX 205 Register Name Address Permission Description PERI_MS_PPU_FX205_SL_ADDR 0x40013B40 FULL Slave region base address...

Page 1211: ...s 3 21 226 PPU_FX 209 Register Name Address Permission Description PERI_MS_PPU_FX209_SL_ADDR 0x40013C40 FULL Slave region base address PERI_MS_PPU_FX209_SL_SIZE 0x40013C44 FULL Slave region size PERI_...

Page 1212: ...on PERI_MS_PPU_FX213_SL_ADDR 0x40013D40 READ Slave region base address PERI_MS_PPU_FX213_SL_SIZE 0x40013D44 READ Slave region size PERI_MS_PPU_FX213_SL_ATT0 0x40013D50 READ Slave attributes 0 PERI_MS_...

Page 1213: ...se address PERI_MS_PPU_FX217_SL_SIZE 0x40013E44 FULL Slave region size PERI_MS_PPU_FX217_SL_ATT0 0x40013E50 FULL Slave attributes 0 PERI_MS_PPU_FX217_SL_ATT1 0x40013E54 FULL Slave attributes 1 PERI_MS...

Page 1214: ...gion size PERI_MS_PPU_FX221_SL_ATT0 0x40013F50 FULL Slave attributes 0 PERI_MS_PPU_FX221_SL_ATT1 0x40013F54 FULL Slave attributes 1 PERI_MS_PPU_FX221_SL_ATT2 0x40013F58 FULL Slave attributes 2 PERI_MS...

Page 1215: ...ributes 0 PERI_MS_PPU_FX225_SL_ATT1 0x40014054 FULL Slave attributes 1 PERI_MS_PPU_FX225_SL_ATT2 0x40014058 FULL Slave attributes 2 PERI_MS_PPU_FX225_SL_ATT3 0x4001405C FULL Slave attributes 3 PERI_MS...

Page 1216: ...ributes 1 PERI_MS_PPU_FX229_SL_ATT2 0x40014158 FULL Slave attributes 2 PERI_MS_PPU_FX229_SL_ATT3 0x4001415C FULL Slave attributes 3 PERI_MS_PPU_FX229_MS_ADDR 0x40014160 FULL Master region base address...

Page 1217: ...tes 2 PERI_MS_PPU_FX233_SL_ATT3 0x4001425C FULL Slave attributes 3 PERI_MS_PPU_FX233_MS_ADDR 0x40014260 FULL Master region base address PERI_MS_PPU_FX233_MS_SIZE 0x40014264 FULL Master region size PER...

Page 1218: ...3 PERI_MS_PPU_FX237_MS_ADDR 0x40014360 FULL Master region base address PERI_MS_PPU_FX237_MS_SIZE 0x40014364 FULL Master region size PERI_MS_PPU_FX237_MS_ATT0 0x40014370 FULL Master attributes 0 PERI_M...

Page 1219: ...address PERI_MS_PPU_FX241_MS_SIZE 0x40014464 FULL Master region size PERI_MS_PPU_FX241_MS_ATT0 0x40014470 FULL Master attributes 0 PERI_MS_PPU_FX241_MS_ATT1 0x40014474 FULL Master attributes 1 PERI_M...

Page 1220: ...on size PERI_MS_PPU_FX245_MS_ATT0 0x40014570 FULL Master attributes 0 PERI_MS_PPU_FX245_MS_ATT1 0x40014574 FULL Master attributes 1 PERI_MS_PPU_FX245_MS_ATT2 0x40014578 FULL Master attributes 2 PERI_M...

Page 1221: ...butes 0 PERI_MS_PPU_FX249_MS_ATT1 0x40014674 FULL Master attributes 1 PERI_MS_PPU_FX249_MS_ATT2 0x40014678 FULL Master attributes 2 PERI_MS_PPU_FX249_MS_ATT3 0x4001467C FULL Master attributes 3 21 267...

Page 1222: ...butes 1 PERI_MS_PPU_FX253_MS_ATT2 0x40014778 FULL Master attributes 2 PERI_MS_PPU_FX253_MS_ATT3 0x4001477C FULL Master attributes 3 21 271 PPU_FX 254 Register Name Address Permission Description PERI_...

Page 1223: ...butes 2 PERI_MS_PPU_FX257_MS_ATT3 0x4001487C FULL Master attributes 3 21 275 PPU_FX 258 Register Name Address Permission Description PERI_MS_PPU_FX258_SL_ADDR 0x40014880 FULL Slave region base address...

Page 1224: ...s 3 21 279 PPU_FX 262 Register Name Address Permission Description PERI_MS_PPU_FX262_SL_ADDR 0x40014980 FULL Slave region base address PERI_MS_PPU_FX262_SL_SIZE 0x40014984 FULL Slave region size PERI_...

Page 1225: ...on PERI_MS_PPU_FX266_SL_ADDR 0x40014A80 FULL Slave region base address PERI_MS_PPU_FX266_SL_SIZE 0x40014A84 FULL Slave region size PERI_MS_PPU_FX266_SL_ATT0 0x40014A90 FULL Slave attributes 0 PERI_MS_...

Page 1226: ...se address PERI_MS_PPU_FX270_SL_SIZE 0x40014B84 FULL Slave region size PERI_MS_PPU_FX270_SL_ATT0 0x40014B90 FULL Slave attributes 0 PERI_MS_PPU_FX270_SL_ATT1 0x40014B94 FULL Slave attributes 1 PERI_MS...

Page 1227: ...gion size PERI_MS_PPU_FX274_SL_ATT0 0x40014C90 FULL Slave attributes 0 PERI_MS_PPU_FX274_SL_ATT1 0x40014C94 FULL Slave attributes 1 PERI_MS_PPU_FX274_SL_ATT2 0x40014C98 FULL Slave attributes 2 PERI_MS...

Page 1228: ...ributes 0 PERI_MS_PPU_FX278_SL_ATT1 0x40014D94 FULL Slave attributes 1 PERI_MS_PPU_FX278_SL_ATT2 0x40014D98 FULL Slave attributes 2 PERI_MS_PPU_FX278_SL_ATT3 0x40014D9C FULL Slave attributes 3 PERI_MS...

Page 1229: ...ributes 1 PERI_MS_PPU_FX282_SL_ATT2 0x40014E98 FULL Slave attributes 2 PERI_MS_PPU_FX282_SL_ATT3 0x40014E9C FULL Slave attributes 3 PERI_MS_PPU_FX282_MS_ADDR 0x40014EA0 FULL Master region base address...

Page 1230: ...tes 2 PERI_MS_PPU_FX286_SL_ATT3 0x40014F9C FULL Slave attributes 3 PERI_MS_PPU_FX286_MS_ADDR 0x40014FA0 FULL Master region base address PERI_MS_PPU_FX286_MS_SIZE 0x40014FA4 FULL Master region size PER...

Page 1231: ...3 PERI_MS_PPU_FX290_MS_ADDR 0x400150A0 FULL Master region base address PERI_MS_PPU_FX290_MS_SIZE 0x400150A4 FULL Master region size PERI_MS_PPU_FX290_MS_ATT0 0x400150B0 FULL Master attributes 0 PERI_M...

Page 1232: ...address PERI_MS_PPU_FX294_MS_SIZE 0x400151A4 FULL Master region size PERI_MS_PPU_FX294_MS_ATT0 0x400151B0 FULL Master attributes 0 PERI_MS_PPU_FX294_MS_ATT1 0x400151B4 FULL Master attributes 1 PERI_M...

Page 1233: ...on size PERI_MS_PPU_FX298_MS_ATT0 0x400152B0 FULL Master attributes 0 PERI_MS_PPU_FX298_MS_ATT1 0x400152B4 FULL Master attributes 1 PERI_MS_PPU_FX298_MS_ATT2 0x400152B8 FULL Master attributes 2 PERI_M...

Page 1234: ...butes 0 PERI_MS_PPU_FX302_MS_ATT1 0x400153B4 FULL Master attributes 1 PERI_MS_PPU_FX302_MS_ATT2 0x400153B8 FULL Master attributes 2 PERI_MS_PPU_FX302_MS_ATT3 0x400153BC FULL Master attributes 3 21 320...

Page 1235: ...butes 1 PERI_MS_PPU_FX306_MS_ATT2 0x400154B8 FULL Master attributes 2 PERI_MS_PPU_FX306_MS_ATT3 0x400154BC FULL Master attributes 3 21 324 PPU_FX 307 Register Name Address Permission Description PERI_...

Page 1236: ...butes 2 PERI_MS_PPU_FX310_MS_ATT3 0x400155BC FULL Master attributes 3 21 328 PPU_FX 311 Register Name Address Permission Description PERI_MS_PPU_FX311_SL_ADDR 0x400155C0 FULL Slave region base address...

Page 1237: ...s 3 21 332 PPU_FX 315 Register Name Address Permission Description PERI_MS_PPU_FX315_SL_ADDR 0x400156C0 FULL Slave region base address PERI_MS_PPU_FX315_SL_SIZE 0x400156C4 FULL Slave region size PERI_...

Page 1238: ...on PERI_MS_PPU_FX319_SL_ADDR 0x400157C0 FULL Slave region base address PERI_MS_PPU_FX319_SL_SIZE 0x400157C4 FULL Slave region size PERI_MS_PPU_FX319_SL_ATT0 0x400157D0 FULL Slave attributes 0 PERI_MS_...

Page 1239: ...se address PERI_MS_PPU_FX323_SL_SIZE 0x400158C4 FULL Slave region size PERI_MS_PPU_FX323_SL_ATT0 0x400158D0 FULL Slave attributes 0 PERI_MS_PPU_FX323_SL_ATT1 0x400158D4 FULL Slave attributes 1 PERI_MS...

Page 1240: ...gion size PERI_MS_PPU_FX327_SL_ATT0 0x400159D0 FULL Slave attributes 0 PERI_MS_PPU_FX327_SL_ATT1 0x400159D4 FULL Slave attributes 1 PERI_MS_PPU_FX327_SL_ATT2 0x400159D8 FULL Slave attributes 2 PERI_MS...

Page 1241: ...ributes 0 PERI_MS_PPU_FX331_SL_ATT1 0x40015AD4 FULL Slave attributes 1 PERI_MS_PPU_FX331_SL_ATT2 0x40015AD8 FULL Slave attributes 2 PERI_MS_PPU_FX331_SL_ATT3 0x40015ADC FULL Slave attributes 3 PERI_MS...

Page 1242: ...ributes 1 PERI_MS_PPU_FX335_SL_ATT2 0x40015BD8 FULL Slave attributes 2 PERI_MS_PPU_FX335_SL_ATT3 0x40015BDC FULL Slave attributes 3 PERI_MS_PPU_FX335_MS_ADDR 0x40015BE0 FULL Master region base address...

Page 1243: ...tes 2 PERI_MS_PPU_FX339_SL_ATT3 0x40015CDC FULL Slave attributes 3 PERI_MS_PPU_FX339_MS_ADDR 0x40015CE0 FULL Master region base address PERI_MS_PPU_FX339_MS_SIZE 0x40015CE4 FULL Master region size PER...

Page 1244: ...3 PERI_MS_PPU_FX343_MS_ADDR 0x40015DE0 FULL Master region base address PERI_MS_PPU_FX343_MS_SIZE 0x40015DE4 FULL Master region size PERI_MS_PPU_FX343_MS_ATT0 0x40015DF0 FULL Master attributes 0 PERI_M...

Page 1245: ...address PERI_MS_PPU_FX347_MS_SIZE 0x40015EE4 FULL Master region size PERI_MS_PPU_FX347_MS_ATT0 0x40015EF0 FULL Master attributes 0 PERI_MS_PPU_FX347_MS_ATT1 0x40015EF4 FULL Master attributes 1 PERI_M...

Page 1246: ...on size PERI_MS_PPU_FX351_MS_ATT0 0x40015FF0 FULL Master attributes 0 PERI_MS_PPU_FX351_MS_ATT1 0x40015FF4 FULL Master attributes 1 PERI_MS_PPU_FX351_MS_ATT2 0x40015FF8 FULL Master attributes 2 PERI_M...

Page 1247: ...butes 0 PERI_MS_PPU_FX355_MS_ATT1 0x400160F4 FULL Master attributes 1 PERI_MS_PPU_FX355_MS_ATT2 0x400160F8 FULL Master attributes 2 PERI_MS_PPU_FX355_MS_ATT3 0x400160FC FULL Master attributes 3 21 373...

Page 1248: ...butes 1 PERI_MS_PPU_FX359_MS_ATT2 0x400161F8 FULL Master attributes 2 PERI_MS_PPU_FX359_MS_ATT3 0x400161FC FULL Master attributes 3 21 377 PPU_FX 360 Register Name Address Permission Description PERI_...

Page 1249: ...butes 2 PERI_MS_PPU_FX363_MS_ATT3 0x400162FC FULL Master attributes 3 21 381 PPU_FX 364 Register Name Address Permission Description PERI_MS_PPU_FX364_SL_ADDR 0x40016300 FULL Slave region base address...

Page 1250: ...s 3 21 385 PPU_FX 368 Register Name Address Permission Description PERI_MS_PPU_FX368_SL_ADDR 0x40016400 FULL Slave region base address PERI_MS_PPU_FX368_SL_SIZE 0x40016404 FULL Slave region size PERI_...

Page 1251: ...on PERI_MS_PPU_FX372_SL_ADDR 0x40016500 FULL Slave region base address PERI_MS_PPU_FX372_SL_SIZE 0x40016504 FULL Slave region size PERI_MS_PPU_FX372_SL_ATT0 0x40016510 FULL Slave attributes 0 PERI_MS_...

Page 1252: ...se address PERI_MS_PPU_FX376_SL_SIZE 0x40016604 FULL Slave region size PERI_MS_PPU_FX376_SL_ATT0 0x40016610 FULL Slave attributes 0 PERI_MS_PPU_FX376_SL_ATT1 0x40016614 FULL Slave attributes 1 PERI_MS...

Page 1253: ...gion size PERI_MS_PPU_FX380_SL_ATT0 0x40016710 FULL Slave attributes 0 PERI_MS_PPU_FX380_SL_ATT1 0x40016714 FULL Slave attributes 1 PERI_MS_PPU_FX380_SL_ATT2 0x40016718 FULL Slave attributes 2 PERI_MS...

Page 1254: ...ributes 0 PERI_MS_PPU_FX384_SL_ATT1 0x40016814 FULL Slave attributes 1 PERI_MS_PPU_FX384_SL_ATT2 0x40016818 FULL Slave attributes 2 PERI_MS_PPU_FX384_SL_ATT3 0x4001681C FULL Slave attributes 3 PERI_MS...

Page 1255: ...ributes 1 PERI_MS_PPU_FX388_SL_ATT2 0x40016918 FULL Slave attributes 2 PERI_MS_PPU_FX388_SL_ATT3 0x4001691C FULL Slave attributes 3 PERI_MS_PPU_FX388_MS_ADDR 0x40016920 FULL Master region base address...

Page 1256: ...tes 2 PERI_MS_PPU_FX392_SL_ATT3 0x40016A1C FULL Slave attributes 3 PERI_MS_PPU_FX392_MS_ADDR 0x40016A20 FULL Master region base address PERI_MS_PPU_FX392_MS_SIZE 0x40016A24 FULL Master region size PER...

Page 1257: ...3 PERI_MS_PPU_FX396_MS_ADDR 0x40016B20 FULL Master region base address PERI_MS_PPU_FX396_MS_SIZE 0x40016B24 FULL Master region size PERI_MS_PPU_FX396_MS_ATT0 0x40016B30 FULL Master attributes 0 PERI_M...

Page 1258: ...address PERI_MS_PPU_FX400_MS_SIZE 0x40016C24 FULL Master region size PERI_MS_PPU_FX400_MS_ATT0 0x40016C30 FULL Master attributes 0 PERI_MS_PPU_FX400_MS_ATT1 0x40016C34 FULL Master attributes 1 PERI_M...

Page 1259: ...on size PERI_MS_PPU_FX404_MS_ATT0 0x40016D30 FULL Master attributes 0 PERI_MS_PPU_FX404_MS_ATT1 0x40016D34 FULL Master attributes 1 PERI_MS_PPU_FX404_MS_ATT2 0x40016D38 FULL Master attributes 2 PERI_M...

Page 1260: ...butes 0 PERI_MS_PPU_FX408_MS_ATT1 0x40016E34 FULL Master attributes 1 PERI_MS_PPU_FX408_MS_ATT2 0x40016E38 FULL Master attributes 2 PERI_MS_PPU_FX408_MS_ATT3 0x40016E3C FULL Master attributes 3 21 426...

Page 1261: ...butes 1 PERI_MS_PPU_FX412_MS_ATT2 0x40016F38 FULL Master attributes 2 PERI_MS_PPU_FX412_MS_ATT3 0x40016F3C FULL Master attributes 3 21 430 PPU_FX 413 Register Name Address Permission Description PERI_...

Page 1262: ...butes 2 PERI_MS_PPU_FX416_MS_ATT3 0x4001703C FULL Master attributes 3 21 434 PPU_FX 417 Register Name Address Permission Description PERI_MS_PPU_FX417_SL_ADDR 0x40017040 FULL Slave region base address...

Page 1263: ...s 3 21 438 PPU_FX 421 Register Name Address Permission Description PERI_MS_PPU_FX421_SL_ADDR 0x40017140 FULL Slave region base address PERI_MS_PPU_FX421_SL_SIZE 0x40017144 FULL Slave region size PERI_...

Page 1264: ...on PERI_MS_PPU_FX425_SL_ADDR 0x40017240 FULL Slave region base address PERI_MS_PPU_FX425_SL_SIZE 0x40017244 FULL Slave region size PERI_MS_PPU_FX425_SL_ATT0 0x40017250 FULL Slave attributes 0 PERI_MS_...

Page 1265: ...se address PERI_MS_PPU_FX429_SL_SIZE 0x40017344 FULL Slave region size PERI_MS_PPU_FX429_SL_ATT0 0x40017350 FULL Slave attributes 0 PERI_MS_PPU_FX429_SL_ATT1 0x40017354 FULL Slave attributes 1 PERI_MS...

Page 1266: ...gion size PERI_MS_PPU_FX433_SL_ATT0 0x40017450 FULL Slave attributes 0 PERI_MS_PPU_FX433_SL_ATT1 0x40017454 FULL Slave attributes 1 PERI_MS_PPU_FX433_SL_ATT2 0x40017458 FULL Slave attributes 2 PERI_MS...

Page 1267: ...ributes 0 PERI_MS_PPU_FX437_SL_ATT1 0x40017554 FULL Slave attributes 1 PERI_MS_PPU_FX437_SL_ATT2 0x40017558 FULL Slave attributes 2 PERI_MS_PPU_FX437_SL_ATT3 0x4001755C FULL Slave attributes 3 PERI_MS...

Page 1268: ...ributes 1 PERI_MS_PPU_FX441_SL_ATT2 0x40017658 FULL Slave attributes 2 PERI_MS_PPU_FX441_SL_ATT3 0x4001765C FULL Slave attributes 3 PERI_MS_PPU_FX441_MS_ADDR 0x40017660 FULL Master region base address...

Page 1269: ...tes 2 PERI_MS_PPU_FX445_SL_ATT3 0x4001775C FULL Slave attributes 3 PERI_MS_PPU_FX445_MS_ADDR 0x40017760 FULL Master region base address PERI_MS_PPU_FX445_MS_SIZE 0x40017764 FULL Master region size PER...

Page 1270: ...3 PERI_MS_PPU_FX449_MS_ADDR 0x40017860 FULL Master region base address PERI_MS_PPU_FX449_MS_SIZE 0x40017864 FULL Master region size PERI_MS_PPU_FX449_MS_ATT0 0x40017870 FULL Master attributes 0 PERI_M...

Page 1271: ...address PERI_MS_PPU_FX453_MS_SIZE 0x40017964 FULL Master region size PERI_MS_PPU_FX453_MS_ATT0 0x40017970 FULL Master attributes 0 PERI_MS_PPU_FX453_MS_ATT1 0x40017974 FULL Master attributes 1 PERI_M...

Page 1272: ...on size PERI_MS_PPU_FX457_MS_ATT0 0x40017A70 FULL Master attributes 0 PERI_MS_PPU_FX457_MS_ATT1 0x40017A74 FULL Master attributes 1 PERI_MS_PPU_FX457_MS_ATT2 0x40017A78 FULL Master attributes 2 PERI_M...

Page 1273: ...butes 0 PERI_MS_PPU_FX461_MS_ATT1 0x40017B74 FULL Master attributes 1 PERI_MS_PPU_FX461_MS_ATT2 0x40017B78 FULL Master attributes 2 PERI_MS_PPU_FX461_MS_ATT3 0x40017B7C FULL Master attributes 3 21 479...

Page 1274: ...butes 1 PERI_MS_PPU_FX465_MS_ATT2 0x40017C78 FULL Master attributes 2 PERI_MS_PPU_FX465_MS_ATT3 0x40017C7C FULL Master attributes 3 21 483 PPU_FX 466 Register Name Address Permission Description PERI_...

Page 1275: ...butes 2 PERI_MS_PPU_FX469_MS_ATT3 0x40017D7C FULL Master attributes 3 21 487 PPU_FX 470 Register Name Address Permission Description PERI_MS_PPU_FX470_SL_ADDR 0x40017D80 FULL Slave region base address...

Page 1276: ...s 3 21 491 PPU_FX 474 Register Name Address Permission Description PERI_MS_PPU_FX474_SL_ADDR 0x40017E80 FULL Slave region base address PERI_MS_PPU_FX474_SL_SIZE 0x40017E84 FULL Slave region size PERI_...

Page 1277: ...on PERI_MS_PPU_FX478_SL_ADDR 0x40017F80 FULL Slave region base address PERI_MS_PPU_FX478_SL_SIZE 0x40017F84 FULL Slave region size PERI_MS_PPU_FX478_SL_ATT0 0x40017F90 FULL Slave attributes 0 PERI_MS_...

Page 1278: ...se address PERI_MS_PPU_FX482_SL_SIZE 0x40018084 FULL Slave region size PERI_MS_PPU_FX482_SL_ATT0 0x40018090 FULL Slave attributes 0 PERI_MS_PPU_FX482_SL_ATT1 0x40018094 FULL Slave attributes 1 PERI_MS...

Page 1279: ...s 3 PERI_MS_PPU_FX485_MS_ADDR 0x40018160 FULL Master region base address PERI_MS_PPU_FX485_MS_SIZE 0x40018164 FULL Master region size PERI_MS_PPU_FX485_MS_ATT0 0x40018170 FULL Master attributes 0 PERI...

Page 1280: ...the boot process with protection context 0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 1 0 Bits 15 14 13 12 11 10 9 8 Name ADDR30 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR30 23 16 Bit...

Page 1281: ...6 25 24 Name VALID 31 31 None 30 29 REGION_SIZE 28 24 Bit fields Bits Name SW HW Default or Enum Description 24 28 REGION_SIZE RW R Undefined This field specifies the size of the slave region 0 Undefi...

Page 1282: ...me SW HW Default or Enum Description 31 VALID RW R 0 Slave region enable 0 Disabled A disabled region will never result in a match on the transfer address 1 Enabled 1282 2022 04 18 TRAVEO T2G Automoti...

Page 1283: ...as 0 Default 0x1F1F1F1F Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 PC0_NS 4 4 PC0_PW 3 3 PC0_PR 2 2 PC0_UW 1 1 PC0_UR 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 13 PC1_NS 12 12 PC1_PW 11 11 P...

Page 1284: ...NS RW R 1 Protection context 1 non secure 16 PC2_UR RW R 1 Protection context 2 user read enable 17 PC2_UW RW R 1 Protection context 2 user write enable 18 PC2_PR RW R 1 Protection context 2 privilege...

Page 1285: ...nable 3 PC4_PW RW R 1 Protection context 4 privileged write enable 4 PC4_NS RW R 1 Protection context 4 non secure 8 PC5_UR RW R 1 Protection context 5 user read enable 9 PC5_UW RW R 1 Protection cont...

Page 1286: ...3 PC8_PW RW R 1 Protection context 8 privileged write enable 4 PC8_NS RW R 1 Protection context 8 non secure 8 PC9_UR RW R 1 Protection context 9 user read enable 9 PC9_UW RW R 1 Protection context 9...

Page 1287: ...e 3 PC12_PW RW R 1 Protection context 12 privileged write enable 4 PC12_NS RW R 1 Protection context 12 non secure 8 PC13_UR RW R 1 Protection context 13 user read enable 9 PC13_UW RW R 1 Protection c...

Page 1288: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 5 0 Bits 15 14 13 12 11 10 9 8 Name ADDR26 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR26 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR26 31 24 Bi...

Page 1289: ...8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name VALID 31 31 None 30 29 REGION_SIZE 28 24 Bit fields Bits Name SW HW Default or Enum Description 24 28 REGION_SIZE R R...

Page 1290: ..._UR 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 PC0_UR R R 1 Protection context 0 user read enable 0 Disabled user read accesses are NOT allowed 1 Enabled user read accesses are all...

Page 1291: ...d read enable 19 PC2_PW RW R 1 Protection context 2 privileged write enable 20 PC2_NS RW R 1 Protection context 2 non secure 24 PC3_UR R R 1 Protection context 3 user read enable 25 PC3_UW RW R 1 Prot...

Page 1292: ...d enable 3 PC4_PW RW R 1 Protection context 4 privileged write enable 4 PC4_NS RW R 1 Protection context 4 non secure 8 PC5_UR R R 1 Protection context 5 user read enable 9 PC5_UW RW R 1 Protection co...

Page 1293: ...ble 3 PC8_PW RW R 1 Protection context 8 privileged write enable 4 PC8_NS RW R 1 Protection context 8 non secure 8 PC9_UR R R 1 Protection context 9 user read enable 9 PC9_UW RW R 1 Protection context...

Page 1294: ...able 3 PC12_PW RW R 1 Protection context 12 privileged write enable 4 PC12_NS RW R 1 Protection context 12 non secure 8 PC13_UR R R 1 Protection context 13 user read enable 9 PC13_UW RW R 1 Protection...

Page 1295: ...8 17 16 Name ADDR30 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR30 31 24 Bit fields Bits Name SW HW Default or Enum Description 2 31 ADDR30 R R ADDR0 _DEF This field specifies the base address of the...

Page 1296: ...n 24 28 REGION_SIZE R R REGION_SI ZE0_DEF This field specifies the size of the slave region 0 Undefined 1 4 B region this is the smallest region size 2 8 B region 3 16 B region 4 32 B region 5 64 B re...

Page 1297: ...me SW HW Default or Enum Description 31 VALID R R 1 Slave region enable 0 Disabled A disabled region will never result in a match on the transfer address 1 Enabled 1297 2022 04 18 TRAVEO T2G Automotiv...

Page 1298: ...as 0 Default 0x1F1F1F1F Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 5 PC0_NS 4 4 PC0_PW 3 3 PC0_PR 2 2 PC0_UW 1 1 PC0_UR 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 13 PC1_NS 12 12 PC1_PW 11 11 P...

Page 1299: ...NS RW R 1 Protection context 1 non secure 16 PC2_UR RW R 1 Protection context 2 user read enable 17 PC2_UW RW R 1 Protection context 2 user write enable 18 PC2_PR RW R 1 Protection context 2 privilege...

Page 1300: ...nable 3 PC4_PW RW R 1 Protection context 4 privileged write enable 4 PC4_NS RW R 1 Protection context 4 non secure 8 PC5_UR RW R 1 Protection context 5 user read enable 9 PC5_UW RW R 1 Protection cont...

Page 1301: ...3 PC8_PW RW R 1 Protection context 8 privileged write enable 4 PC8_NS RW R 1 Protection context 8 non secure 8 PC9_UR RW R 1 Protection context 9 user read enable 9 PC9_UW RW R 1 Protection context 9...

Page 1302: ...e 3 PC12_PW RW R 1 Protection context 12 privileged write enable 4 PC12_NS RW R 1 Protection context 12 non secure 8 PC13_UR RW R 1 Protection context 13 user read enable 9 PC13_UW RW R 1 Protection c...

Page 1303: ...ault 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 5 0 Bits 15 14 13 12 11 10 9 8 Name ADDR26 15 8 Bits 23 22 21 20 19 18 17 16 Name ADDR26 23 16 Bits 31 30 29 28 27 26 25 24 Name ADDR26 31 24 Bi...

Page 1304: ...8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name VALID 31 31 None 30 29 REGION_SIZE 28 24 Bit fields Bits Name SW HW Default or Enum Description 24 28 REGION_SIZE R R...

Page 1305: ..._UR 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 PC0_UR R R 1 Protection context 0 user read enable 0 Disabled user read accesses are NOT allowed 1 Enabled user read accesses are all...

Page 1306: ...d read enable 19 PC2_PW RW R 1 Protection context 2 privileged write enable 20 PC2_NS RW R 1 Protection context 2 non secure 24 PC3_UR R R 1 Protection context 3 user read enable 25 PC3_UW RW R 1 Prot...

Page 1307: ...d enable 3 PC4_PW RW R 1 Protection context 4 privileged write enable 4 PC4_NS RW R 1 Protection context 4 non secure 8 PC5_UR R R 1 Protection context 5 user read enable 9 PC5_UW RW R 1 Protection co...

Page 1308: ...ble 3 PC8_PW RW R 1 Protection context 8 privileged write enable 4 PC8_NS RW R 1 Protection context 8 non secure 8 PC9_UR R R 1 Protection context 9 user read enable 9 PC9_UW RW R 1 Protection context...

Page 1309: ...able 3 PC12_PW RW R 1 Protection context 12 privileged write enable 4 PC12_NS RW R 1 Protection context 12 non secure 8 PC13_UR R R 1 Protection context 13 user read enable 9 PC13_UW RW R 1 Protection...

Page 1310: ...MPU_STRUCT1_ATT0 0x40232044 FULL SMPU region attributes 0 slave structure PROT_SMPU_SMPU_STRUCT1_ADDR1 0x40232060 FULL SMPU region address 1 master structure PROT_SMPU_SMPU_STRUCT1_ATT1 0x40232064 FUL...

Page 1311: ...region attributes 0 slave structure PROT_SMPU_SMPU_STRUCT9_ADDR1 0x40232260 FULL SMPU region address 1 master structure PROT_SMPU_SMPU_STRUCT9_ATT1 0x40232264 FULL SMPU region attributes 1 master stru...

Page 1312: ..._READ_MIR12 0x40234034 FULL Master control read mirror PROT_MPU0_MS_CTL_READ_MIR13 0x40234038 FULL Master control read mirror PROT_MPU0_MS_CTL_READ_MIR14 0x4023403C FULL Master control read mirror PRO...

Page 1313: ...U0_MS_CTL_READ_MIR70 0x4023411C FULL Master control read mirror PROT_MPU0_MS_CTL_READ_MIR71 0x40234120 FULL Master control read mirror PROT_MPU0_MS_CTL_READ_MIR72 0x40234124 FULL Master control read m...

Page 1314: ...aster control read mirror PROT_MPU14_MS_CTL_READ_MIR2 0x4023780C FULL Master control read mirror PROT_MPU14_MS_CTL_READ_MIR3 0x40237810 FULL Master control read mirror PROT_MPU14_MS_CTL_READ_MIR4 0x40...

Page 1315: ...U14_MS_CTL_READ_MIR63 0x40237900 FULL Master control read mirror PROT_MPU14_MS_CTL_READ_MIR64 0x40237904 FULL Master control read mirror PROT_MPU14_MS_CTL_READ_MIR65 0x40237908 FULL Master control rea...

Page 1316: ...D_MIR124 0x402379F4 FULL Master control read mirror PROT_MPU14_MS_CTL_READ_MIR125 0x402379F8 FULL Master control read mirror PROT_MPU14_MS_CTL_READ_MIR126 0x402379FC FULL Master control read mirror 22...

Page 1317: ...U15_MS_CTL_READ_MIR56 0x40237CE4 FULL Master control read mirror PROT_MPU15_MS_CTL_READ_MIR57 0x40237CE8 FULL Master control read mirror PROT_MPU15_MS_CTL_READ_MIR58 0x40237CEC FULL Master control rea...

Page 1318: ...IR113 0x40237DC8 FULL Master control read mirror PROT_MPU15_MS_CTL_READ_MIR114 0x40237DCC FULL Master control read mirror PROT_MPU15_MS_CTL_READ_MIR115 0x40237DD0 FULL Master control read mirror PROT_...

Page 1319: ...6 Register Name Address Permission Description PROT_MPU15_MPU_STRUCT6_ADDR 0x40237EC0 FULL MPU region address PROT_MPU15_MPU_STRUCT6_ATT 0x40237EC4 FULL MPU region attrributes 22 4 8 MPU_STRUCT 7 Regi...

Page 1320: ..._CTL Master 15 test controller uses SMPU MS15_CTL Default 0x303 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 2 NS 1 1 P 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19...

Page 1321: ...ion is not applied and PC 3 0 can be changed 17 31 PC_MASK_15_TO_1 RW R 0 Protection context mask for protection contexts 15 down to 1 Bit PC_MASK_15_TO_1 i indicates if the MPU MS_CTL PC 3 0 protecti...

Page 1322: ...14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19 18 17 16 Name PC_MASK _0 16 16 Bits 31 30 29 28 27 26 25 24 Name PC_MASK_15_TO_1 31 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 1323: ...14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19 18 17 16 Name PC_MASK _0 16 16 Bits 31 30 29 28 27 26 25 24 Name PC_MASK_15_TO_1 31 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 1324: ...14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19 18 17 16 Name PC_MASK _0 16 16 Bits 31 30 29 28 27 26 25 24 Name PC_MASK_15_TO_1 31 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 1325: ...14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19 18 17 16 Name PC_MASK _0 16 16 Bits 31 30 29 28 27 26 25 24 Name PC_MASK_15_TO_1 31 24 Bit fields Bits Name SW HW Default or Enum Descr...

Page 1326: ...5 14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19 18 17 16 Name PC_MASK _0 16 16 Bits 31 30 29 28 27 26 25 24 Name PC_MASK_15_TO_1 31 24 Bit fields Bits Name SW HW Default or Enum Desc...

Page 1327: ...5 14 13 12 11 10 9 8 Name None 15 10 PRIO 9 8 Bits 23 22 21 20 19 18 17 16 Name PC_MASK _0 16 16 Bits 31 30 29 28 27 26 25 24 Name PC_MASK_15_TO_1 31 24 Bit fields Bits Name SW HW Default or Enum Desc...

Page 1328: ...t 3 subregion 3 disable Bit 4 subregion 4 disable Bit 5 subregion 5 disable Bit 6 subregion 6 disable Bit 7 subregion 7 disable E g a 64 KByte address region ATT0 REGION_SIZE is 15 has eight 8 KByte s...

Page 1329: ...ite accesses are NOT allowed 1 Enabled user write accesses are allowed 2 UX RW R Undefined User execute enable 0 Disabled user execute accesses are NOT allowed 1 Enabled user execute accesses are allo...

Page 1330: ...ion 30 PC_MATCH RW R Undefined This field specifies if the PC field participates in the matching process or the access evaluation process 0 PC field participates in access evaluation 1 PC field partic...

Page 1331: ...e SW HW Default or Enum Description 0 7 SUBREGION_DISABLE R R SUBREGION _DISABLE _DEF1 This field is used to individually disabled the eight equally sized subregions in which a region is partitioned S...

Page 1332: ...bled user read accesses are allowed Note that this register is constant 1 i e user read accesses are ALWAYS allowed 1 UW RW R Undefined User write enable 0 Disabled user write accesses are NOT allowed...

Page 1333: ...28 REGION_SIZE R R 7 This field specifies the region size 7 256 B region 8 32 B subregions Note this field is read only 30 PC_MATCH RW R Undefined This field specifies if the PC field participates in...

Page 1334: ...MPU MS_CTL register is special the PC field is modifiable by BOTH HW and SW for all other masters the MPU MS_CTL PC field is modifiable by SW ONLY For CM0 PC field HW modifications the following hold...

Page 1335: ...19 PC_SAVED RW RW 0 Saved protection context Modifications to this field are constrained by the associated SMPU MS_CTL PC_MASK_0 and MS_CTL PC_MASK_15_TO_1 fields Note this field is ONLY used by the...

Page 1336: ...6 5 4 3 2 1 0 Name None 7 4 PC 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 20 PC_SAVED 19 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Na...

Page 1337: ...3 disable Bit 4 subregion 4 disable Bit 5 subregion 5 disable Bit 6 subregion 6 disable Bit 7 subregion 7 disable E g a 64 KByte address region REGION_SIZE is 15 has eight 8 KByte subregions The acces...

Page 1338: ...ser write enable 0 Disabled user write accesses are NOT allowed 1 Enabled user write accesses are allowed 2 UX RW R Undefined User execute enable 0 Disabled user execute accesses are NOT allowed 1 Ena...

Page 1339: ...B region 18 512 KB region 19 1 MB region 20 2 MB region 21 4 MB region 22 8 MB region 23 16 MB region 24 32 MB region 25 64 MB region 26 128 MB region 27 256 MB region 28 512 MB region 39 1 GB region...

Page 1340: ...write SCB0_RX_CTRL 0x40600300 FULL Receiver control SCB0_RX_FIFO_CTRL 0x40600304 FULL Receiver FIFO control SCB0_RX_FIFO_STATUS 0x40600308 FULL Receiver FIFO status SCB0_RX_MATCH 0x40600310 FULL Slave...

Page 1341: ...A54 0x406004D8 FULL Memory buffer SCB0_EZ_DATA55 0x406004DC FULL Memory buffer SCB0_EZ_DATA56 0x406004E0 FULL Memory buffer SCB0_EZ_DATA57 0x406004E4 FULL Memory buffer SCB0_EZ_DATA58 0x406004E8 FULL...

Page 1342: ...6005D4 FULL Memory buffer SCB0_EZ_DATA118 0x406005D8 FULL Memory buffer SCB0_EZ_DATA119 0x406005DC FULL Memory buffer SCB0_EZ_DATA120 0x406005E0 FULL Memory buffer SCB0_EZ_DATA121 0x406005E4 FULL Memo...

Page 1343: ...0 0x406006D0 FULL Memory buffer SCB0_EZ_DATA181 0x406006D4 FULL Memory buffer SCB0_EZ_DATA182 0x406006D8 FULL Memory buffer SCB0_EZ_DATA183 0x406006DC FULL Memory buffer SCB0_EZ_DATA184 0x406006E0 FUL...

Page 1344: ...emory buffer SCB0_EZ_DATA248 0x406007E0 FULL Memory buffer SCB0_EZ_DATA249 0x406007E4 FULL Memory buffer SCB0_EZ_DATA250 0x406007E8 FULL Memory buffer SCB0_EZ_DATA251 0x406007EC FULL Memory buffer SCB...

Page 1345: ...FO control SCB1_TX_FIFO_STATUS 0x40610208 FULL Transmitter FIFO status SCB1_TX_FIFO_WR 0x40610240 FULL Transmitter FIFO write SCB1_RX_CTRL 0x40610300 FULL Receiver control SCB1_RX_FIFO_CTRL 0x40610304...

Page 1346: ...A52 0x406104D0 FULL Memory buffer SCB1_EZ_DATA53 0x406104D4 FULL Memory buffer SCB1_EZ_DATA54 0x406104D8 FULL Memory buffer SCB1_EZ_DATA55 0x406104DC FULL Memory buffer SCB1_EZ_DATA56 0x406104E0 FULL...

Page 1347: ...105CC FULL Memory buffer SCB1_EZ_DATA116 0x406105D0 FULL Memory buffer SCB1_EZ_DATA117 0x406105D4 FULL Memory buffer SCB1_EZ_DATA118 0x406105D8 FULL Memory buffer SCB1_EZ_DATA119 0x406105DC FULL Memor...

Page 1348: ...8 0x406106C8 FULL Memory buffer SCB1_EZ_DATA179 0x406106CC FULL Memory buffer SCB1_EZ_DATA180 0x406106D0 FULL Memory buffer SCB1_EZ_DATA181 0x406106D4 FULL Memory buffer SCB1_EZ_DATA182 0x406106D8 FUL...

Page 1349: ...emory buffer SCB1_EZ_DATA245 0x406107D4 FULL Memory buffer SCB1_EZ_DATA246 0x406107D8 FULL Memory buffer SCB1_EZ_DATA247 0x406107DC FULL Memory buffer SCB1_EZ_DATA248 0x406107E0 FULL Memory buffer SCB...

Page 1350: ...FO control SCB2_TX_FIFO_STATUS 0x40620208 FULL Transmitter FIFO status SCB2_TX_FIFO_WR 0x40620240 FULL Transmitter FIFO write SCB2_RX_CTRL 0x40620300 FULL Receiver control SCB2_RX_FIFO_CTRL 0x40620304...

Page 1351: ...A52 0x406204D0 FULL Memory buffer SCB2_EZ_DATA53 0x406204D4 FULL Memory buffer SCB2_EZ_DATA54 0x406204D8 FULL Memory buffer SCB2_EZ_DATA55 0x406204DC FULL Memory buffer SCB2_EZ_DATA56 0x406204E0 FULL...

Page 1352: ...205CC FULL Memory buffer SCB2_EZ_DATA116 0x406205D0 FULL Memory buffer SCB2_EZ_DATA117 0x406205D4 FULL Memory buffer SCB2_EZ_DATA118 0x406205D8 FULL Memory buffer SCB2_EZ_DATA119 0x406205DC FULL Memor...

Page 1353: ...8 0x406206C8 FULL Memory buffer SCB2_EZ_DATA179 0x406206CC FULL Memory buffer SCB2_EZ_DATA180 0x406206D0 FULL Memory buffer SCB2_EZ_DATA181 0x406206D4 FULL Memory buffer SCB2_EZ_DATA182 0x406206D8 FUL...

Page 1354: ...emory buffer SCB2_EZ_DATA245 0x406207D4 FULL Memory buffer SCB2_EZ_DATA246 0x406207D8 FULL Memory buffer SCB2_EZ_DATA247 0x406207DC FULL Memory buffer SCB2_EZ_DATA248 0x406207E0 FULL Memory buffer SCB...

Page 1355: ...FO control SCB3_TX_FIFO_STATUS 0x40630208 FULL Transmitter FIFO status SCB3_TX_FIFO_WR 0x40630240 FULL Transmitter FIFO write SCB3_RX_CTRL 0x40630300 FULL Receiver control SCB3_RX_FIFO_CTRL 0x40630304...

Page 1356: ...A52 0x406304D0 FULL Memory buffer SCB3_EZ_DATA53 0x406304D4 FULL Memory buffer SCB3_EZ_DATA54 0x406304D8 FULL Memory buffer SCB3_EZ_DATA55 0x406304DC FULL Memory buffer SCB3_EZ_DATA56 0x406304E0 FULL...

Page 1357: ...305CC FULL Memory buffer SCB3_EZ_DATA116 0x406305D0 FULL Memory buffer SCB3_EZ_DATA117 0x406305D4 FULL Memory buffer SCB3_EZ_DATA118 0x406305D8 FULL Memory buffer SCB3_EZ_DATA119 0x406305DC FULL Memor...

Page 1358: ...8 0x406306C8 FULL Memory buffer SCB3_EZ_DATA179 0x406306CC FULL Memory buffer SCB3_EZ_DATA180 0x406306D0 FULL Memory buffer SCB3_EZ_DATA181 0x406306D4 FULL Memory buffer SCB3_EZ_DATA182 0x406306D8 FUL...

Page 1359: ...emory buffer SCB3_EZ_DATA245 0x406307D4 FULL Memory buffer SCB3_EZ_DATA246 0x406307D8 FULL Memory buffer SCB3_EZ_DATA247 0x406307DC FULL Memory buffer SCB3_EZ_DATA248 0x406307E0 FULL Memory buffer SCB...

Page 1360: ...FO control SCB4_TX_FIFO_STATUS 0x40640208 FULL Transmitter FIFO status SCB4_TX_FIFO_WR 0x40640240 FULL Transmitter FIFO write SCB4_RX_CTRL 0x40640300 FULL Receiver control SCB4_RX_FIFO_CTRL 0x40640304...

Page 1361: ...A52 0x406404D0 FULL Memory buffer SCB4_EZ_DATA53 0x406404D4 FULL Memory buffer SCB4_EZ_DATA54 0x406404D8 FULL Memory buffer SCB4_EZ_DATA55 0x406404DC FULL Memory buffer SCB4_EZ_DATA56 0x406404E0 FULL...

Page 1362: ...405CC FULL Memory buffer SCB4_EZ_DATA116 0x406405D0 FULL Memory buffer SCB4_EZ_DATA117 0x406405D4 FULL Memory buffer SCB4_EZ_DATA118 0x406405D8 FULL Memory buffer SCB4_EZ_DATA119 0x406405DC FULL Memor...

Page 1363: ...8 0x406406C8 FULL Memory buffer SCB4_EZ_DATA179 0x406406CC FULL Memory buffer SCB4_EZ_DATA180 0x406406D0 FULL Memory buffer SCB4_EZ_DATA181 0x406406D4 FULL Memory buffer SCB4_EZ_DATA182 0x406406D8 FUL...

Page 1364: ...emory buffer SCB4_EZ_DATA245 0x406407D4 FULL Memory buffer SCB4_EZ_DATA246 0x406407D8 FULL Memory buffer SCB4_EZ_DATA247 0x406407DC FULL Memory buffer SCB4_EZ_DATA248 0x406407E0 FULL Memory buffer SCB...

Page 1365: ...FO control SCB5_TX_FIFO_STATUS 0x40650208 FULL Transmitter FIFO status SCB5_TX_FIFO_WR 0x40650240 FULL Transmitter FIFO write SCB5_RX_CTRL 0x40650300 FULL Receiver control SCB5_RX_FIFO_CTRL 0x40650304...

Page 1366: ...A52 0x406504D0 FULL Memory buffer SCB5_EZ_DATA53 0x406504D4 FULL Memory buffer SCB5_EZ_DATA54 0x406504D8 FULL Memory buffer SCB5_EZ_DATA55 0x406504DC FULL Memory buffer SCB5_EZ_DATA56 0x406504E0 FULL...

Page 1367: ...505CC FULL Memory buffer SCB5_EZ_DATA116 0x406505D0 FULL Memory buffer SCB5_EZ_DATA117 0x406505D4 FULL Memory buffer SCB5_EZ_DATA118 0x406505D8 FULL Memory buffer SCB5_EZ_DATA119 0x406505DC FULL Memor...

Page 1368: ...8 0x406506C8 FULL Memory buffer SCB5_EZ_DATA179 0x406506CC FULL Memory buffer SCB5_EZ_DATA180 0x406506D0 FULL Memory buffer SCB5_EZ_DATA181 0x406506D4 FULL Memory buffer SCB5_EZ_DATA182 0x406506D8 FUL...

Page 1369: ...emory buffer SCB5_EZ_DATA245 0x406507D4 FULL Memory buffer SCB5_EZ_DATA246 0x406507D8 FULL Memory buffer SCB5_EZ_DATA247 0x406507DC FULL Memory buffer SCB5_EZ_DATA248 0x406507E0 FULL Memory buffer SCB...

Page 1370: ...SCB6_TX_CTRL 0x40660200 FULL Transmitter control SCB6_TX_FIFO_CTRL 0x40660204 FULL Transmitter FIFO control SCB6_TX_FIFO_STATUS 0x40660208 FULL Transmitter FIFO status SCB6_TX_FIFO_WR 0x40660240 FULL...

Page 1371: ...A50 0x406604C8 FULL Memory buffer SCB6_EZ_DATA51 0x406604CC FULL Memory buffer SCB6_EZ_DATA52 0x406604D0 FULL Memory buffer SCB6_EZ_DATA53 0x406604D4 FULL Memory buffer SCB6_EZ_DATA54 0x406604D8 FULL...

Page 1372: ...05C4 FULL Memory buffer SCB6_EZ_DATA114 0x406605C8 FULL Memory buffer SCB6_EZ_DATA115 0x406605CC FULL Memory buffer SCB6_EZ_DATA116 0x406605D0 FULL Memory buffer SCB6_EZ_DATA117 0x406605D4 FULL Memory...

Page 1373: ...6 0x406606C0 FULL Memory buffer SCB6_EZ_DATA177 0x406606C4 FULL Memory buffer SCB6_EZ_DATA178 0x406606C8 FULL Memory buffer SCB6_EZ_DATA179 0x406606CC FULL Memory buffer SCB6_EZ_DATA180 0x406606D0 FUL...

Page 1374: ...06607C8 FULL Memory buffer SCB6_EZ_DATA243 0x406607CC FULL Memory buffer SCB6_EZ_DATA244 0x406607D0 FULL Memory buffer SCB6_EZ_DATA245 0x406607D4 FULL Memory buffer SCB6_EZ_DATA246 0x406607D8 FULL Mem...

Page 1375: ...uration SCB7_TX_CTRL 0x40670200 FULL Transmitter control SCB7_TX_FIFO_CTRL 0x40670204 FULL Transmitter FIFO control SCB7_TX_FIFO_STATUS 0x40670208 FULL Transmitter FIFO status SCB7_TX_FIFO_WR 0x406702...

Page 1376: ...A50 0x406704C8 FULL Memory buffer SCB7_EZ_DATA51 0x406704CC FULL Memory buffer SCB7_EZ_DATA52 0x406704D0 FULL Memory buffer SCB7_EZ_DATA53 0x406704D4 FULL Memory buffer SCB7_EZ_DATA54 0x406704D8 FULL...

Page 1377: ...05C4 FULL Memory buffer SCB7_EZ_DATA114 0x406705C8 FULL Memory buffer SCB7_EZ_DATA115 0x406705CC FULL Memory buffer SCB7_EZ_DATA116 0x406705D0 FULL Memory buffer SCB7_EZ_DATA117 0x406705D4 FULL Memory...

Page 1378: ...6 0x406706C0 FULL Memory buffer SCB7_EZ_DATA177 0x406706C4 FULL Memory buffer SCB7_EZ_DATA178 0x406706C8 FULL Memory buffer SCB7_EZ_DATA179 0x406706CC FULL Memory buffer SCB7_EZ_DATA180 0x406706D0 FUL...

Page 1379: ...06707C8 FULL Memory buffer SCB7_EZ_DATA243 0x406707CC FULL Memory buffer SCB7_EZ_DATA244 0x406707D0 FULL Memory buffer SCB7_EZ_DATA245 0x406707D4 FULL Memory buffer SCB7_EZ_DATA246 0x406707D8 FULL Mem...

Page 1380: ...FULL Receiver interrupt request SCB7_INTR_RX_SET 0x40670FC4 FULL Receiver interrupt set request SCB7_INTR_RX_MASK 0x40670FC8 FULL Receiver interrupt mask SCB7_INTR_RX_MASKED 0x40670FCC FULL Receiver...

Page 1381: ...0 Name None 7 4 OVS 3 0 Bits 15 14 13 12 11 10 9 8 Name MEM_WIDTH 15 14 None 13 13 CMD _RESP_ MODE 12 12 None 11 11 EZ_MODE 10 10 EC_OP _MODE 9 9 EC_AM _MODE 8 8 Bits 23 22 21 20 19 18 17 16 Name Non...

Page 1382: ...he OVS field is NOT used However there is a frequency requirement for the SCB clock wrt the SPI input clock IF on the interface to guarantee functional correct behavior This requirement is expressed a...

Page 1383: ...s bitrates Pulse widths greater or equal than two SCB clock cycles are guaranteed to be detected by the receiver Pulse widths less than two SCB clock cycles and greater or equal than one SCB clock cyc...

Page 1384: ...ocked mode the serial interface protocols run off the clock as provided by the serial interface Externally clocked operation mode is only used for synchronous serial interface protocols SPI and I2C in...

Page 1385: ...for both I2C read and write transfers In multi processor UART receiver mode this field is used to allow the receiver to put the received address in the RX FIFO Note non matching addresses are never pu...

Page 1386: ...TX_FIFO_CTRL and receiver FIFO RX_FIFO_CTRL information Program CTRL register to enable SCB select the specific operation mode and oversampling factor Generally when this block is enabled no control...

Page 1387: ...SW HW Default or Enum Description 0 EC_BUSY R W Undefined Indicates whether the externally clocked logic is potentially accessing the EZ memory this is only possible in EZ mode This bit can be used b...

Page 1388: ...SE_WR _ADDR 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 8 BASE_RD_ADDR RW R 0 I2C SPI read base address for CMD_RESP mode At the start of a read transfer this BASE_RD_ADDR is copied...

Page 1389: ...er However when the last memory buffer address is reached the address is NOT incremented but remains at the maximum memory buffer address The field is used to determine how many bytes have been read b...

Page 1390: ...ESP_EC_BUSY R W Undefined Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable when CMD_RESP_EC_BUSY is 0 or not reliable when CMD_RESP_EC_BUSY is 1 Note When there...

Page 1391: ...ed in master mode In slave mode both continuous and non continuous SPI data transfers are supported independent of this field When continuous transfers are enabled individual data frame transfers are...

Page 1392: ...aptured Only used in master mode When 0 the default applies for Motorola as determined by CPOL and CPHA for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising...

Page 1393: ...loopback control does NOT affect the information on the pins Only used in master mode Not used in National Semiconductors submode 0 No local loopback 1 the SPI master MISO line is connected to the SPI...

Page 1394: ...e disabled when changes are made to this field 31 MASTER_MODE RW R 0 Master 1 or slave 0 mode In master mode transmission will commence on availability of data frames in the TX FIFO In slave mode when...

Page 1395: ...l the last MOSI MISO bit of the last data frame is transmitted 1 SPI_EC_BUSY R W Undefined Indicates whether the externally clocked logic is potentially accessing the EZ memory and or updating BASE_AD...

Page 1396: ...e 7 6 PARITY _ENABLED 5 5 PARITY 4 4 None 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name S...

Page 1397: ...5 9 DROP_ON _PARITY _ERROR 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 4 PARITY RW R 0 Parity b...

Page 1398: ...ffect the information on the pins 0 Loopback is not enabled 1 UART_TX is connected to UART_RX UART_RTS is connected to UART_CTS This allows a SCB UART transmitter to communicate with its receiver coun...

Page 1399: ...op period in terms of halve bit periods Valid range is 1 7 i e a stop period should last at least one bit period 4 PARITY RW R 0 Parity bit When 0 the transmitter generates an even parity When 1 the t...

Page 1400: ...receiver needs to resynchronize its start bit detection The amount of lost data frames depends on both the amount of stop bits the idle time between data frames and the data frame value 4 PARITY RW R...

Page 1401: ...TER Successful baud rate detection sets the INTR_RX BAUD_DETECT interrupt cause to 1 BR_COUNTER is reliable This functionality is used to synchronize refine the receiver clock to the transmitter clock...

Page 1402: ...standard also accounts for this imprecision a LIN start bit followed by 8 data bits allows for up to 9 consecutive 0 bit periods during regular transmission whereas the LIN break detection should be...

Page 1403: ...18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 11 BR_COUNTER R W Undefined Amount of SCB clock periods that constitute...

Page 1404: ...ne 23 17 RTS _POLAR ITY 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 26 CTS _ENABLED 25 25 CTS _POLAR ITY 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 TRIGGER_LEVEL RW R 0 Trigg...

Page 1405: ...t register 1 Enabled The UART transmitter uses CTS input signal to qualify the transmission of data It transmits when CTS input signal is active and a data frame is available for transmission in the T...

Page 1406: ...Bit fields Bits Name SW HW Default or Enum Description 0 3 HIGH_PHASE_OVS RW R 8 Serial I2C interface high phase oversampling factor HIGH_PHASE_OVS 1 SCB clock periods constitute the high phase of a...

Page 1407: ...a ready to SCL rising edge released from I2C slave clock stretching 8 M_READY_DATA_ACK RW R 1 When 1 a received data element by the master is immediately ACK d when the receiver FIFO is not full 9 M_N...

Page 1408: ...ot observe the NACK 2 SCB clock is not present in DeepSleep system power mode In this case the I2C master will observe the NACK and may retry the transfer in the future which gives the internally cloc...

Page 1409: ...CL line For a 100 kHz interface frequency this maximum high time may last roughly 5 us half a bit period For single master systems BUS_BUSY does not have to be used to detect an idle bus before a mast...

Page 1410: ..._ADDR R W Undefined I2C slave current EZ address Current address pointer This field is only reliable in internally clocked mode In externally clocked mode the field may be unreliable during an ongoing...

Page 1411: ...te but is working on an ongoing transaction The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a r...

Page 1412: ...mit a STOP When this action is performed the hardware sets this field to 0 I2C_M_CMD M_START has a higher priority than this command in situations where both a STOP and a REPEATED START could be trans...

Page 1413: ...Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 S_ACK RW RW1C 0 When 1 attempt to transmit an acknowledgement ACK When this action is performed the hardware sets this field to...

Page 1414: ...specs Programmability available if required 4 SDA_IN_FILT_SEL RW R 1 Enable for 50ns glitch filter on SDA input 0 0 ns 1 50 ns filter enabled 8 9 SCL_IN_FILT_TRIM RW R 0 Trim settings for the 50ns gli...

Page 1415: ...29 SDA_OUT_FILT_SEL RW R 0 Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter 0 0 ns 1 50 ns filter 0 enabled 2 100 ns filters 0 and 1 enabled 3 150 ns filters 0 1 and 2 enab...

Page 1416: ...16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 DATA_WIDTH RW R 7 Dataframe width DATA_WIDTH 1 is the amount of bits in a transmitted data...

Page 1417: ...n mode is used for IO cells that are connected to board wires lines that are driven by multiple IO cells possibly on multiple chips In this operation mode for and IO cell xxx that is used as an output...

Page 1418: ...ter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX TRIGGER is generated 16 CLEAR RW R 0 When 1 the transmitter FIFO and transmitter shift register are cleared...

Page 1419: ...nges from 0 to FF_DATA_NR EZ_DATA_NR 2 15 SR_VALID R W 0 Indicates whether the TX shift registers holds a valid data frame 1 or not 0 The shift register can be considered the top of the TX FIFO the da...

Page 1420: ...returns 0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 3...

Page 1421: ...pected amount of bits in received data frame This number does not include start parity and stop bits For UART mode the valid range is 3 8 For SPI the valid range is 3 31 For I2C the only valid value i...

Page 1422: ...the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX TRIGGER is generated 16 CLEAR RW R 0 When 1 the receiver FIFO and receiver shift register are cleared...

Page 1423: ...the receiver FIFO The value of this field ranges from 0 to FF_DATA_NR EZ_DATA_NR 2 15 SR_VALID R W 0 Indicates whether the RX shift registers holds a partial valid data frame 1 or not 0 The shift reg...

Page 1424: ...m Description 0 7 ADDR RW R 0 Slave device address In UART multi processor mode all 8 bits are used In I2C slave mode only bits 7 down to 1 are used This reflects the organization of the first transmi...

Page 1425: ...Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 DATA R W Undefined Data read from...

Page 1426: ...0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA 31 24 Bit fields Bits Name SW HW Default or Enum Descripti...

Page 1427: ...not in FIFO mode Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name EZ_DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24...

Page 1428: ...1 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 M R W 0 Master interrupt active interrupt_master INTR_M_MASKED 0...

Page 1429: ...used when CTRL EC_AM_MODE is 1 1 EZ_STOP RW1C A 0 STOP detection Activated on the end of a every transfer I2C STOP Only available for a slave request with an address match in EZ and CMD_RESP modes whe...

Page 1430: ...5 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 WAKE_UP RW R 0 Mask bit for corresponding bit in...

Page 1431: ...ociated interrupt is active 1 when INTR_I2C_EC_MASKED 0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 EZ_READ _STOP 3 3 EZ_WRITE _STOP 2 2 EZ_STOP 1 1 WAKE_UP 0 0 Bits 15 14 13 12 11...

Page 1432: ...ing slave request when externally clocked selection is 1 Only used when CTRL EC_AM_MODE is 1 1 EZ_STOP RW1C A 0 STOP detection Activated on the end of a every transfer SPI deselection Only available i...

Page 1433: ...5 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 WAKE_UP RW R 0 Mask bit for corresponding bit in...

Page 1434: ...ociated interrupt is active 1 when INTR_SPI_EC_MASKED 0 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 4 EZ_READ _STOP 3 3 EZ_WRITE _STOP 2 2 EZ_STOP 1 1 WAKE_UP 0 0 Bits 15 14 13 12 11...

Page 1435: ...20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 I2C_ARB_LOST RW1C RW1S 0 I2C master lost arbitration the value driv...

Page 1436: ...9 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 I2C_ARB_LOST RW1S A 0 Write with 1 to set corresponding bit in interrupt request register 1 I2C_NACK RW1S A 0...

Page 1437: ...25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 I2C_ARB_LOST RW R 0 Mask bit for corresponding bit in interrupt request register 1 I2C_NACK RW R 0 Mask bit for correspo...

Page 1438: ...4 3 2 1 0 Name None 7 5 I2C_STOP 4 4 None 3 3 I2C_ACK 2 2 I2C_NACK 1 1 I2C_ARB_L OST 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 10 SPI_DONE 9 9 I2C_BUS_E RROR 8 8 Bits 23 22 21 20 19 18 17 16 Name N...

Page 1439: ...RB_L OST 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 12 SPI_BUS_E RROR 11 11 SPI_EZ_ST OP 10 10 SPI_EZ _WRITE _STOP 9 9 I2C_BUS_E RROR 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28...

Page 1440: ...fers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware Note that the second I2C transfer after a REPEATED START may be to a different slave address...

Page 1441: ...g transfer The Firmware may decide to clear the TX and RX FIFOs in case of this error 9 SPI_EZ_WRITE_STOP RW1C RW1S 0 SPI slave deselected after a write EZ SPI transfer occurred 10 SPI_EZ_STOP RW1C RW...

Page 1442: ...ing bit in interrupt request register 2 I2C_ACK RW1S A 0 Write with 1 to set corresponding bit in interrupt request register 3 I2C_WRITE_STOP RW1S A 0 Write with 1 to set corresponding bit in interrup...

Page 1443: ...ng bit in interrupt request register 2 I2C_ACK RW R 0 Mask bit for corresponding bit in interrupt request register 3 I2C_WRITE_STOP RW R 0 Mask bit for corresponding bit in interrupt request register...

Page 1444: ...23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 I2C_ARB_LOST R W 0 Logical and of corresponding request an...

Page 1445: ...31 24 Bit fields Bits Name SW HW Default or Enum Description 0 TRIGGER RW1C RW1S 0 Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL TRIGGER_LEVEL Only used in FIFO mode 1 NOT_FULL...

Page 1446: ...register are empty Set to 1 when event is detected Write with 1 to clear bit 10 UART_ARB_LOST RW1C RW1S 0 UART lost arbitration the value driven on the TX line is not the same as the value observed o...

Page 1447: ...with 1 to set corresponding bit in interrupt request register 1 NOT_FULL RW1S A 0 Write with 1 to set corresponding bit in interrupt request register 4 EMPTY RW1S A 0 Write with 1 to set corresponding...

Page 1448: ...bit for corresponding bit in interrupt request register 1 NOT_FULL RW R 0 Mask bit for corresponding bit in interrupt request register 4 EMPTY RW R 0 Mask bit for corresponding bit in interrupt reques...

Page 1449: ...13 12 11 10 9 8 Name None 15 11 UART_ARB _LOST 10 10 UART _DONE 9 9 UART _NACK 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW...

Page 1450: ...RROR 9 9 FRAME _ERROR 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 TRIGGER RW1C RW1S 0 More en...

Page 1451: ...o tag erroneous data frames 9 PARITY_ERROR RW1C RW1S 0 Parity error in received data frame Set to 1 when event is detected Write with 1 to clear bit If UART_RX_CTL DROP_ON_PARITY_ERROR is 1 the receiv...

Page 1452: ...it in interrupt request register 2 NOT_EMPTY RW1S A 0 Write with 1 to set corresponding bit in interrupt status register 3 FULL RW1S A 0 Write with 1 to set corresponding bit in interrupt status regis...

Page 1453: ...interrupt request register 2 NOT_EMPTY RW R 0 Mask bit for corresponding bit in interrupt request register 3 FULL RW R 0 Mask bit for corresponding bit in interrupt request register 5 OVERFLOW RW R 0...

Page 1454: ...11 11 BAUD _DETECT 10 10 PARITY _ERROR 9 9 FRAME _ERROR 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Descrip...

Page 1455: ...0066A FULL Temperature sensor calibration data for VDDA 5V Temperature sensor diode voltage at ROOM SFLASH_EPASS_TEMP_TRIM_VBG_ROOMSORT_5V 0x1700066C FULL Temperature sensor calibration data for VDDA...

Page 1456: ...ULL USER_FREE_ROW0 SFLASH_USER_FREE_ROW048 0x170008C0 FULL USER_FREE_ROW0 SFLASH_USER_FREE_ROW049 0x170008C4 FULL USER_FREE_ROW0 SFLASH_USER_FREE_ROW050 0x170008C8 FULL USER_FREE_ROW0 SFLASH_USER_FREE...

Page 1457: ...FULL USER_FREE_ROW0 SFLASH_USER_FREE_ROW0111 0x170009BC FULL USER_FREE_ROW0 SFLASH_USER_FREE_ROW0112 0x170009C0 FULL USER_FREE_ROW0 SFLASH_USER_FREE_ROW0113 0x170009C4 FULL USER_FREE_ROW0 SFLASH_USER...

Page 1458: ...ULL USER_FREE_ROW1 SFLASH_USER_FREE_ROW146 0x17000AB8 FULL USER_FREE_ROW1 SFLASH_USER_FREE_ROW147 0x17000ABC FULL USER_FREE_ROW1 SFLASH_USER_FREE_ROW148 0x17000AC0 FULL USER_FREE_ROW1 SFLASH_USER_FREE...

Page 1459: ...ULL USER_FREE_ROW1 SFLASH_USER_FREE_ROW1109 0x17000BB4 FULL USER_FREE_ROW1 SFLASH_USER_FREE_ROW1110 0x17000BB8 FULL USER_FREE_ROW1 SFLASH_USER_FREE_ROW1111 0x17000BBC FULL USER_FREE_ROW1 SFLASH_USER_F...

Page 1460: ...ULL USER_FREE_ROW2 SFLASH_USER_FREE_ROW244 0x17000CB0 FULL USER_FREE_ROW2 SFLASH_USER_FREE_ROW245 0x17000CB4 FULL USER_FREE_ROW2 SFLASH_USER_FREE_ROW246 0x17000CB8 FULL USER_FREE_ROW2 SFLASH_USER_FREE...

Page 1461: ...L USER_FREE_ROW2 SFLASH_USER_FREE_ROW2107 0x17000DAC FULL USER_FREE_ROW2 SFLASH_USER_FREE_ROW2108 0x17000DB0 FULL USER_FREE_ROW2 SFLASH_USER_FREE_ROW2109 0x17000DB4 FULL USER_FREE_ROW2 SFLASH_USER_FRE...

Page 1462: ...ULL USER_FREE_ROW3 SFLASH_USER_FREE_ROW342 0x17000EA8 FULL USER_FREE_ROW3 SFLASH_USER_FREE_ROW343 0x17000EAC FULL USER_FREE_ROW3 SFLASH_USER_FREE_ROW344 0x17000EB0 FULL USER_FREE_ROW3 SFLASH_USER_FREE...

Page 1463: ...USER_FREE_ROW3 SFLASH_USER_FREE_ROW3106 0x17000FA8 FULL USER_FREE_ROW3 SFLASH_USER_FREE_ROW3107 0x17000FAC FULL USER_FREE_ROW3 SFLASH_USER_FREE_ROW3108 0x17000FB0 FULL USER_FREE_ROW3 SFLASH_USER_FREE...

Page 1464: ...SFLASH_PUBLIC_KEY17 0x17006411 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY18 0x17006412 FULL Public key for signature verification max RSA key size 4096 SFLASH_...

Page 1465: ...4096 SFLASH_PUBLIC_KEY49 0x17006431 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY50 0x17006432 FULL Public key for signature verification max RSA key size 4096 SFL...

Page 1466: ...4096 SFLASH_PUBLIC_KEY81 0x17006451 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY82 0x17006452 FULL Public key for signature verification max RSA key size 4096 SFL...

Page 1467: ...96 SFLASH_PUBLIC_KEY113 0x17006471 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY114 0x17006472 FULL Public key for signature verification max RSA key size 4096 SFL...

Page 1468: ...096 SFLASH_PUBLIC_KEY145 0x17006491 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY146 0x17006492 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1469: ...096 SFLASH_PUBLIC_KEY177 0x170064B1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY178 0x170064B2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1470: ...096 SFLASH_PUBLIC_KEY209 0x170064D1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY210 0x170064D2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1471: ...096 SFLASH_PUBLIC_KEY241 0x170064F1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY242 0x170064F2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1472: ...096 SFLASH_PUBLIC_KEY273 0x17006511 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY274 0x17006512 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1473: ...096 SFLASH_PUBLIC_KEY305 0x17006531 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY306 0x17006532 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1474: ...096 SFLASH_PUBLIC_KEY337 0x17006551 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY338 0x17006552 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1475: ...096 SFLASH_PUBLIC_KEY369 0x17006571 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY370 0x17006572 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1476: ...096 SFLASH_PUBLIC_KEY401 0x17006591 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY402 0x17006592 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1477: ...096 SFLASH_PUBLIC_KEY433 0x170065B1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY434 0x170065B2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1478: ...096 SFLASH_PUBLIC_KEY465 0x170065D1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY466 0x170065D2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1479: ...096 SFLASH_PUBLIC_KEY497 0x170065F1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY498 0x170065F2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1480: ...096 SFLASH_PUBLIC_KEY529 0x17006611 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY530 0x17006612 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1481: ...096 SFLASH_PUBLIC_KEY561 0x17006631 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY562 0x17006632 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1482: ...096 SFLASH_PUBLIC_KEY593 0x17006651 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY594 0x17006652 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1483: ...096 SFLASH_PUBLIC_KEY625 0x17006671 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY626 0x17006672 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1484: ...096 SFLASH_PUBLIC_KEY657 0x17006691 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY658 0x17006692 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1485: ...096 SFLASH_PUBLIC_KEY689 0x170066B1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY690 0x170066B2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1486: ...096 SFLASH_PUBLIC_KEY721 0x170066D1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY722 0x170066D2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1487: ...096 SFLASH_PUBLIC_KEY753 0x170066F1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY754 0x170066F2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1488: ...096 SFLASH_PUBLIC_KEY785 0x17006711 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY786 0x17006712 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1489: ...096 SFLASH_PUBLIC_KEY817 0x17006731 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY818 0x17006732 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1490: ...096 SFLASH_PUBLIC_KEY849 0x17006751 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY850 0x17006752 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1491: ...096 SFLASH_PUBLIC_KEY881 0x17006771 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY882 0x17006772 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1492: ...096 SFLASH_PUBLIC_KEY913 0x17006791 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY914 0x17006792 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1493: ...096 SFLASH_PUBLIC_KEY945 0x170067B1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY946 0x170067B2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1494: ...096 SFLASH_PUBLIC_KEY977 0x170067D1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY978 0x170067D2 FULL Public key for signature verification max RSA key size 4096 SF...

Page 1495: ...SFLASH_PUBLIC_KEY1009 0x170067F1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1010 0x170067F2 FULL Public key for signature verification max RSA key size 4096 SFLA...

Page 1496: ...96 SFLASH_PUBLIC_KEY1041 0x17006811 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1042 0x17006812 FULL Public key for signature verification max RSA key size 4096 S...

Page 1497: ...96 SFLASH_PUBLIC_KEY1073 0x17006831 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1074 0x17006832 FULL Public key for signature verification max RSA key size 4096 S...

Page 1498: ...96 SFLASH_PUBLIC_KEY1105 0x17006851 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1106 0x17006852 FULL Public key for signature verification max RSA key size 4096 S...

Page 1499: ...96 SFLASH_PUBLIC_KEY1137 0x17006871 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1138 0x17006872 FULL Public key for signature verification max RSA key size 4096 S...

Page 1500: ...96 SFLASH_PUBLIC_KEY1169 0x17006891 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1170 0x17006892 FULL Public key for signature verification max RSA key size 4096 S...

Page 1501: ...96 SFLASH_PUBLIC_KEY1201 0x170068B1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1202 0x170068B2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1502: ...96 SFLASH_PUBLIC_KEY1233 0x170068D1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1234 0x170068D2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1503: ...96 SFLASH_PUBLIC_KEY1265 0x170068F1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1266 0x170068F2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1504: ...96 SFLASH_PUBLIC_KEY1297 0x17006911 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1298 0x17006912 FULL Public key for signature verification max RSA key size 4096 S...

Page 1505: ...96 SFLASH_PUBLIC_KEY1329 0x17006931 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1330 0x17006932 FULL Public key for signature verification max RSA key size 4096 S...

Page 1506: ...96 SFLASH_PUBLIC_KEY1361 0x17006951 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1362 0x17006952 FULL Public key for signature verification max RSA key size 4096 S...

Page 1507: ...96 SFLASH_PUBLIC_KEY1393 0x17006971 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1394 0x17006972 FULL Public key for signature verification max RSA key size 4096 S...

Page 1508: ...96 SFLASH_PUBLIC_KEY1425 0x17006991 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1426 0x17006992 FULL Public key for signature verification max RSA key size 4096 S...

Page 1509: ...96 SFLASH_PUBLIC_KEY1457 0x170069B1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1458 0x170069B2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1510: ...96 SFLASH_PUBLIC_KEY1489 0x170069D1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1490 0x170069D2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1511: ...96 SFLASH_PUBLIC_KEY1521 0x170069F1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1522 0x170069F2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1512: ...96 SFLASH_PUBLIC_KEY1553 0x17006A11 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1554 0x17006A12 FULL Public key for signature verification max RSA key size 4096 S...

Page 1513: ...96 SFLASH_PUBLIC_KEY1585 0x17006A31 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1586 0x17006A32 FULL Public key for signature verification max RSA key size 4096 S...

Page 1514: ...96 SFLASH_PUBLIC_KEY1617 0x17006A51 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1618 0x17006A52 FULL Public key for signature verification max RSA key size 4096 S...

Page 1515: ...96 SFLASH_PUBLIC_KEY1649 0x17006A71 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1650 0x17006A72 FULL Public key for signature verification max RSA key size 4096 S...

Page 1516: ...96 SFLASH_PUBLIC_KEY1681 0x17006A91 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1682 0x17006A92 FULL Public key for signature verification max RSA key size 4096 S...

Page 1517: ...96 SFLASH_PUBLIC_KEY1713 0x17006AB1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1714 0x17006AB2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1518: ...96 SFLASH_PUBLIC_KEY1745 0x17006AD1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1746 0x17006AD2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1519: ...96 SFLASH_PUBLIC_KEY1777 0x17006AF1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1778 0x17006AF2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1520: ...96 SFLASH_PUBLIC_KEY1809 0x17006B11 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1810 0x17006B12 FULL Public key for signature verification max RSA key size 4096 S...

Page 1521: ...96 SFLASH_PUBLIC_KEY1841 0x17006B31 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1842 0x17006B32 FULL Public key for signature verification max RSA key size 4096 S...

Page 1522: ...96 SFLASH_PUBLIC_KEY1873 0x17006B51 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1874 0x17006B52 FULL Public key for signature verification max RSA key size 4096 S...

Page 1523: ...96 SFLASH_PUBLIC_KEY1905 0x17006B71 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1906 0x17006B72 FULL Public key for signature verification max RSA key size 4096 S...

Page 1524: ...96 SFLASH_PUBLIC_KEY1937 0x17006B91 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1938 0x17006B92 FULL Public key for signature verification max RSA key size 4096 S...

Page 1525: ...96 SFLASH_PUBLIC_KEY1969 0x17006BB1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY1970 0x17006BB2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1526: ...96 SFLASH_PUBLIC_KEY2001 0x17006BD1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2002 0x17006BD2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1527: ...96 SFLASH_PUBLIC_KEY2033 0x17006BF1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2034 0x17006BF2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1528: ...96 SFLASH_PUBLIC_KEY2065 0x17006C11 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2066 0x17006C12 FULL Public key for signature verification max RSA key size 4096 S...

Page 1529: ...96 SFLASH_PUBLIC_KEY2097 0x17006C31 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2098 0x17006C32 FULL Public key for signature verification max RSA key size 4096 S...

Page 1530: ...96 SFLASH_PUBLIC_KEY2129 0x17006C51 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2130 0x17006C52 FULL Public key for signature verification max RSA key size 4096 S...

Page 1531: ...96 SFLASH_PUBLIC_KEY2161 0x17006C71 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2162 0x17006C72 FULL Public key for signature verification max RSA key size 4096 S...

Page 1532: ...96 SFLASH_PUBLIC_KEY2193 0x17006C91 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2194 0x17006C92 FULL Public key for signature verification max RSA key size 4096 S...

Page 1533: ...96 SFLASH_PUBLIC_KEY2225 0x17006CB1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2226 0x17006CB2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1534: ...96 SFLASH_PUBLIC_KEY2257 0x17006CD1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2258 0x17006CD2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1535: ...96 SFLASH_PUBLIC_KEY2289 0x17006CF1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2290 0x17006CF2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1536: ...96 SFLASH_PUBLIC_KEY2321 0x17006D11 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2322 0x17006D12 FULL Public key for signature verification max RSA key size 4096 S...

Page 1537: ...96 SFLASH_PUBLIC_KEY2353 0x17006D31 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2354 0x17006D32 FULL Public key for signature verification max RSA key size 4096 S...

Page 1538: ...96 SFLASH_PUBLIC_KEY2385 0x17006D51 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2386 0x17006D52 FULL Public key for signature verification max RSA key size 4096 S...

Page 1539: ...96 SFLASH_PUBLIC_KEY2417 0x17006D71 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2418 0x17006D72 FULL Public key for signature verification max RSA key size 4096 S...

Page 1540: ...96 SFLASH_PUBLIC_KEY2449 0x17006D91 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2450 0x17006D92 FULL Public key for signature verification max RSA key size 4096 S...

Page 1541: ...96 SFLASH_PUBLIC_KEY2481 0x17006DB1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2482 0x17006DB2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1542: ...96 SFLASH_PUBLIC_KEY2513 0x17006DD1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2514 0x17006DD2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1543: ...96 SFLASH_PUBLIC_KEY2545 0x17006DF1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2546 0x17006DF2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1544: ...96 SFLASH_PUBLIC_KEY2577 0x17006E11 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2578 0x17006E12 FULL Public key for signature verification max RSA key size 4096 S...

Page 1545: ...96 SFLASH_PUBLIC_KEY2609 0x17006E31 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2610 0x17006E32 FULL Public key for signature verification max RSA key size 4096 S...

Page 1546: ...96 SFLASH_PUBLIC_KEY2641 0x17006E51 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2642 0x17006E52 FULL Public key for signature verification max RSA key size 4096 S...

Page 1547: ...96 SFLASH_PUBLIC_KEY2673 0x17006E71 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2674 0x17006E72 FULL Public key for signature verification max RSA key size 4096 S...

Page 1548: ...96 SFLASH_PUBLIC_KEY2705 0x17006E91 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2706 0x17006E92 FULL Public key for signature verification max RSA key size 4096 S...

Page 1549: ...96 SFLASH_PUBLIC_KEY2737 0x17006EB1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2738 0x17006EB2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1550: ...96 SFLASH_PUBLIC_KEY2769 0x17006ED1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2770 0x17006ED2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1551: ...96 SFLASH_PUBLIC_KEY2801 0x17006EF1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2802 0x17006EF2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1552: ...96 SFLASH_PUBLIC_KEY2833 0x17006F11 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2834 0x17006F12 FULL Public key for signature verification max RSA key size 4096 S...

Page 1553: ...96 SFLASH_PUBLIC_KEY2865 0x17006F31 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2866 0x17006F32 FULL Public key for signature verification max RSA key size 4096 S...

Page 1554: ...96 SFLASH_PUBLIC_KEY2897 0x17006F51 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2898 0x17006F52 FULL Public key for signature verification max RSA key size 4096 S...

Page 1555: ...96 SFLASH_PUBLIC_KEY2929 0x17006F71 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2930 0x17006F72 FULL Public key for signature verification max RSA key size 4096 S...

Page 1556: ...96 SFLASH_PUBLIC_KEY2961 0x17006F91 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2962 0x17006F92 FULL Public key for signature verification max RSA key size 4096 S...

Page 1557: ...96 SFLASH_PUBLIC_KEY2993 0x17006FB1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY2994 0x17006FB2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1558: ...96 SFLASH_PUBLIC_KEY3025 0x17006FD1 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY3026 0x17006FD2 FULL Public key for signature verification max RSA key size 4096 S...

Page 1559: ...RSA key size 4096 SFLASH_PUBLIC_KEY3058 0x17006FF2 FULL Public key for signature verification max RSA key size 4096 SFLASH_PUBLIC_KEY3059 0x17006FF3 FULL Public key for signature verification max RSA...

Page 1560: ...FULL Application protection settings 4 128 512 bytes SFLASH_APP_PROT_SETTINGS35 0x1700768C FULL Application protection settings 4 128 512 bytes SFLASH_APP_PROT_SETTINGS36 0x17007690 FULL Application p...

Page 1561: ...ROT_SETTINGS97 0x17007784 FULL Application protection settings 4 128 512 bytes SFLASH_APP_PROT_SETTINGS98 0x17007788 FULL Application protection settings 4 128 512 bytes SFLASH_APP_PROT_SETTINGS99 0x1...

Page 1562: ...lication Object SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR 0x17007C20 FULL Address of Second CM4 or CM7 core1 User Application Object SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR 0x17007C24 FULL Address of First...

Page 1563: ...sed to store Silicon Revision ID Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name SI_REVISION_ID 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1564: ...nt Used to store silicon ID Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name ID 7 0 Bits 15 14 13 12 11 10 9 8 Name ID 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25...

Page 1565: ...ult 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA32 31 24 B...

Page 1566: ...end of Flash boot 2 Enable toggling a GPIO pin at the start and end of Flash boot Others Disable toggling a GPIO pin at the start and end of Flash boot Default value 1 2 3 FB_RSA3K_CTL RW 1 Determine...

Page 1567: ...on data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 3...

Page 1568: ...ion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1569: ...on data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 3...

Page 1570: ...on data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 3...

Page 1571: ...ion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1572: ...on data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 3...

Page 1573: ...ion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1574: ...ion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1575: ...on data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 3...

Page 1576: ...ation data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 3...

Page 1577: ...tion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1578: ...ation data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 3...

Page 1579: ...tion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1580: ...ation data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 3...

Page 1581: ...tion data for EPASS Temperature sensor Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA16 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA16 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31...

Page 1582: ...8 Name None 15 13 REGHC_TRANS_VADJ_OFFSET 12 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 4 PMIC...

Page 1583: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA3...

Page 1584: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA3...

Page 1585: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA3...

Page 1586: ...ment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA3...

Page 1587: ...t Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA32 3...

Page 1588: ...p No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 1589: ...le Bits 7 6 5 4 3 2 1 0 Name APP_ID 7 0 Bits 15 14 13 12 11 10 9 8 Name APP_ID 15 8 Bits 23 22 21 20 19 18 17 16 Name MINOR_VERSION 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 28 MAJOR_VERSION 27...

Page 1590: ...p No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Na...

Page 1591: ...No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 1592: ...etained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27...

Page 1593: ...IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 2...

Page 1594: ...Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 2...

Page 1595: ...No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name...

Page 1596: ...Retention Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 B...

Page 1597: ...IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 2...

Page 1598: ...0 Retention Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16...

Page 1599: ...IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27...

Page 1600: ...18 Retention Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16...

Page 1601: ...Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DA...

Page 1602: ...ion Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31...

Page 1603: ...on Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 3...

Page 1604: ...ion Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31...

Page 1605: ...When marker is set to 0xFEDEEDDF the following PPUs will be configured during boot PERI_MS_PPU_FX_PERI_GR2_GROUP Fixed PPU read only for all PCs Programmable PPU 11 configured to allow full access for...

Page 1606: ...tained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29...

Page 1607: ...007D04 Offset 0x7D04 Retention Retained IsDeepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16...

Page 1608: ...eepSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 2...

Page 1609: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA32 7 0 Bits 15 14 13 12 11 10 9 8 Name DATA32 15 8 Bits 23 22 21 20 19 18 17 16 Name DATA32 23 16 Bits 31 30 29 28 27 26 25 24 Name DATA32 31 24 Bit field...

Page 1610: ...nfiguration default 2 4 LISTEN_WINDOW RW 0 Determines the Listen window to allow sufficient time to acquire debug port When CLOCK_CONFIG is set to 3 these window times are calculated assuming ROM boot...

Page 1611: ...if the internal bootloader in Flash boot is disabled 0 Internal bootloader is disabled 1 Internal bootloader is launched if the other bootloader conditions are met default 2 Internal bootloader is dis...

Page 1612: ...Address Permission Description SMARTIO_PRT13_CTL 0x40320D00 FULL Control register SMARTIO_PRT13_SYNC_CTL 0x40320D10 FULL Synchronization control register SMARTIO_PRT13_LUT_SEL0 0x40320D20 FULL LUT com...

Page 1613: ...T component input selection SMARTIO_PRT15_LUT_CTL0 0x40320F40 FULL LUT component control register SMARTIO_PRT15_LUT_CTL1 0x40320F44 FULL LUT component control register SMARTIO_PRT15_LUT_CTL2 0x40320F4...

Page 1614: ...on SMARTIO_PRT17_DU_SEL 0x403211C0 FULL Data unit component input selection SMARTIO_PRT17_DU_CTL 0x403211C4 FULL Data unit component control register SMARTIO_PRT17_DATA 0x403211F0 FULL Data register 1...

Page 1615: ...None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLED 31 31 None 30 26 PIPELINE_ EN 25 25 HLD_OVR 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 BYPASS RW R Undefined Bypass of the pr...

Page 1616: ..._lf Note that the fabric s clocked elements are frequency aligned but NOT phase aligned to other clk_lf clocked elements 20 30 Clock source is constant 0 Any of these clock sources should be selected...

Page 1617: ...and LUTs reset is activated If the IP is disabled The PIPELINE_EN register field should be set to 1 to ensure low power consumption by preventing combinatorial loops The CLOCK_SRC register field shoul...

Page 1618: ...16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 IO_SYNC_EN RW R Undefined Synchronization of the IO pin input signals to clk_fabric one bit...

Page 1619: ...gnal tr0_in source selection 0 Data unit output 1 LUT 1 output 2 LUT 2 output 3 LUT 3 output 4 LUT 4 output 5 LUT 5 output 6 LUT 6 output 7 LUT 7 output 8 chip_data 0 for LUTs 0 1 2 3 chip_data 4 for...

Page 1620: ...LUTs 4 5 6 7 10 chip_data 2 for LUTs 0 1 2 3 chip_data 6 for LUTs 4 5 6 7 11 chip_data 3 for LUTs 0 1 2 3 chip_data 7 for LUTs 4 5 6 7 12 io_data_in 0 for LUTs 0 1 2 3 io_data_in 4 for LUTs 4 5 6 7 13...

Page 1621: ...p flop and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential state lut_reg 8 9 LUT_OPC RW R Undefined LUT opcode speci...

Page 1622: ...EL RW R Undefined Data unit input signal tr0_in source selection 0 Constant 0 1 Constant 1 2 Data unit output 10 3 LUT 7 0 outputs Otherwise Undefined 8 11 DU_TR1_SEL RW R Undefined Data unit input si...

Page 1623: ...17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 DU_SIZE RW R Undefined Size width of the data unit data operands in bits i...

Page 1624: ...0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name DATA 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits...

Page 1625: ...HVLVD Configuration Register Note HVLVD1_TRIPSEL HVLVD1_SRCSEL HVLVD1_EN are not available for this register PWR_LVD_CTL2 0x40261024 FULL High Voltage Low Voltage Detector HVLVD Configuration Register...

Page 1626: ...Clock Supervision Monitor Control 26 2 CSV_REF 26 2 1 CSV Register Name Address Permission Description CSV_REF_CSV_REF_CTL 0x40261710 FULL Clock Supervision Reference Control CSV_REF_CSV_REF_LIMIT 0x4...

Page 1627: ...8194 FULL MCWDT Service Register MCWDT1_INTR 0x402681A0 FULL MCWDT Interrupt Register MCWDT1_INTR_SET 0x402681A4 FULL MCWDT Interrupt Set Register MCWDT1_INTR_MASK 0x402681A8 FULL MCWDT Interrupt Mask...

Page 1628: ...4026C050 FULL WDT Interrupt Register WDT_INTR_SET 0x4026C054 FULL WDT Interrupt Set Register WDT_INTR_MASK 0x4026C058 FULL WDT Interrupt Mask Register WDT_INTR_MASKED 0x4026C05C FULL WDT Interrupt Mas...

Page 1629: ...Monitoring System Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 HVLVD1 _OUT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 2...

Page 1630: ...g System Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 HVLVD2 _OUT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25...

Page 1631: ...n undefined behavior It can be used to clocks to DSI or as reference inputs for the FLL PLL subject to the frequency limits of those circuits This mux is not glitch free so do not change the selection...

Page 1632: ...be a gated version of a fast clock and therefore may have a short high pulse PATH_SEL0 5 Selects the clock path chosen by PATH_SEL0 field HFCLK_SEL0 6 Selects the output of the HFCLK_SEL0 mux SLOW_SEL...

Page 1633: ...UTPUT_SLOW SLOW_SEL1 20 23 PATH_SEL1 RW R 0 Selects a clock path to use in fast clock output 1 logic 0 FLL output 1 15 PLL output on path1 path15 if available 24 27 HFCLK_SEL1 RW R 0 Selects a HFCLK t...

Page 1634: ...low speed clock tree LFCLK IMO 6 Internal Main Oscillator IMO This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry exit SLPCTRL 7 Sleep Controller clock SLPCTRL This is g...

Page 1635: ...o it can be observed during DEEPSLEEP entry exit PILO 8 Precision Internal Low Speed Oscillator PILO ILO1 9 Internal Low Speed Oscillator ILO1 if present on the product ECO_PRESCALER 10 ECO Prescaler...

Page 1636: ...utput 0 see CLK_OUTPUT_FAST This register always reads as zero Counting starts internally when this register is written with a nonzero value CAL_COUNTER_DONE goes immediately low to indicate that the...

Page 1637: ...27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 23 CAL_COUNTER2 R RW 0 Up counter clocked on fast clock output 1 see CLK_OUTPUT_FAST When CLK_CAL_CNT1 CAL_COUNTER_...

Page 1638: ...None 4 3 HVLVD2 2 2 HVLVD1 1 1 None 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW D...

Page 1639: ...VD1 1 1 None 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Descript...

Page 1640: ...Table Bits 7 6 5 4 3 2 1 0 Name None 7 6 CLK_CAL 5 5 None 4 3 HVLVD2 2 2 HVLVD1 1 1 None 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27...

Page 1641: ...Table Bits 7 6 5 4 3 2 1 0 Name None 7 6 CLK_CAL 5 5 None 4 3 HVLVD2 2 2 HVLVD1 1 1 None 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27...

Page 1642: ...w speed clocks are available Communication interface clocks may be present 4 DEBUG_SESSION R RW 0 Indicates whether a debug session is active CDBGPWRUPREQ signal is 1 NO_SESSION 0 No debug session act...

Page 1643: ...ly supervision reset 0 Linear Core Regulator is not explicitly disabled Hardware disables it automatically for internal sequences including for DEEPSLEEP HIBERNATE and XRES low power modes 1 Linear Co...

Page 1644: ...Hardware disables it automatically for internal sequences including for HIBERNATE and XRES low power modes Hardware keeps the Retention Regulator enabled during ACTIVE SLEEP modes so it is ready to e...

Page 1645: ...5 REFI_OK R RW 0 Indicates that the current reference is ready Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS 1 26 REFI_LPMODE R...

Page 1646: ...t 0 Do not bypass the level shifter This setting is ok for all operational modes and vccd target voltage 1 Bypass the level shifter This may reduce jitter on the PLL output clock but can only be used...

Page 1647: ...ken that is retained through a HIBERNATE WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event Note that waking up from HIBERNATE using XRES will reset this r...

Page 1648: ...scribed 1 Further writes to this register are ignored Note This bit is a write once bit until the next reset Avoid changing any other bits in this register while disabling HIBERNATE mode Also it is re...

Page 1649: ...LE 24 24 Bit fields Bits Name SW HW Default or Enum Description 0 BODVDDD_VSEL RW A 0 Selects the voltage threshold for BOD on vddd The BOD does not reliably monitor the supply during the transition 0...

Page 1650: ...20 OVDVDDA_VSEL RW A 0 Selects the voltage threshold for OVD on vdda Ensure OVDVDDA_ENABLE 0 before changing this setting to prevent false triggers 0 vddd 5 5V 1 vddd 5 0V 22 23 OVDVDDA_ACTION RW A 0...

Page 1651: ...et the chip 1 BODVDDA_OK R RW 0 BOD indicates vdda is ok 2 BODVCCD_OK R RW 1 BOD indicates vccd is ok This will always read 1 because a detected brownout will reset the chip 8 OVDVDDD_OK R RW 1 OVD in...

Page 1652: ...0 rise 1 225V nom fall 1 2V nom 1 rise 1 425V nom fall 1 4V nom 2 rise 1 625V nom fall 1 6V nom 3 rise 1 825V nom fall 1 8V nom 4 rise 2 025V nom fall 2V nom 5 rise 2 125V nom fall 2 1V nom 6 rise 2...

Page 1653: ...l 4 4V nom 17 rise 4 525V nom fall 4 5V nom 18 rise 4 625V nom fall 4 6V nom 19 rise 4 725V nom fall 4 7V nom 20 rise 4 825V nom fall 4 8V nom 21 rise 4 925V nom fall 4 9V nom 22 rise 5 025V nom fall...

Page 1654: ...ector HVLVD1_EN 0 before changing the threshold 0 rise 2 825V nom fall 2 8V nom 1 rise 2 925V nom fall 2 9V nom 2 rise 3 025V nom fall 3 0V nom 3 rise 3 125V nom fall 3 1V nom 4 rise 3 225V nom fall 3...

Page 1655: ...only Do not change other HVLVD2 settings when enabled 16 17 HVLVD2_EDGE_SEL RW R 0 Sets which edge s will trigger an action when the threshold is crossed DISABLE 0 Disabled RISING 1 Rising edge FALLI...

Page 1656: ...15 14 13 12 11 10 9 8 Name HIB_DATA 15 8 Bits 23 22 21 20 19 18 17 16 Name HIB_DATA 23 16 Bits 31 30 29 28 27 26 25 24 Name HIB_DATA 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 H...

Page 1657: ...30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 PATH_MUX RW R 0 Selects a source for clock PATH i Note that not all products support all clock sources S...

Page 1658: ...L using the related CLK_PLL_CONFIG k register Note that not all products support all clock sources Selecting a clock source that is not supported will result in undefined behavior It takes four cycles...

Page 1659: ...with clock supervision the output of this mux is the monitored clock for CSV_HF k NO_DIV 0 Transparent mode feed through selected clock source w o dividing DIV_BY_2 1 Divide selected clock source by...

Page 1660: ...0 ILO0 Internal Low speed Oscillator 0 WCO 1 WCO Watch Crystal Oscillator Requires Backup domain to be present and properly configured including external watch crystal if used ALTLF 2 ALTLF Alternate...

Page 1661: ...Rev B Bits Name SW HW Default or Enum Description DIV_BY_4 2 N A DIV_BY_8 3 N A DIV_BY_16 4 N A 15 PUMP_ENABLE RW R 0 Reserved Not used in the product 1661 2022 04 18 TRAVEO T2G Automotive MCU TVII B...

Page 1662: ...e Do not use in new designs Keep default value in new designs IMO 0 Obsolete Do not use in new designs Keep default value in new designs HF0_DIV 1 Obsolete Do not use in new designs 8 9 TIMER_HF0_DIV...

Page 1663: ...ndicates if ILO0 should stay enabled through power related resets on other supplies e g BOD on VDDD VCCD Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register This regist...

Page 1664: ...one 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLE 31 31 ILO1_MON _ENABLE 30 30 None 29 24 Bit fields Bits Name SW HW Default or Enum Description 30 ILO1_MO...

Page 1665: ...s This is done in fast IMO FIMO mode that does not require any external references and runs at a fixed 12MHz Default 0x80000000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 0 Bits 15 14 13 12 11 1...

Page 1666: ...ly damage the crystal 27 ECO_DIV_DISABLE RW RW1C 0 ECO prescaler disable command mutually exclusive with ECO_DIV_ENABLE SW sets this field to 1 and HW sets this field to 0 HW sets ECO_DIV_DISABLE fiel...

Page 1667: ...Default or Enum Description 31 ECO_EN RW R 0 Master enable for ECO oscillator Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal before enabling ECO 1667 2022 04 18 TRAVEO T2G...

Page 1668: ..._DIV 25 24 Bit fields Bits Name SW HW Default or Enum Description 0 ECO_DIV_ENABLED R RW 0 ECO prescaler enabled HW sets this field to 1 as a result of an CLK_ECO_CONFIG ECO_DIV_ENABLE command HW sets...

Page 1669: ...17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 ECO_OK R W 0 Indicates the ECO internal oscillator circuit has sufficient am...

Page 1670: ...FLL_MULT 7 0 Bits 15 14 13 12 11 10 9 8 Name FLL_MULT 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 18 FLL_MULT 17 16 Bits 31 30 29 28 27 26 25 24 Name FLL _ENABLE 31 31 None 30 25 FLL _OUTPUT _DIV 2...

Page 1671: ...when LOCKED 1 To disable the FLL use the following sequence 1 Write CLK_FLL_CONFIG3 BYPASS_SEL FLL_REF 2 Read CLK_FLL_CONFIG3 BYPASS_SEL to ensure the write completes read is not optional 3 Wait at l...

Page 1672: ...for reference divider Set the divide value before enabling the FLL and do not change it while FLL is enabled 0 illegal undefined behavior 1 divide by 1 8191 divide by 8191 16 23 LOCK_TOL RW R 2 Lock...

Page 1673: ...16 Name None 23 21 SETTLING_COUNT 20 16 Bits 31 30 29 28 27 26 25 24 Name None 31 30 BYPASS_SEL 29 28 None 27 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 FLL_LF_IGAIN RW R 0 FLL Loop...

Page 1674: ...red Refer to FLL disable sequence for more details in CLK_FLL_CONFIG FLL_ENABLE Whenever BYPASS_SEL is changed it is required to read CLK_FLL_CONFIG3 to ensure the change takes effect AUTO 0 Automatic...

Page 1675: ...CCO_RANGE RW R 0 Frequency range of CCO RANGE0 0 Target frequency is in range 48 64 MHz RANGE1 1 Target frequency is in range 64 85 MHz RANGE2 2 Target frequency is in range 85 113 MHz RANGE3 3 Targe...

Page 1676: ...t field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 CCO _READY 2 2 UNLOCK _OC CURRED 1 1 LOCKED 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28...

Page 1677: ...9 8 Name None 15 15 GTRIM 14 12 RTRIM 11 10 FTRIM 9 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0...

Page 1678: ...ated limit can permanently damage the crystal 0x0 Vp 0 35V 0x1 Vp 0 40V 0x2 Vp 0 45V 0x3 Vp 0 50V 0x4 Vp 0 55V 0x5 Vp 0 60V 0x6 Vp 0 65V 0x7 Vp 0 70V 0x8 Vp 0 75V 0x9 Vp 0 80V 0xA Vp 0 85V 0xB Vp 0 90...

Page 1679: ...ts Name SW HW Default or Enum Description 0 6 FEEDBACK_DIV RW R 22 Control bits for feedback divider Set the divide value before enabling the PLL and do not change it while PLL is enabled 0 21 illegal...

Page 1680: ...s whichever is slower AUTO 0 Automatic using lock indicator When unlocked automatically selects PLL reference input bypass mode When locked automatically selects PLL output If ENABLE 0 automatically s...

Page 1681: ...n depending on the frequency ration between system and PLL frequency Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 2 UNLOCK _OC CURRED 1 1 LOCKED 0 0 Bits 15 14 13 12 11 10 9 8 Name Non...

Page 1682: ...30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 REF_MUX RW R 0 Selects a source for clock clk_ref_hf Note that not all products support all clock sourc...

Page 1683: ..._OVD VDDD 20 20 RESET _BOD VCCD 19 19 RESET _BOD VDDA 18 18 RESET _BOD VDDD 17 17 RESET _XRES 16 16 Bits 31 30 29 28 27 26 25 24 Name None 31 31 RESET _POR VDDD 30 30 RESET _STRUCT _XRES 29 29 RESET _...

Page 1684: ...not blocked by other HV cause bits 17 RESET_BODVDDD RW1C A 0 External VDDD supply crossed brown out limit Note that this cause will only be observable as long as the VDDD supply does not go below the...

Page 1685: ...r set this bit This is a high voltage cause bit that blocks recording of other high voltage cause bits except RESET_PORVDDD Hardware clears this bit during POR 26 RESET_PMIC RW1C A 0 PMIC status trigg...

Page 1686: ...detected brown out Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name RESET_CSV_HF 7 0 Bits 15 14 13 12 11 10 9 8 Name RESET_CSV_HF 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 17 RESET _CSV_REF...

Page 1687: ...either SECURE TEST or FIRMWARE TEST key Must not be changed in the same write that is toggling any of the _WR bits below 8 11 FW_WR RW R 0 Latch enables for each of the 4 bytes in the 32 bit FIRMWARE...

Page 1688: ...eset that is equivalent to XRES except for RES_CAUSE registers Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 PXRES _TRIGGER 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21...

Page 1689: ...15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 WAKE_DELAY RW...

Page 1690: ...are reset by XRES and power related resets unless configured otherwise Default 0x52C Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 6 ILO0_FTRIM 5 0 Bits 15 14 13 12 11 10 9 8 Name None 15 12 ILO0_...

Page 1691: ...efault 0x52C Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 6 ILO1_FTRIM 5 0 Bits 15 14 13 12 11 10 9 8 Name None 15 12 ILO1_MONTRIM 11 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 2...

Page 1692: ...eference frequency Monitored frequency On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added 30 CSV_ACTION RW R 0 Specifies the action taken when an an...

Page 1693: ...it Set the lower limit 1 in reference clock cycles before the next monitored clock event is allowed to happen If a monitored clock event happens before this limit is reached a CSV error is detected LO...

Page 1694: ...Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 PERIOD RW R 0 Period time Set the Period 1 in monitored clock cycles before the...

Page 1695: ...Reference frequency Monitored frequency On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added 30 CSV_ACTION RW R 0 Specifies the action taken when an a...

Page 1696: ...it Set the lower limit 1 in reference clock cycles before the next monitored clock event is allowed to happen If a monitored clock event happens before this limit is reached a CSV error is detected LO...

Page 1697: ...Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 PERIOD RW R 0 Period time Set the Period 1 in monitored clock cycles before th...

Page 1698: ...running STARTUP PERIOD 3 FREQ_RATIO UPPER with FREQ_RATIO Reference frequency Monitored frequency On top of that the actual clock startup delay and the margin for accuracy of both clocks must be adde...

Page 1699: ...Set the lower limit 1 in reference clock cycles before the next monitored clock event is allowed to happen If a monitored clock event happens before this limit is reached a CSV error is detected LOWE...

Page 1700: ...Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 PERIOD RW R 0 Period time Set the Period 1 in monitored clock cycles before the...

Page 1701: ...s running STARTUP PERIOD 3 FREQ_RATIO UPPER with FREQ_RATIO Reference frequency Monitored frequency On top of that the actual clock startup delay and the margin for accuracy of both clocks must be add...

Page 1702: ...t Set the lower limit 1 in reference clock cycles before the next monitored clock event is allowed to happen If a monitored clock event happens before this limit is reached a CSV error is detected LOW...

Page 1703: ...Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 7 PERIOD RW R 0 Period time Set the Period 1 in monitored clock cycles before the...

Page 1704: ...eld Table Bits 7 6 5 4 3 2 1 0 Name None 7 2 CPU_SEL 1 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields...

Page 1705: ...able Bits 7 6 5 4 3 2 1 0 Name None 7 1 ENABLED 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLE 31 31 None 30 24 Bit...

Page 1706: ...28 None 27 24 Bit fields Bits Name SW HW Default or Enum Description 0 ACTION RW R 0 Action taken when the specified BIT toggles Action will be triggered on the same edge where BITS to observe toggle...

Page 1707: ...responding processor is in SLEEPDEEP 31 DEBUG_RUN RW R 0 Pauses runs this counter while a debugger is connected Other behaviors are unchanged during debugging including service configuration updates a...

Page 1708: ...4 13 12 11 10 9 8 Name CNT2 15 8 Bits 23 22 21 20 19 18 17 16 Name CNT2 23 16 Bits 31 30 29 28 27 26 25 24 Name CNT2 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 CNT2 RW A 0 Curre...

Page 1709: ...16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 MCWDT_LOCK RW A 0 Prohibits writing control and configuration registers relat...

Page 1710: ...to zero This may take up to three clk_lf cycles to take effect Hardware clears this bit after necessary synchronization To ensure a pending CTR0_SERVICE write is reflected firmware should wait until t...

Page 1711: ...24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 CTR0_INT RW1C A 0 MCWDT Interrupt Request for sub counter 0 This bit is set by hardware as configured by this registers This...

Page 1712: ...6 5 4 3 2 1 0 Name None 7 3 CTR2_INT 2 2 CTR1_INT 1 1 CTR0_INT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24...

Page 1713: ...ult or Enum Description 0 CTR0_INT RW R 0 Interrupt Mask for sub counter 0 for warning interrupt The bit controls if the interrupt is forwarded to the CPU The interrupt is blocked when the value of th...

Page 1714: ...egister Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 3 CTR2_INT 2 2 CTR1_INT 1 1 CTR0_INT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bit...

Page 1715: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 ENABLED 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name ENABLE 31 31 No...

Page 1716: ...effect Before changing the limit it is recommended to set the service bit for this subcounter within the configured limits This prevents possible unintended actions caused by the updated limits Defau...

Page 1717: ...effect Before changing the limit it is recommended to set the service bit for this subcounter within the configured limits This prevents possible unintended actions caused by the updated limits Defau...

Page 1718: ...e effect Before changing the limit it is recommended to set the service bit for this subcounter within the configured limits This prevents possible unintended actions caused by the updated limits Defa...

Page 1719: ...ion taken if this watchdog is serviced before LOWER_LIMIT is reached LOWER_ACTION is ignored i e treated as NOTHING when a debugger is connected and or when the corresponding processor is in SLEEPDEEP...

Page 1720: ...ation of a periodic interrupt if this counter is not needed as a watchdog This field is ignored when LOWER_ACTION NOTHING or when UPPER_ACTION NOTHING 28 DEBUG_TRIGGER_EN RW R 0 Enables the trigger in...

Page 1721: ...e after the debugger is disconnected After the debugger is disconnected the LOWER_ACTION is ignored until after the first service This prevents an unintentional trigger of the LOWER_ACTION before the...

Page 1722: ...15 14 13 12 11 10 9 8 Name CNT 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 15 CNT RW A 0 Cur...

Page 1723: ...16 Bits 31 30 29 28 27 26 25 24 Name ENABLE 31 31 None 30 24 Bit fields Bits Name SW HW Default or Enum Description 0 ENABLED R RW 1 Indicates actual state of watchdog May lag ENABLE by up to three c...

Page 1724: ...when enabled i e ENABLE 1 and ENABLED 1 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name LOWER_LIMIT 7 0 Bits 15 14 13 12 11 10 9 8 Name LOWER_LIMIT 15 8 Bits 23 22 21 20 19 18 17 16 Name LOWER_...

Page 1725: ...n enabled i e ENABLE 1 and ENABLED 1 Default 0x8000 Bit field Table Bits 7 6 5 4 3 2 1 0 Name UPPER_LIMIT 7 0 Bits 15 14 13 12 11 10 9 8 Name UPPER_LIMIT 15 8 Bits 23 22 21 20 19 18 17 16 Name UPPER_L...

Page 1726: ...or when enabled i e ENABLE 1 and ENABLED 1 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name WARN_LIMIT 7 0 Bits 15 14 13 12 11 10 9 8 Name WARN_LIMIT 15 8 Bits 23 22 21 20 19 18 17 16 Name WARN_L...

Page 1727: ...CTION RW A 0 Action taken if this watchdog is serviced before LOWER_LIMIT is reached LOWER_ACTION is ignored i e treated as NOTHING when a debugger is connected and or when the chip is in DEEPSLEEP HI...

Page 1728: ...time it is halted 0 Pauses the counter whenever a debug probe is connected 1 Pauses the counter whenever a debug probe is connected and the trigger input is high 29 DPSLP_PAUSE RW A 0 Pauses runs this...

Page 1729: ...two clk_ilo0 cycles the LOWER_ACTION is ignored until after the first service after the debugger is disconnected This prevents an unintentional trigger of the LOWER_ACTION before the firmware realign...

Page 1730: ...Name CNT 15 8 Bits 23 22 21 20 19 18 17 16 Name CNT 23 16 Bits 31 30 29 28 27 26 25 24 Name CNT 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 31 CNT RW A 0 Current value of subcounte...

Page 1731: ...29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 1 WDT_LOCK RW A 3 Prohibits writing control and configuration registers related to this WDT when not equal 0...

Page 1732: ...8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 SERVICE RW1S RW1C 0 Services the watchdog This res...

Page 1733: ...8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 WDT RW1C A 0 WDT Interrupt Request...

Page 1734: ...Name None 7 1 WDT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 1735: ...forward the interrupt when 1 Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 WDT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29...

Page 1736: ...tion Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name None 7 1 WDT 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name Non...

Page 1737: ...ID7 0xF1000FDC FULL Peripheral Identification Register 7 SYSAP_ROMTABLE_PID0 0xF1000FE0 FULL Peripheral Identification Register 0 SYSAP_ROMTABLE_PID1 0xF1000FE4 FULL Peripheral Identification Register...

Page 1738: ...on Retained IsDeepSleep No Comment Default 0x1 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 2...

Page 1739: ...3 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 3 JEP_CONTINUATION R R...

Page 1740: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 1741: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 1742: ...epSleep No Comment Default 0x0 Bit field Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24...

Page 1743: ...Bit field Table Bits 7 6 5 4 3 2 1 0 Name PN_MIN 7 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits...

Page 1744: ...ID_MIN 7 4 PN_MAJ 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 1745: ...8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 JEPID_MAJ R R Undefined JEP106 ven...

Page 1746: ...me REV_AND 7 4 CM 3 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 1747: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name S...

Page 1748: ...7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name SW HW Default...

Page 1749: ...d Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name...

Page 1750: ...Table Bits 7 6 5 4 3 2 1 0 Name VALUE 7 0 Bits 15 14 13 12 11 10 9 8 Name VALUE 15 8 Bits 23 22 21 20 19 18 17 16 Name VALUE 23 16 Bits 31 30 29 28 27 26 25 24 Name VALUE 31 24 Bit fields Bits Name S...

Page 1751: ..._CNT0_INTR 0x40380070 FULL Interrupt request register TCPWM0_GRP0_CNT0_INTR_SET 0x40380074 FULL Interrupt set request register TCPWM0_GRP0_CNT0_INTR_MASK 0x40380078 FULL Interrupt mask register TCPWM0...

Page 1752: ...errupt request register TCPWM0_GRP0_CNT2_INTR_SET 0x40380174 FULL Interrupt set request register TCPWM0_GRP0_CNT2_INTR_MASK 0x40380178 FULL Interrupt mask register TCPWM0_GRP0_CNT2_INTR_MASKED 0x40380...

Page 1753: ...GRP0_CNT4_INTR_MASKED 0x4038027C FULL Interrupt masked request register 28 1 6 CNT 5 Register Name Address Permission Description TCPWM0_GRP0_CNT5_CTRL 0x40380280 FULL Counter control register Note AU...

Page 1754: ...tion TCPWM0_GRP0_CNT7_CTRL 0x40380380 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not available for this register TC...

Page 1755: ...DT_CNT_H is not available for this register TCPWM0_GRP0_CNT9_COUNTER 0x40380488 FULL Counter count register TCPWM0_GRP0_CNT9_CC0 0x40380490 FULL Counter compare capture 0 register TCPWM0_GRP0_CNT9_CC0...

Page 1756: ...re capture 1 register TCPWM0_GRP0_CNT11_CC1_BUFF 0x4038059C FULL Counter buffered compare capture 1 register TCPWM0_GRP0_CNT11_PERIOD 0x403805A0 FULL Counter period register TCPWM0_GRP0_CNT11_PERIOD_B...

Page 1757: ...ead time register Note DT_LINE_OUT_H DT_LINE_COMPL_OUT are not available for this register TCPWM0_GRP0_CNT13_TR_CMD 0x403806C0 FULL Counter trigger command register TCPWM0_GRP0_CNT13_TR_IN_SEL0 0x4038...

Page 1758: ..._IN_EDGE_SEL 0x403807CC FULL Counter input trigger edge selection register TCPWM0_GRP0_CNT15_TR_PWM_CTRL 0x403807D0 FULL Counter trigger PWM control register TCPWM0_GRP0_CNT15_TR_OUT_SEL 0x403807D4 FU...

Page 1759: ..._INTR_SET 0x403808F4 FULL Interrupt set request register TCPWM0_GRP0_CNT17_INTR_MASK 0x403808F8 FULL Interrupt mask register TCPWM0_GRP0_CNT17_INTR_MASKED 0x403808FC FULL Interrupt masked request regi...

Page 1760: ...ion TCPWM0_GRP0_CNT20_CTRL 0x40380A00 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not available for this register TC...

Page 1761: ...e DT_CNT_H is not available for this register TCPWM0_GRP0_CNT22_COUNTER 0x40380B08 FULL Counter count register TCPWM0_GRP0_CNT22_CC0 0x40380B10 FULL Counter compare capture 0 register TCPWM0_GRP0_CNT2...

Page 1762: ...re capture 1 register TCPWM0_GRP0_CNT24_CC1_BUFF 0x40380C1C FULL Counter buffered compare capture 1 register TCPWM0_GRP0_CNT24_PERIOD 0x40380C20 FULL Counter period register TCPWM0_GRP0_CNT24_PERIOD_B...

Page 1763: ...ead time register Note DT_LINE_OUT_H DT_LINE_COMPL_OUT are not available for this register TCPWM0_GRP0_CNT26_TR_CMD 0x40380D40 FULL Counter trigger command register TCPWM0_GRP0_CNT26_TR_IN_SEL0 0x4038...

Page 1764: ..._IN_EDGE_SEL 0x40380E4C FULL Counter input trigger edge selection register TCPWM0_GRP0_CNT28_TR_PWM_CTRL 0x40380E50 FULL Counter trigger PWM control register TCPWM0_GRP0_CNT28_TR_OUT_SEL 0x40380E54 FU...

Page 1765: ..._INTR_SET 0x40380F74 FULL Interrupt set request register TCPWM0_GRP0_CNT30_INTR_MASK 0x40380F78 FULL Interrupt mask register TCPWM0_GRP0_CNT30_INTR_MASKED 0x40380F7C FULL Interrupt masked request regi...

Page 1766: ...ion TCPWM0_GRP0_CNT33_CTRL 0x40381080 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not available for this register TC...

Page 1767: ...e DT_CNT_H is not available for this register TCPWM0_GRP0_CNT35_COUNTER 0x40381188 FULL Counter count register TCPWM0_GRP0_CNT35_CC0 0x40381190 FULL Counter compare capture 0 register TCPWM0_GRP0_CNT3...

Page 1768: ...re capture 1 register TCPWM0_GRP0_CNT37_CC1_BUFF 0x4038129C FULL Counter buffered compare capture 1 register TCPWM0_GRP0_CNT37_PERIOD 0x403812A0 FULL Counter period register TCPWM0_GRP0_CNT37_PERIOD_B...

Page 1769: ...ead time register Note DT_LINE_OUT_H DT_LINE_COMPL_OUT are not available for this register TCPWM0_GRP0_CNT39_TR_CMD 0x403813C0 FULL Counter trigger command register TCPWM0_GRP0_CNT39_TR_IN_SEL0 0x4038...

Page 1770: ..._IN_EDGE_SEL 0x403814CC FULL Counter input trigger edge selection register TCPWM0_GRP0_CNT41_TR_PWM_CTRL 0x403814D0 FULL Counter trigger PWM control register TCPWM0_GRP0_CNT41_TR_OUT_SEL 0x403814D4 FU...

Page 1771: ..._INTR_SET 0x403815F4 FULL Interrupt set request register TCPWM0_GRP0_CNT43_INTR_MASK 0x403815F8 FULL Interrupt mask register TCPWM0_GRP0_CNT43_INTR_MASKED 0x403815FC FULL Interrupt masked request regi...

Page 1772: ...ion TCPWM0_GRP0_CNT46_CTRL 0x40381700 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not available for this register TC...

Page 1773: ...e DT_CNT_H is not available for this register TCPWM0_GRP0_CNT48_COUNTER 0x40381808 FULL Counter count register TCPWM0_GRP0_CNT48_CC0 0x40381810 FULL Counter compare capture 0 register TCPWM0_GRP0_CNT4...

Page 1774: ...re capture 1 register TCPWM0_GRP0_CNT50_CC1_BUFF 0x4038191C FULL Counter buffered compare capture 1 register TCPWM0_GRP0_CNT50_PERIOD 0x40381920 FULL Counter period register TCPWM0_GRP0_CNT50_PERIOD_B...

Page 1775: ...ead time register Note DT_LINE_OUT_H DT_LINE_COMPL_OUT are not available for this register TCPWM0_GRP0_CNT52_TR_CMD 0x40381A40 FULL Counter trigger command register TCPWM0_GRP0_CNT52_TR_IN_SEL0 0x4038...

Page 1776: ..._IN_EDGE_SEL 0x40381B4C FULL Counter input trigger edge selection register TCPWM0_GRP0_CNT54_TR_PWM_CTRL 0x40381B50 FULL Counter trigger PWM control register TCPWM0_GRP0_CNT54_TR_OUT_SEL 0x40381B54 FU...

Page 1777: ..._INTR_SET 0x40381C74 FULL Interrupt set request register TCPWM0_GRP0_CNT56_INTR_MASK 0x40381C78 FULL Interrupt mask register TCPWM0_GRP0_CNT56_INTR_MASKED 0x40381C7C FULL Interrupt masked request regi...

Page 1778: ...ion TCPWM0_GRP0_CNT59_CTRL 0x40381D80 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not available for this register TC...

Page 1779: ...e DT_CNT_H is not available for this register TCPWM0_GRP0_CNT61_COUNTER 0x40381E88 FULL Counter count register TCPWM0_GRP0_CNT61_CC0 0x40381E90 FULL Counter compare capture 0 register TCPWM0_GRP0_CNT6...

Page 1780: ...register TCPWM0_GRP1_CNT0_LINE_SEL_BUFF 0x4038802C FULL Counter buffered line selection register TCPWM0_GRP1_CNT0_DT 0x40388030 FULL Counter PWM dead time register TCPWM0_GRP1_CNT0_TR_CMD 0x40388040 F...

Page 1781: ...set request register TCPWM0_GRP1_CNT2_INTR_MASK 0x40388178 FULL Interrupt mask register TCPWM0_GRP1_CNT2_INTR_MASKED 0x4038817C FULL Interrupt masked request register 28 2 4 CNT 3 Register Name Addres...

Page 1782: ...82A8 FULL Counter line selection register TCPWM0_GRP1_CNT5_LINE_SEL_BUFF 0x403882AC FULL Counter buffered line selection register TCPWM0_GRP1_CNT5_DT 0x403882B0 FULL Counter PWM dead time register TCP...

Page 1783: ...er TCPWM0_GRP1_CNT7_INTR_MASKED 0x403883FC FULL Interrupt masked request register 28 2 9 CNT 8 Register Name Address Permission Description TCPWM0_GRP1_CNT8_CTRL 0x40388400 FULL Counter control regist...

Page 1784: ...r buffered line selection register TCPWM0_GRP1_CNT10_DT 0x40388530 FULL Counter PWM dead time register TCPWM0_GRP1_CNT10_TR_CMD 0x40388540 FULL Counter trigger command register TCPWM0_GRP1_CNT10_TR_IN...

Page 1785: ...ister TCPWM0_GRP2_CNT0_INTR 0x40390070 FULL Interrupt request register TCPWM0_GRP2_CNT0_INTR_SET 0x40390074 FULL Interrupt set request register TCPWM0_GRP2_CNT0_INTR_MASK 0x40390078 FULL Interrupt mas...

Page 1786: ...CNT2_INTR_MASK 0x40390178 FULL Interrupt mask register TCPWM0_GRP2_CNT2_INTR_MASKED 0x4039017C FULL Interrupt masked request register 28 3 4 CNT 3 Register Name Address Permission Description TCPWM0_G...

Page 1787: ...tion TCPWM0_GRP2_CNT5_CTRL 0x40390280 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not available for this register TC...

Page 1788: ...me Address Permission Description TCPWM0_GRP2_CNT7_CTRL 0x40390380 FULL Counter control register Note AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN CC1_MATCH_DOWN_EN are not a...

Page 1789: ...0 PWM _STOP_ON _KILL 9 9 PWM_IMM _KILL 8 8 Bits 23 22 21 20 19 18 17 16 Name None 23 22 QUAD_ENCODING _MODE 21 20 None 19 19 ONE _SHOT 18 18 UP_DOWN_MODE 17 16 Bits 31 30 29 28 27 26 25 24 Name ENABLE...

Page 1790: ...ptures when COUNTER equals 0 or 0xffff The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff 3 AUTO_RELOAD_LINE _SEL RW R 0 Specifies switching of the LINE_SEL and LINE_BU...

Page 1791: ...mmediate kill activation Immediately deactivates the dt_line_out and dt_line_compl_out signals This field has a function in PWM PWM_DT and PWM_PR modes only 9 PWM_STOP_ON_KILL RW R 0 Specifies whether...

Page 1792: ...nter is disabled the PWM outputs line_out and line_compl_out are driven by the TCPWM When the counter is disabled or stopped upon a stop event the PWM output line_out is driven as a fixed 1 and the PW...

Page 1793: ...event is generated This mode is 100 percent backward compatible with previous TCPWM quadrature behavior QUAD_RANGE0_CMP 1 In QUAD mode this setting selects the QUAD_RANGE0_CMP mode with the following...

Page 1794: ...ncoder moves back and forth around start position It is recommended to not use the tc interrupt in this mode QUAD_RANGE1_CMP 3 In QUAD mode this setting selects the QUAD_RANGE1_CMP mode The behavior i...

Page 1795: ...avior in debug mode 0 The counter operation continues in debug mode 1 The counter operation freezes in debug mode 31 ENABLED RW R 0 Counter Enable 0 counter disabled 1 counter enabled Counter static c...

Page 1796: ...10 10 TR _CAPTUR E1 9 9 TR_START 8 8 Bits 23 22 21 20 19 18 17 16 Name DT_CNT_L 23 16 Bits 31 30 29 28 27 26 25 24 Name DT_CNT_H 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 DOWN R R...

Page 1797: ...nter is used for dead time insertion 8bit dead time counter or low byte of 16 bit dead time counter In all other modes this counter is used for pre scaling the selected counter clock PWM_DT mode can N...

Page 1798: ...3 2 1 0 Name COUNTER 7 0 Bits 15 14 13 12 11 10 9 8 Name COUNTER 15 8 Bits 23 22 21 20 19 18 17 16 Name COUNTER 23 16 Bits 31 30 29 28 27 26 25 24 Name COUNTER 31 24 Bit fields Bits Name SW HW Default...

Page 1799: ...ld Table Bits 7 6 5 4 3 2 1 0 Name CC 7 0 Bits 15 14 13 12 11 10 9 8 Name CC 15 8 Bits 23 22 21 20 19 18 17 16 Name CC 23 16 Bits 31 30 29 28 27 26 25 24 Name CC 31 24 Bit fields Bits Name SW HW Defau...

Page 1800: ...t Default 0xFFFFFFFF Bit field Table Bits 7 6 5 4 3 2 1 0 Name CC 7 0 Bits 15 14 13 12 11 10 9 8 Name CC 15 8 Bits 23 22 21 20 19 18 17 16 Name CC 23 16 Bits 31 30 29 28 27 26 25 24 Name CC 31 24 Bit...

Page 1801: ...ld Table Bits 7 6 5 4 3 2 1 0 Name CC 7 0 Bits 15 14 13 12 11 10 9 8 Name CC 15 8 Bits 23 22 21 20 19 18 17 16 Name CC 23 16 Bits 31 30 29 28 27 26 25 24 Name CC 31 24 Bit fields Bits Name SW HW Defau...

Page 1802: ...Default 0xFFFFFFFF Bit field Table Bits 7 6 5 4 3 2 1 0 Name CC 7 0 Bits 15 14 13 12 11 10 9 8 Name CC 15 8 Bits 23 22 21 20 19 18 17 16 Name CC 23 16 Bits 31 30 29 28 27 26 25 24 Name CC 31 24 Bit f...

Page 1803: ...Name PERIOD 7 0 Bits 15 14 13 12 11 10 9 8 Name PERIOD 15 8 Bits 23 22 21 20 19 18 17 16 Name PERIOD 23 16 Bits 31 30 29 28 27 26 25 24 Name PERIOD 31 24 Bit fields Bits Name SW HW Default or Enum Des...

Page 1804: ...a tap of the shift register which can be feed back to the MSB via an XOR tree Examples for GRP_CNT_WIDTH 16 Maximum length 16bit LFSR polynomial x 16 x 14 x 13 x 11 1 taps 0 2 3 5 PERIOD 0x002d perio...

Page 1805: ...his selection can be further modified by the stop kill logic and line_out polarity setting CTRL QUAD_ENCODING_MODE 0 L 0 fixed 0 H 1 fixed 1 PWM 2 PWM signal line PWM_INV 3 inverted PWM signal line Z...

Page 1806: ...line Z 4 The output line_compl_out is not driven by the TCPWM Instead the port default level configuration applies e g Z high impedance Note This is realized by driving the output line_compl_out_en t...

Page 1807: ...28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 2 OUT_SEL RW RW 2 Buffer for LINE_SEL OUT_SEL Can be exchanged with LINE_SEL LINE_OUT_SEL on a terminal count e...

Page 1808: ...control is set to 1 Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating line_out and line_compl_out DIVBY1 0 Divide by 1...

Page 1809: ...ompl_out amount of dead time cycles in the counter clock domain In all other modes this field has no effect Note This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set...

Page 1810: ...one 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 CAPTURE0 RW1S RW1C 0 SW capture 0 trigger When written with 1 a capture 0 trigger is generated and the HW sets the field to 0 when th...

Page 1811: ..._in connected to all counters selected In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts 8 15 COUNT_SEL RW...

Page 1812: ...temporarily block the PWM outputs PWM_STOP_ON_KILL is 0 or stop the functionality PWM_STOP_ON_KILL is 1 For the PWM and PWM_DT modes the blocking of the output signals can be asynchronous STOP_EDGE sh...

Page 1813: ...Name START_SEL 7 0 Bits 15 14 13 12 11 10 9 8 Name CAPTURE1_SEL 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or En...

Page 1814: ...OUNT_EDGE RW R 3 A counter event will increase or decrease the counter by 1 RISING_EDGE 0 Rising edge Any rising edge generates an event FALLING_EDGE 1 Falling edge Any falling edge generates an event...

Page 1815: ...ling edge generates an event ANY_EDGE 2 Rising AND falling edge Any odd amount of edges generates an event NO_EDGE_DET 3 No edge detection use trigger as is 10 11 CAPTURE1_EDGE RW R 3 A capture 1 even...

Page 1816: ...ul for center aligned pulse width modulation To generate a duty cycle of 0 percent the counter CC0 register should be set to 0 For a 100 percent duty cycle the counter CC0 register should be set to la...

Page 1817: ...Technical Reference Manual 002 29852 Rev B Bits Name SW HW Default or Enum Description NO_CHANGE 3 No Change 1817 2022 04 18 TRAVEO T2G Automotive MCU TVII B E 4M body controller entry registers...

Page 1818: ...rate the output trigger 0 Default setting selects the terminal count event OVERFLOW 0 Overflow event UNDERFLOW 1 Underflow event TC 2 Terminal count event default selection CC0_MATCH 3 Compare match 0...

Page 1819: ...3 CC1 _MATCH 2 2 CC0 _MATCH 1 1 TC 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW De...

Page 1820: ...TCH 1 1 TC 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Descriptio...

Page 1821: ...4 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit fields Bits Name SW HW Default or Enum Description 0 TC RW R 0 Mask bit f...

Page 1822: ...5 4 3 2 1 0 Name None 7 3 CC1 _MATCH 2 2 CC0 _MATCH 1 1 TC 0 0 Bits 15 14 13 12 11 10 9 8 Name None 15 8 Bits 23 22 21 20 19 18 17 16 Name None 23 16 Bits 31 30 29 28 27 26 25 24 Name None 31 24 Bit...

Page 1823: ...l 002 29852Rev B 2022 04 13 1823 TRAVEO T2G Automotive MCU TVII B E 4M body controller entry registers References References 1 002 19314 TRAVEO T2G Automotive MCU body controller entry architecture te...

Page 1824: ...p included 3 Register Structure with links all homepage notes are moved down 4 Some fixes which were present in the previous revision in spec system Missing contents due to parser errors CDT 343334 5...

Page 1825: ...quirements norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications The data contained in this document is exclusively intended...

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